maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
llvm-project/llvm/test/CodeGen/AMDGPU/global-saddr-atomics.ll

Ignoring revisions in .git-blame-ignore-revs. Click here to bypass and see the normal blame view.

2874 lines
122 KiB
LLVM
Raw Normal View History

AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9 %s
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GCN,GFX10 %s
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; Test using saddr addressing mode of global_* flat atomic instructions.
define amdgpu_ps void @global_xchg_saddr_i32_nortn(i8 addrspace(1)* inreg %sbase, i32 %voffset, i32 %data) {
; GFX9-LABEL: global_xchg_saddr_i32_nortn:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_swap v0, v1, s[2:3]
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: s_endpgm
;
; GFX10-LABEL: global_xchg_saddr_i32_nortn:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_swap v0, v1, s[2:3]
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%cast.gep0 = bitcast i8 addrspace(1)* %gep0 to i32 addrspace(1)*
%unused = atomicrmw xchg i32 addrspace(1)* %cast.gep0, i32 %data seq_cst
ret void
}
; Maximum positive offset on gfx10
define amdgpu_ps void @global_xchg_saddr_i32_nortn_offset_2047(i8 addrspace(1)* inreg %sbase, i32 %voffset, i32 %data) {
; GFX9-LABEL: global_xchg_saddr_i32_nortn_offset_2047:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_swap v0, v1, s[2:3] offset:2047
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: s_endpgm
;
; GFX10-LABEL: global_xchg_saddr_i32_nortn_offset_2047:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_swap v0, v1, s[2:3] offset:2047
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 2047
%cast.gep1 = bitcast i8 addrspace(1)* %gep1 to i32 addrspace(1)*
%unused = atomicrmw xchg i32 addrspace(1)* %cast.gep1, i32 %data seq_cst
ret void
}
; Maximum negative offset on gfx10
define amdgpu_ps void @global_xchg_saddr_i32_nortn_offset_neg2048(i8 addrspace(1)* inreg %sbase, i32 %voffset, i32 %data) {
; GFX9-LABEL: global_xchg_saddr_i32_nortn_offset_neg2048:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_swap v0, v1, s[2:3] offset:-2048
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: s_endpgm
;
; GFX10-LABEL: global_xchg_saddr_i32_nortn_offset_neg2048:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_swap v0, v1, s[2:3] offset:-2048
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -2048
%cast.gep1 = bitcast i8 addrspace(1)* %gep1 to i32 addrspace(1)*
%unused = atomicrmw xchg i32 addrspace(1)* %cast.gep1, i32 %data seq_cst
ret void
}
define amdgpu_ps float @global_xchg_saddr_i32_rtn(i8 addrspace(1)* inreg %sbase, i32 %voffset, i32 %data) {
; GFX9-LABEL: global_xchg_saddr_i32_rtn:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_swap v0, v0, v1, s[2:3] glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: global_xchg_saddr_i32_rtn:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_swap v0, v0, v1, s[2:3] glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%cast.gep0 = bitcast i8 addrspace(1)* %gep0 to i32 addrspace(1)*
%rtn = atomicrmw xchg i32 addrspace(1)* %cast.gep0, i32 %data seq_cst
%cast.rtn = bitcast i32 %rtn to float
ret float %cast.rtn
}
define amdgpu_ps float @global_xchg_saddr_i32_rtn_2048(i8 addrspace(1)* inreg %sbase, i32 %voffset, i32 %data) {
; GFX9-LABEL: global_xchg_saddr_i32_rtn_2048:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_swap v0, v0, v1, s[2:3] offset:2048 glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: global_xchg_saddr_i32_rtn_2048:
; GFX10: ; %bb.0:
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: v_add_co_u32_e64 v0, s[0:1], s2, v0
; GFX10-NEXT: v_add_co_ci_u32_e64 v3, s[0:1], s3, 0, s[0:1]
; GFX10-NEXT: v_add_co_u32_e64 v2, vcc, 0x800, v0
; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc, 0, v3, vcc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_atomic_swap v0, v[2:3], v1, off glc
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 2048
%cast.gep1 = bitcast i8 addrspace(1)* %gep1 to i32 addrspace(1)*
%rtn = atomicrmw xchg i32 addrspace(1)* %cast.gep1, i32 %data seq_cst
%cast.rtn = bitcast i32 %rtn to float
ret float %cast.rtn
}
define amdgpu_ps float @global_xchg_saddr_i32_rtn_neg2048(i8 addrspace(1)* inreg %sbase, i32 %voffset, i32 %data) {
; GFX9-LABEL: global_xchg_saddr_i32_rtn_neg2048:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_swap v0, v0, v1, s[2:3] offset:-2048 glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: global_xchg_saddr_i32_rtn_neg2048:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_swap v0, v0, v1, s[2:3] offset:-2048 glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -2048
%cast.gep1 = bitcast i8 addrspace(1)* %gep1 to i32 addrspace(1)*
%rtn = atomicrmw xchg i32 addrspace(1)* %cast.gep1, i32 %data seq_cst
%cast.rtn = bitcast i32 %rtn to float
ret float %cast.rtn
}
; --------------------------------------------------------------------------------
; Uniformity edge cases
; --------------------------------------------------------------------------------
@ptr.in.lds = internal addrspace(3) global i8 addrspace(1)* undef
; Base pointer is uniform, but also in VGPRs
define amdgpu_ps float @global_xchg_saddr_uniform_ptr_in_vgprs_rtn(i32 %voffset, i32 %data) {
; GFX9-LABEL: global_xchg_saddr_uniform_ptr_in_vgprs_rtn:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_mov_b32_e32 v2, 0
; GFX9-NEXT: ds_read_b64 v[2:3], v2
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: v_readfirstlane_b32 s0, v2
; GFX9-NEXT: v_readfirstlane_b32 s1, v3
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
[AMDGPU] Avoid inserting noops during scheduling Passes that are run after the post-RA scheduler may insert instructions like waitcnt which eliminate the need for certain noops. After this patch the scheduler is still aware of possible latency from hazards but noops will not be inserted until the dedicated hazard recognizer pass is run. Depends on D89753. Reviewed By: foad Differential Revision: https://reviews.llvm.org/D89754
2020-10-20 07:54:24 +08:00
; GFX9-NEXT: s_nop 3
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_swap v0, v0, v1, s[0:1] glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: global_xchg_saddr_uniform_ptr_in_vgprs_rtn:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_mov_b32_e32 v2, 0
; GFX10-NEXT: ds_read_b64 v[2:3], v2
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: v_readfirstlane_b32 s0, v2
; GFX10-NEXT: v_readfirstlane_b32 s1, v3
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
[AMDGPU] Avoid inserting noops during scheduling Passes that are run after the post-RA scheduler may insert instructions like waitcnt which eliminate the need for certain noops. After this patch the scheduler is still aware of possible latency from hazards but noops will not be inserted until the dedicated hazard recognizer pass is run. Depends on D89753. Reviewed By: foad Differential Revision: https://reviews.llvm.org/D89754
2020-10-20 07:54:24 +08:00
; GFX10-NEXT: s_nop 2
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_swap v0, v0, v1, s[0:1] glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: ; return to shader part epilog
%sbase = load i8 addrspace(1)*, i8 addrspace(1)* addrspace(3)* @ptr.in.lds
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%cast.gep0 = bitcast i8 addrspace(1)* %gep0 to i32 addrspace(1)*
%rtn = atomicrmw xchg i32 addrspace(1)* %cast.gep0, i32 %data seq_cst
%cast.rtn = bitcast i32 %rtn to float
ret float %cast.rtn
}
; Base pointer is uniform, but also in VGPRs, with imm offset
define amdgpu_ps float @global_xchg_saddr_uniform_ptr_in_vgprs_rtn_immoffset(i32 %voffset, i32 %data) {
; GFX9-LABEL: global_xchg_saddr_uniform_ptr_in_vgprs_rtn_immoffset:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_mov_b32_e32 v2, 0
; GFX9-NEXT: ds_read_b64 v[2:3], v2
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: v_readfirstlane_b32 s0, v2
; GFX9-NEXT: v_readfirstlane_b32 s1, v3
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
[AMDGPU] Avoid inserting noops during scheduling Passes that are run after the post-RA scheduler may insert instructions like waitcnt which eliminate the need for certain noops. After this patch the scheduler is still aware of possible latency from hazards but noops will not be inserted until the dedicated hazard recognizer pass is run. Depends on D89753. Reviewed By: foad Differential Revision: https://reviews.llvm.org/D89754
2020-10-20 07:54:24 +08:00
; GFX9-NEXT: s_nop 3
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_swap v0, v0, v1, s[0:1] offset:42 glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: global_xchg_saddr_uniform_ptr_in_vgprs_rtn_immoffset:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_mov_b32_e32 v2, 0
; GFX10-NEXT: ds_read_b64 v[2:3], v2
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: v_readfirstlane_b32 s0, v2
; GFX10-NEXT: v_readfirstlane_b32 s1, v3
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
[AMDGPU] Avoid inserting noops during scheduling Passes that are run after the post-RA scheduler may insert instructions like waitcnt which eliminate the need for certain noops. After this patch the scheduler is still aware of possible latency from hazards but noops will not be inserted until the dedicated hazard recognizer pass is run. Depends on D89753. Reviewed By: foad Differential Revision: https://reviews.llvm.org/D89754
2020-10-20 07:54:24 +08:00
; GFX10-NEXT: s_nop 2
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_swap v0, v0, v1, s[0:1] offset:42 glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: ; return to shader part epilog
%sbase = load i8 addrspace(1)*, i8 addrspace(1)* addrspace(3)* @ptr.in.lds
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 42
%cast.gep1 = bitcast i8 addrspace(1)* %gep1 to i32 addrspace(1)*
%rtn = atomicrmw xchg i32 addrspace(1)* %cast.gep1, i32 %data seq_cst
%cast.rtn = bitcast i32 %rtn to float
ret float %cast.rtn
}
; Base pointer is uniform, but also in VGPRs
define amdgpu_ps void @global_xchg_saddr_uniform_ptr_in_vgprs_nortn(i32 %voffset, i32 %data) {
; GFX9-LABEL: global_xchg_saddr_uniform_ptr_in_vgprs_nortn:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_mov_b32_e32 v2, 0
; GFX9-NEXT: ds_read_b64 v[2:3], v2
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: v_readfirstlane_b32 s0, v2
; GFX9-NEXT: v_readfirstlane_b32 s1, v3
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
[AMDGPU] Avoid inserting noops during scheduling Passes that are run after the post-RA scheduler may insert instructions like waitcnt which eliminate the need for certain noops. After this patch the scheduler is still aware of possible latency from hazards but noops will not be inserted until the dedicated hazard recognizer pass is run. Depends on D89753. Reviewed By: foad Differential Revision: https://reviews.llvm.org/D89754
2020-10-20 07:54:24 +08:00
; GFX9-NEXT: s_nop 3
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_swap v0, v1, s[0:1]
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: s_endpgm
;
; GFX10-LABEL: global_xchg_saddr_uniform_ptr_in_vgprs_nortn:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_mov_b32_e32 v2, 0
; GFX10-NEXT: ds_read_b64 v[2:3], v2
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: v_readfirstlane_b32 s0, v2
; GFX10-NEXT: v_readfirstlane_b32 s1, v3
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
[AMDGPU] Avoid inserting noops during scheduling Passes that are run after the post-RA scheduler may insert instructions like waitcnt which eliminate the need for certain noops. After this patch the scheduler is still aware of possible latency from hazards but noops will not be inserted until the dedicated hazard recognizer pass is run. Depends on D89753. Reviewed By: foad Differential Revision: https://reviews.llvm.org/D89754
2020-10-20 07:54:24 +08:00
; GFX10-NEXT: s_nop 2
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_swap v0, v1, s[0:1]
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: s_endpgm
%sbase = load i8 addrspace(1)*, i8 addrspace(1)* addrspace(3)* @ptr.in.lds
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%cast.gep0 = bitcast i8 addrspace(1)* %gep0 to i32 addrspace(1)*
%unused = atomicrmw xchg i32 addrspace(1)* %cast.gep0, i32 %data seq_cst
ret void
}
; Base pointer is uniform, but also in VGPRs, with imm offset
define amdgpu_ps void @global_xchg_saddr_uniform_ptr_in_vgprs_nortn_immoffset(i32 %voffset, i32 %data) {
; GFX9-LABEL: global_xchg_saddr_uniform_ptr_in_vgprs_nortn_immoffset:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_mov_b32_e32 v2, 0
; GFX9-NEXT: ds_read_b64 v[2:3], v2
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: v_readfirstlane_b32 s0, v2
; GFX9-NEXT: v_readfirstlane_b32 s1, v3
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
[AMDGPU] Avoid inserting noops during scheduling Passes that are run after the post-RA scheduler may insert instructions like waitcnt which eliminate the need for certain noops. After this patch the scheduler is still aware of possible latency from hazards but noops will not be inserted until the dedicated hazard recognizer pass is run. Depends on D89753. Reviewed By: foad Differential Revision: https://reviews.llvm.org/D89754
2020-10-20 07:54:24 +08:00
; GFX9-NEXT: s_nop 3
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_swap v0, v1, s[0:1] offset:42
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: s_endpgm
;
; GFX10-LABEL: global_xchg_saddr_uniform_ptr_in_vgprs_nortn_immoffset:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_mov_b32_e32 v2, 0
; GFX10-NEXT: ds_read_b64 v[2:3], v2
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: v_readfirstlane_b32 s0, v2
; GFX10-NEXT: v_readfirstlane_b32 s1, v3
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
[AMDGPU] Avoid inserting noops during scheduling Passes that are run after the post-RA scheduler may insert instructions like waitcnt which eliminate the need for certain noops. After this patch the scheduler is still aware of possible latency from hazards but noops will not be inserted until the dedicated hazard recognizer pass is run. Depends on D89753. Reviewed By: foad Differential Revision: https://reviews.llvm.org/D89754
2020-10-20 07:54:24 +08:00
; GFX10-NEXT: s_nop 2
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_swap v0, v1, s[0:1] offset:42
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: s_endpgm
%sbase = load i8 addrspace(1)*, i8 addrspace(1)* addrspace(3)* @ptr.in.lds
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 42
%cast.gep1 = bitcast i8 addrspace(1)* %gep1 to i32 addrspace(1)*
%unused = atomicrmw xchg i32 addrspace(1)* %cast.gep1, i32 %data seq_cst
ret void
}
; --------------------------------------------------------------------------------
; All atomicrmw ops
; --------------------------------------------------------------------------------
; --------------------------------------------------------------------------------
; atomicrmw xchg
; --------------------------------------------------------------------------------
define amdgpu_ps <2 x float> @global_xchg_saddr_i64_rtn(i8 addrspace(1)* inreg %sbase, i32 %voffset, i64 %data) {
; GFX9-LABEL: global_xchg_saddr_i64_rtn:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_swap_x2 v[0:1], v0, v[1:2], s[2:3] glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: global_xchg_saddr_i64_rtn:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_swap_x2 v[0:1], v0, v[1:2], s[2:3] glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%cast.gep0 = bitcast i8 addrspace(1)* %gep0 to i64 addrspace(1)*
%rtn = atomicrmw xchg i64 addrspace(1)* %cast.gep0, i64 %data seq_cst
%cast.rtn = bitcast i64 %rtn to <2 x float>
ret <2 x float> %cast.rtn
}
define amdgpu_ps <2 x float> @global_xchg_saddr_i64_rtn_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, i64 %data) {
; GFX9-LABEL: global_xchg_saddr_i64_rtn_neg128:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_swap_x2 v[0:1], v0, v[1:2], s[2:3] offset:-128 glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: global_xchg_saddr_i64_rtn_neg128:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_swap_x2 v[0:1], v0, v[1:2], s[2:3] offset:-128 glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128
%cast.gep1 = bitcast i8 addrspace(1)* %gep1 to i64 addrspace(1)*
%rtn = atomicrmw xchg i64 addrspace(1)* %cast.gep1, i64 %data seq_cst
%cast.rtn = bitcast i64 %rtn to <2 x float>
ret <2 x float> %cast.rtn
}
define amdgpu_ps void @global_xchg_saddr_i64_nortn(i8 addrspace(1)* inreg %sbase, i32 %voffset, i64 %data) {
; GFX9-LABEL: global_xchg_saddr_i64_nortn:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_swap_x2 v0, v[1:2], s[2:3]
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: s_endpgm
;
; GFX10-LABEL: global_xchg_saddr_i64_nortn:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_swap_x2 v0, v[1:2], s[2:3]
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%cast.gep0 = bitcast i8 addrspace(1)* %gep0 to i64 addrspace(1)*
%unused = atomicrmw xchg i64 addrspace(1)* %cast.gep0, i64 %data seq_cst
ret void
}
define amdgpu_ps void @global_xchg_saddr_i64_nortn_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, i64 %data) {
; GFX9-LABEL: global_xchg_saddr_i64_nortn_neg128:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_swap_x2 v0, v[1:2], s[2:3] offset:-128
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: s_endpgm
;
; GFX10-LABEL: global_xchg_saddr_i64_nortn_neg128:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_swap_x2 v0, v[1:2], s[2:3] offset:-128
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128
%cast.gep1 = bitcast i8 addrspace(1)* %gep1 to i64 addrspace(1)*
%unused = atomicrmw xchg i64 addrspace(1)* %cast.gep1, i64 %data seq_cst
ret void
}
; --------------------------------------------------------------------------------
; atomicrmw add
; --------------------------------------------------------------------------------
define amdgpu_ps float @global_add_saddr_i32_rtn(i8 addrspace(1)* inreg %sbase, i32 %voffset, i32 %data) {
; GFX9-LABEL: global_add_saddr_i32_rtn:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_add v0, v0, v1, s[2:3] glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: global_add_saddr_i32_rtn:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_add v0, v0, v1, s[2:3] glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%cast.gep0 = bitcast i8 addrspace(1)* %gep0 to i32 addrspace(1)*
%rtn = atomicrmw add i32 addrspace(1)* %cast.gep0, i32 %data seq_cst
%cast.rtn = bitcast i32 %rtn to float
ret float %cast.rtn
}
define amdgpu_ps float @global_add_saddr_i32_rtn_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, i32 %data) {
; GFX9-LABEL: global_add_saddr_i32_rtn_neg128:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_add v0, v0, v1, s[2:3] offset:-128 glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: global_add_saddr_i32_rtn_neg128:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_add v0, v0, v1, s[2:3] offset:-128 glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128
%cast.gep1 = bitcast i8 addrspace(1)* %gep1 to i32 addrspace(1)*
%rtn = atomicrmw add i32 addrspace(1)* %cast.gep1, i32 %data seq_cst
%cast.rtn = bitcast i32 %rtn to float
ret float %cast.rtn
}
define amdgpu_ps void @global_add_saddr_i32_nortn(i8 addrspace(1)* inreg %sbase, i32 %voffset, i32 %data) {
; GFX9-LABEL: global_add_saddr_i32_nortn:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_add v0, v1, s[2:3]
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: s_endpgm
;
; GFX10-LABEL: global_add_saddr_i32_nortn:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_add v0, v1, s[2:3]
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%cast.gep0 = bitcast i8 addrspace(1)* %gep0 to i32 addrspace(1)*
%unused = atomicrmw add i32 addrspace(1)* %cast.gep0, i32 %data seq_cst
ret void
}
define amdgpu_ps void @global_add_saddr_i32_nortn_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, i32 %data) {
; GFX9-LABEL: global_add_saddr_i32_nortn_neg128:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_add v0, v1, s[2:3] offset:-128
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: s_endpgm
;
; GFX10-LABEL: global_add_saddr_i32_nortn_neg128:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_add v0, v1, s[2:3] offset:-128
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128
%cast.gep1 = bitcast i8 addrspace(1)* %gep1 to i32 addrspace(1)*
%unused = atomicrmw add i32 addrspace(1)* %cast.gep1, i32 %data seq_cst
ret void
}
define amdgpu_ps <2 x float> @global_add_saddr_i64_rtn(i8 addrspace(1)* inreg %sbase, i32 %voffset, i64 %data) {
; GFX9-LABEL: global_add_saddr_i64_rtn:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_add_x2 v[0:1], v0, v[1:2], s[2:3] glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: global_add_saddr_i64_rtn:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_add_x2 v[0:1], v0, v[1:2], s[2:3] glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%cast.gep0 = bitcast i8 addrspace(1)* %gep0 to i64 addrspace(1)*
%rtn = atomicrmw add i64 addrspace(1)* %cast.gep0, i64 %data seq_cst
%cast.rtn = bitcast i64 %rtn to <2 x float>
ret <2 x float> %cast.rtn
}
define amdgpu_ps <2 x float> @global_add_saddr_i64_rtn_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, i64 %data) {
; GFX9-LABEL: global_add_saddr_i64_rtn_neg128:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_add_x2 v[0:1], v0, v[1:2], s[2:3] offset:-128 glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: global_add_saddr_i64_rtn_neg128:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_add_x2 v[0:1], v0, v[1:2], s[2:3] offset:-128 glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128
%cast.gep1 = bitcast i8 addrspace(1)* %gep1 to i64 addrspace(1)*
%rtn = atomicrmw add i64 addrspace(1)* %cast.gep1, i64 %data seq_cst
%cast.rtn = bitcast i64 %rtn to <2 x float>
ret <2 x float> %cast.rtn
}
define amdgpu_ps void @global_add_saddr_i64_nortn(i8 addrspace(1)* inreg %sbase, i32 %voffset, i64 %data) {
; GFX9-LABEL: global_add_saddr_i64_nortn:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_add_x2 v0, v[1:2], s[2:3]
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: s_endpgm
;
; GFX10-LABEL: global_add_saddr_i64_nortn:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_add_x2 v0, v[1:2], s[2:3]
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%cast.gep0 = bitcast i8 addrspace(1)* %gep0 to i64 addrspace(1)*
%unused = atomicrmw add i64 addrspace(1)* %cast.gep0, i64 %data seq_cst
ret void
}
define amdgpu_ps void @global_add_saddr_i64_nortn_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, i64 %data) {
; GFX9-LABEL: global_add_saddr_i64_nortn_neg128:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_add_x2 v0, v[1:2], s[2:3] offset:-128
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: s_endpgm
;
; GFX10-LABEL: global_add_saddr_i64_nortn_neg128:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_add_x2 v0, v[1:2], s[2:3] offset:-128
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128
%cast.gep1 = bitcast i8 addrspace(1)* %gep1 to i64 addrspace(1)*
%unused = atomicrmw add i64 addrspace(1)* %cast.gep1, i64 %data seq_cst
ret void
}
; --------------------------------------------------------------------------------
; atomicrmw sub
; --------------------------------------------------------------------------------
define amdgpu_ps float @global_sub_saddr_i32_rtn(i8 addrspace(1)* inreg %sbase, i32 %voffset, i32 %data) {
; GFX9-LABEL: global_sub_saddr_i32_rtn:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_sub v0, v0, v1, s[2:3] glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: global_sub_saddr_i32_rtn:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_sub v0, v0, v1, s[2:3] glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%cast.gep0 = bitcast i8 addrspace(1)* %gep0 to i32 addrspace(1)*
%rtn = atomicrmw sub i32 addrspace(1)* %cast.gep0, i32 %data seq_cst
%cast.rtn = bitcast i32 %rtn to float
ret float %cast.rtn
}
define amdgpu_ps float @global_sub_saddr_i32_rtn_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, i32 %data) {
; GFX9-LABEL: global_sub_saddr_i32_rtn_neg128:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_sub v0, v0, v1, s[2:3] offset:-128 glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: global_sub_saddr_i32_rtn_neg128:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_sub v0, v0, v1, s[2:3] offset:-128 glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128
%cast.gep1 = bitcast i8 addrspace(1)* %gep1 to i32 addrspace(1)*
%rtn = atomicrmw sub i32 addrspace(1)* %cast.gep1, i32 %data seq_cst
%cast.rtn = bitcast i32 %rtn to float
ret float %cast.rtn
}
define amdgpu_ps void @global_sub_saddr_i32_nortn(i8 addrspace(1)* inreg %sbase, i32 %voffset, i32 %data) {
; GFX9-LABEL: global_sub_saddr_i32_nortn:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_sub v0, v1, s[2:3]
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: s_endpgm
;
; GFX10-LABEL: global_sub_saddr_i32_nortn:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_sub v0, v1, s[2:3]
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%cast.gep0 = bitcast i8 addrspace(1)* %gep0 to i32 addrspace(1)*
%unused = atomicrmw sub i32 addrspace(1)* %cast.gep0, i32 %data seq_cst
ret void
}
define amdgpu_ps void @global_sub_saddr_i32_nortn_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, i32 %data) {
; GFX9-LABEL: global_sub_saddr_i32_nortn_neg128:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_sub v0, v1, s[2:3] offset:-128
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: s_endpgm
;
; GFX10-LABEL: global_sub_saddr_i32_nortn_neg128:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_sub v0, v1, s[2:3] offset:-128
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128
%cast.gep1 = bitcast i8 addrspace(1)* %gep1 to i32 addrspace(1)*
%unused = atomicrmw sub i32 addrspace(1)* %cast.gep1, i32 %data seq_cst
ret void
}
define amdgpu_ps <2 x float> @global_sub_saddr_i64_rtn(i8 addrspace(1)* inreg %sbase, i32 %voffset, i64 %data) {
; GFX9-LABEL: global_sub_saddr_i64_rtn:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_sub_x2 v[0:1], v0, v[1:2], s[2:3] glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: global_sub_saddr_i64_rtn:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_sub_x2 v[0:1], v0, v[1:2], s[2:3] glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%cast.gep0 = bitcast i8 addrspace(1)* %gep0 to i64 addrspace(1)*
%rtn = atomicrmw sub i64 addrspace(1)* %cast.gep0, i64 %data seq_cst
%cast.rtn = bitcast i64 %rtn to <2 x float>
ret <2 x float> %cast.rtn
}
define amdgpu_ps <2 x float> @global_sub_saddr_i64_rtn_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, i64 %data) {
; GFX9-LABEL: global_sub_saddr_i64_rtn_neg128:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_sub_x2 v[0:1], v0, v[1:2], s[2:3] offset:-128 glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: global_sub_saddr_i64_rtn_neg128:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_sub_x2 v[0:1], v0, v[1:2], s[2:3] offset:-128 glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128
%cast.gep1 = bitcast i8 addrspace(1)* %gep1 to i64 addrspace(1)*
%rtn = atomicrmw sub i64 addrspace(1)* %cast.gep1, i64 %data seq_cst
%cast.rtn = bitcast i64 %rtn to <2 x float>
ret <2 x float> %cast.rtn
}
define amdgpu_ps void @global_sub_saddr_i64_nortn(i8 addrspace(1)* inreg %sbase, i32 %voffset, i64 %data) {
; GFX9-LABEL: global_sub_saddr_i64_nortn:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_sub_x2 v0, v[1:2], s[2:3]
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: s_endpgm
;
; GFX10-LABEL: global_sub_saddr_i64_nortn:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_sub_x2 v0, v[1:2], s[2:3]
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%cast.gep0 = bitcast i8 addrspace(1)* %gep0 to i64 addrspace(1)*
%unused = atomicrmw sub i64 addrspace(1)* %cast.gep0, i64 %data seq_cst
ret void
}
define amdgpu_ps void @global_sub_saddr_i64_nortn_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, i64 %data) {
; GFX9-LABEL: global_sub_saddr_i64_nortn_neg128:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_sub_x2 v0, v[1:2], s[2:3] offset:-128
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: s_endpgm
;
; GFX10-LABEL: global_sub_saddr_i64_nortn_neg128:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_sub_x2 v0, v[1:2], s[2:3] offset:-128
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128
%cast.gep1 = bitcast i8 addrspace(1)* %gep1 to i64 addrspace(1)*
%unused = atomicrmw sub i64 addrspace(1)* %cast.gep1, i64 %data seq_cst
ret void
}
; --------------------------------------------------------------------------------
; atomicrmw and
; --------------------------------------------------------------------------------
define amdgpu_ps float @global_and_saddr_i32_rtn(i8 addrspace(1)* inreg %sbase, i32 %voffset, i32 %data) {
; GFX9-LABEL: global_and_saddr_i32_rtn:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_and v0, v0, v1, s[2:3] glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: global_and_saddr_i32_rtn:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_and v0, v0, v1, s[2:3] glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%cast.gep0 = bitcast i8 addrspace(1)* %gep0 to i32 addrspace(1)*
%rtn = atomicrmw and i32 addrspace(1)* %cast.gep0, i32 %data seq_cst
%cast.rtn = bitcast i32 %rtn to float
ret float %cast.rtn
}
define amdgpu_ps float @global_and_saddr_i32_rtn_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, i32 %data) {
; GFX9-LABEL: global_and_saddr_i32_rtn_neg128:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_and v0, v0, v1, s[2:3] offset:-128 glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: global_and_saddr_i32_rtn_neg128:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_and v0, v0, v1, s[2:3] offset:-128 glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128
%cast.gep1 = bitcast i8 addrspace(1)* %gep1 to i32 addrspace(1)*
%rtn = atomicrmw and i32 addrspace(1)* %cast.gep1, i32 %data seq_cst
%cast.rtn = bitcast i32 %rtn to float
ret float %cast.rtn
}
define amdgpu_ps void @global_and_saddr_i32_nortn(i8 addrspace(1)* inreg %sbase, i32 %voffset, i32 %data) {
; GFX9-LABEL: global_and_saddr_i32_nortn:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_and v0, v1, s[2:3]
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: s_endpgm
;
; GFX10-LABEL: global_and_saddr_i32_nortn:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_and v0, v1, s[2:3]
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%cast.gep0 = bitcast i8 addrspace(1)* %gep0 to i32 addrspace(1)*
%unused = atomicrmw and i32 addrspace(1)* %cast.gep0, i32 %data seq_cst
ret void
}
define amdgpu_ps void @global_and_saddr_i32_nortn_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, i32 %data) {
; GFX9-LABEL: global_and_saddr_i32_nortn_neg128:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_and v0, v1, s[2:3] offset:-128
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: s_endpgm
;
; GFX10-LABEL: global_and_saddr_i32_nortn_neg128:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_and v0, v1, s[2:3] offset:-128
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128
%cast.gep1 = bitcast i8 addrspace(1)* %gep1 to i32 addrspace(1)*
%unused = atomicrmw and i32 addrspace(1)* %cast.gep1, i32 %data seq_cst
ret void
}
define amdgpu_ps <2 x float> @global_and_saddr_i64_rtn(i8 addrspace(1)* inreg %sbase, i32 %voffset, i64 %data) {
; GFX9-LABEL: global_and_saddr_i64_rtn:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_and_x2 v[0:1], v0, v[1:2], s[2:3] glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: global_and_saddr_i64_rtn:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_and_x2 v[0:1], v0, v[1:2], s[2:3] glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%cast.gep0 = bitcast i8 addrspace(1)* %gep0 to i64 addrspace(1)*
%rtn = atomicrmw and i64 addrspace(1)* %cast.gep0, i64 %data seq_cst
%cast.rtn = bitcast i64 %rtn to <2 x float>
ret <2 x float> %cast.rtn
}
define amdgpu_ps <2 x float> @global_and_saddr_i64_rtn_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, i64 %data) {
; GFX9-LABEL: global_and_saddr_i64_rtn_neg128:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_and_x2 v[0:1], v0, v[1:2], s[2:3] offset:-128 glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: global_and_saddr_i64_rtn_neg128:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_and_x2 v[0:1], v0, v[1:2], s[2:3] offset:-128 glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128
%cast.gep1 = bitcast i8 addrspace(1)* %gep1 to i64 addrspace(1)*
%rtn = atomicrmw and i64 addrspace(1)* %cast.gep1, i64 %data seq_cst
%cast.rtn = bitcast i64 %rtn to <2 x float>
ret <2 x float> %cast.rtn
}
define amdgpu_ps void @global_and_saddr_i64_nortn(i8 addrspace(1)* inreg %sbase, i32 %voffset, i64 %data) {
; GFX9-LABEL: global_and_saddr_i64_nortn:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_and_x2 v0, v[1:2], s[2:3]
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: s_endpgm
;
; GFX10-LABEL: global_and_saddr_i64_nortn:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_and_x2 v0, v[1:2], s[2:3]
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%cast.gep0 = bitcast i8 addrspace(1)* %gep0 to i64 addrspace(1)*
%unused = atomicrmw and i64 addrspace(1)* %cast.gep0, i64 %data seq_cst
ret void
}
define amdgpu_ps void @global_and_saddr_i64_nortn_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, i64 %data) {
; GFX9-LABEL: global_and_saddr_i64_nortn_neg128:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_and_x2 v0, v[1:2], s[2:3] offset:-128
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: s_endpgm
;
; GFX10-LABEL: global_and_saddr_i64_nortn_neg128:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_and_x2 v0, v[1:2], s[2:3] offset:-128
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128
%cast.gep1 = bitcast i8 addrspace(1)* %gep1 to i64 addrspace(1)*
%unused = atomicrmw and i64 addrspace(1)* %cast.gep1, i64 %data seq_cst
ret void
}
; --------------------------------------------------------------------------------
; atomicrmw or
; --------------------------------------------------------------------------------
define amdgpu_ps float @global_or_saddr_i32_rtn(i8 addrspace(1)* inreg %sbase, i32 %voffset, i32 %data) {
; GFX9-LABEL: global_or_saddr_i32_rtn:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_or v0, v0, v1, s[2:3] glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: global_or_saddr_i32_rtn:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_or v0, v0, v1, s[2:3] glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%cast.gep0 = bitcast i8 addrspace(1)* %gep0 to i32 addrspace(1)*
%rtn = atomicrmw or i32 addrspace(1)* %cast.gep0, i32 %data seq_cst
%cast.rtn = bitcast i32 %rtn to float
ret float %cast.rtn
}
define amdgpu_ps float @global_or_saddr_i32_rtn_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, i32 %data) {
; GFX9-LABEL: global_or_saddr_i32_rtn_neg128:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_or v0, v0, v1, s[2:3] offset:-128 glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: global_or_saddr_i32_rtn_neg128:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_or v0, v0, v1, s[2:3] offset:-128 glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128
%cast.gep1 = bitcast i8 addrspace(1)* %gep1 to i32 addrspace(1)*
%rtn = atomicrmw or i32 addrspace(1)* %cast.gep1, i32 %data seq_cst
%cast.rtn = bitcast i32 %rtn to float
ret float %cast.rtn
}
define amdgpu_ps void @global_or_saddr_i32_nortn(i8 addrspace(1)* inreg %sbase, i32 %voffset, i32 %data) {
; GFX9-LABEL: global_or_saddr_i32_nortn:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_or v0, v1, s[2:3]
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: s_endpgm
;
; GFX10-LABEL: global_or_saddr_i32_nortn:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_or v0, v1, s[2:3]
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%cast.gep0 = bitcast i8 addrspace(1)* %gep0 to i32 addrspace(1)*
%unused = atomicrmw or i32 addrspace(1)* %cast.gep0, i32 %data seq_cst
ret void
}
define amdgpu_ps void @global_or_saddr_i32_nortn_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, i32 %data) {
; GFX9-LABEL: global_or_saddr_i32_nortn_neg128:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_or v0, v1, s[2:3] offset:-128
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: s_endpgm
;
; GFX10-LABEL: global_or_saddr_i32_nortn_neg128:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_or v0, v1, s[2:3] offset:-128
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128
%cast.gep1 = bitcast i8 addrspace(1)* %gep1 to i32 addrspace(1)*
%unused = atomicrmw or i32 addrspace(1)* %cast.gep1, i32 %data seq_cst
ret void
}
define amdgpu_ps <2 x float> @global_or_saddr_i64_rtn(i8 addrspace(1)* inreg %sbase, i32 %voffset, i64 %data) {
; GFX9-LABEL: global_or_saddr_i64_rtn:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_or_x2 v[0:1], v0, v[1:2], s[2:3] glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: global_or_saddr_i64_rtn:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_or_x2 v[0:1], v0, v[1:2], s[2:3] glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%cast.gep0 = bitcast i8 addrspace(1)* %gep0 to i64 addrspace(1)*
%rtn = atomicrmw or i64 addrspace(1)* %cast.gep0, i64 %data seq_cst
%cast.rtn = bitcast i64 %rtn to <2 x float>
ret <2 x float> %cast.rtn
}
define amdgpu_ps <2 x float> @global_or_saddr_i64_rtn_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, i64 %data) {
; GFX9-LABEL: global_or_saddr_i64_rtn_neg128:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_or_x2 v[0:1], v0, v[1:2], s[2:3] offset:-128 glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: global_or_saddr_i64_rtn_neg128:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_or_x2 v[0:1], v0, v[1:2], s[2:3] offset:-128 glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128
%cast.gep1 = bitcast i8 addrspace(1)* %gep1 to i64 addrspace(1)*
%rtn = atomicrmw or i64 addrspace(1)* %cast.gep1, i64 %data seq_cst
%cast.rtn = bitcast i64 %rtn to <2 x float>
ret <2 x float> %cast.rtn
}
define amdgpu_ps void @global_or_saddr_i64_nortn(i8 addrspace(1)* inreg %sbase, i32 %voffset, i64 %data) {
; GFX9-LABEL: global_or_saddr_i64_nortn:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_or_x2 v0, v[1:2], s[2:3]
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: s_endpgm
;
; GFX10-LABEL: global_or_saddr_i64_nortn:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_or_x2 v0, v[1:2], s[2:3]
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%cast.gep0 = bitcast i8 addrspace(1)* %gep0 to i64 addrspace(1)*
%unused = atomicrmw or i64 addrspace(1)* %cast.gep0, i64 %data seq_cst
ret void
}
define amdgpu_ps void @global_or_saddr_i64_nortn_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, i64 %data) {
; GFX9-LABEL: global_or_saddr_i64_nortn_neg128:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_or_x2 v0, v[1:2], s[2:3] offset:-128
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: s_endpgm
;
; GFX10-LABEL: global_or_saddr_i64_nortn_neg128:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_or_x2 v0, v[1:2], s[2:3] offset:-128
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128
%cast.gep1 = bitcast i8 addrspace(1)* %gep1 to i64 addrspace(1)*
%unused = atomicrmw or i64 addrspace(1)* %cast.gep1, i64 %data seq_cst
ret void
}
; --------------------------------------------------------------------------------
; atomicrmw xor
; --------------------------------------------------------------------------------
define amdgpu_ps float @global_xor_saddr_i32_rtn(i8 addrspace(1)* inreg %sbase, i32 %voffset, i32 %data) {
; GFX9-LABEL: global_xor_saddr_i32_rtn:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_xor v0, v0, v1, s[2:3] glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: global_xor_saddr_i32_rtn:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_xor v0, v0, v1, s[2:3] glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%cast.gep0 = bitcast i8 addrspace(1)* %gep0 to i32 addrspace(1)*
%rtn = atomicrmw xor i32 addrspace(1)* %cast.gep0, i32 %data seq_cst
%cast.rtn = bitcast i32 %rtn to float
ret float %cast.rtn
}
define amdgpu_ps float @global_xor_saddr_i32_rtn_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, i32 %data) {
; GFX9-LABEL: global_xor_saddr_i32_rtn_neg128:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_xor v0, v0, v1, s[2:3] offset:-128 glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: global_xor_saddr_i32_rtn_neg128:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_xor v0, v0, v1, s[2:3] offset:-128 glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128
%cast.gep1 = bitcast i8 addrspace(1)* %gep1 to i32 addrspace(1)*
%rtn = atomicrmw xor i32 addrspace(1)* %cast.gep1, i32 %data seq_cst
%cast.rtn = bitcast i32 %rtn to float
ret float %cast.rtn
}
define amdgpu_ps void @global_xor_saddr_i32_nortn(i8 addrspace(1)* inreg %sbase, i32 %voffset, i32 %data) {
; GFX9-LABEL: global_xor_saddr_i32_nortn:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_xor v0, v1, s[2:3]
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: s_endpgm
;
; GFX10-LABEL: global_xor_saddr_i32_nortn:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_xor v0, v1, s[2:3]
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%cast.gep0 = bitcast i8 addrspace(1)* %gep0 to i32 addrspace(1)*
%unused = atomicrmw xor i32 addrspace(1)* %cast.gep0, i32 %data seq_cst
ret void
}
define amdgpu_ps void @global_xor_saddr_i32_nortn_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, i32 %data) {
; GFX9-LABEL: global_xor_saddr_i32_nortn_neg128:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_xor v0, v1, s[2:3] offset:-128
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: s_endpgm
;
; GFX10-LABEL: global_xor_saddr_i32_nortn_neg128:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_xor v0, v1, s[2:3] offset:-128
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128
%cast.gep1 = bitcast i8 addrspace(1)* %gep1 to i32 addrspace(1)*
%unused = atomicrmw xor i32 addrspace(1)* %cast.gep1, i32 %data seq_cst
ret void
}
define amdgpu_ps <2 x float> @global_xor_saddr_i64_rtn(i8 addrspace(1)* inreg %sbase, i32 %voffset, i64 %data) {
; GFX9-LABEL: global_xor_saddr_i64_rtn:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_xor_x2 v[0:1], v0, v[1:2], s[2:3] glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: global_xor_saddr_i64_rtn:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_xor_x2 v[0:1], v0, v[1:2], s[2:3] glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%cast.gep0 = bitcast i8 addrspace(1)* %gep0 to i64 addrspace(1)*
%rtn = atomicrmw xor i64 addrspace(1)* %cast.gep0, i64 %data seq_cst
%cast.rtn = bitcast i64 %rtn to <2 x float>
ret <2 x float> %cast.rtn
}
define amdgpu_ps <2 x float> @global_xor_saddr_i64_rtn_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, i64 %data) {
; GFX9-LABEL: global_xor_saddr_i64_rtn_neg128:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_xor_x2 v[0:1], v0, v[1:2], s[2:3] offset:-128 glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: global_xor_saddr_i64_rtn_neg128:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_xor_x2 v[0:1], v0, v[1:2], s[2:3] offset:-128 glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128
%cast.gep1 = bitcast i8 addrspace(1)* %gep1 to i64 addrspace(1)*
%rtn = atomicrmw xor i64 addrspace(1)* %cast.gep1, i64 %data seq_cst
%cast.rtn = bitcast i64 %rtn to <2 x float>
ret <2 x float> %cast.rtn
}
define amdgpu_ps void @global_xor_saddr_i64_nortn(i8 addrspace(1)* inreg %sbase, i32 %voffset, i64 %data) {
; GFX9-LABEL: global_xor_saddr_i64_nortn:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_xor_x2 v0, v[1:2], s[2:3]
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: s_endpgm
;
; GFX10-LABEL: global_xor_saddr_i64_nortn:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_xor_x2 v0, v[1:2], s[2:3]
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%cast.gep0 = bitcast i8 addrspace(1)* %gep0 to i64 addrspace(1)*
%unused = atomicrmw xor i64 addrspace(1)* %cast.gep0, i64 %data seq_cst
ret void
}
define amdgpu_ps void @global_xor_saddr_i64_nortn_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, i64 %data) {
; GFX9-LABEL: global_xor_saddr_i64_nortn_neg128:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_xor_x2 v0, v[1:2], s[2:3] offset:-128
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: s_endpgm
;
; GFX10-LABEL: global_xor_saddr_i64_nortn_neg128:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_xor_x2 v0, v[1:2], s[2:3] offset:-128
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128
%cast.gep1 = bitcast i8 addrspace(1)* %gep1 to i64 addrspace(1)*
%unused = atomicrmw xor i64 addrspace(1)* %cast.gep1, i64 %data seq_cst
ret void
}
; --------------------------------------------------------------------------------
; atomicrmw max
; --------------------------------------------------------------------------------
define amdgpu_ps float @global_max_saddr_i32_rtn(i8 addrspace(1)* inreg %sbase, i32 %voffset, i32 %data) {
; GFX9-LABEL: global_max_saddr_i32_rtn:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_smax v0, v0, v1, s[2:3] glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: global_max_saddr_i32_rtn:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_smax v0, v0, v1, s[2:3] glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%cast.gep0 = bitcast i8 addrspace(1)* %gep0 to i32 addrspace(1)*
%rtn = atomicrmw max i32 addrspace(1)* %cast.gep0, i32 %data seq_cst
%cast.rtn = bitcast i32 %rtn to float
ret float %cast.rtn
}
define amdgpu_ps float @global_max_saddr_i32_rtn_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, i32 %data) {
; GFX9-LABEL: global_max_saddr_i32_rtn_neg128:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_smax v0, v0, v1, s[2:3] offset:-128 glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: global_max_saddr_i32_rtn_neg128:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_smax v0, v0, v1, s[2:3] offset:-128 glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128
%cast.gep1 = bitcast i8 addrspace(1)* %gep1 to i32 addrspace(1)*
%rtn = atomicrmw max i32 addrspace(1)* %cast.gep1, i32 %data seq_cst
%cast.rtn = bitcast i32 %rtn to float
ret float %cast.rtn
}
define amdgpu_ps void @global_max_saddr_i32_nortn(i8 addrspace(1)* inreg %sbase, i32 %voffset, i32 %data) {
; GFX9-LABEL: global_max_saddr_i32_nortn:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_smax v0, v1, s[2:3]
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: s_endpgm
;
; GFX10-LABEL: global_max_saddr_i32_nortn:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_smax v0, v1, s[2:3]
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%cast.gep0 = bitcast i8 addrspace(1)* %gep0 to i32 addrspace(1)*
%unused = atomicrmw max i32 addrspace(1)* %cast.gep0, i32 %data seq_cst
ret void
}
define amdgpu_ps void @global_max_saddr_i32_nortn_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, i32 %data) {
; GFX9-LABEL: global_max_saddr_i32_nortn_neg128:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_smax v0, v1, s[2:3] offset:-128
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: s_endpgm
;
; GFX10-LABEL: global_max_saddr_i32_nortn_neg128:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_smax v0, v1, s[2:3] offset:-128
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128
%cast.gep1 = bitcast i8 addrspace(1)* %gep1 to i32 addrspace(1)*
%unused = atomicrmw max i32 addrspace(1)* %cast.gep1, i32 %data seq_cst
ret void
}
define amdgpu_ps <2 x float> @global_max_saddr_i64_rtn(i8 addrspace(1)* inreg %sbase, i32 %voffset, i64 %data) {
; GFX9-LABEL: global_max_saddr_i64_rtn:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_smax_x2 v[0:1], v0, v[1:2], s[2:3] glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: global_max_saddr_i64_rtn:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_smax_x2 v[0:1], v0, v[1:2], s[2:3] glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%cast.gep0 = bitcast i8 addrspace(1)* %gep0 to i64 addrspace(1)*
%rtn = atomicrmw max i64 addrspace(1)* %cast.gep0, i64 %data seq_cst
%cast.rtn = bitcast i64 %rtn to <2 x float>
ret <2 x float> %cast.rtn
}
define amdgpu_ps <2 x float> @global_max_saddr_i64_rtn_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, i64 %data) {
; GFX9-LABEL: global_max_saddr_i64_rtn_neg128:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_smax_x2 v[0:1], v0, v[1:2], s[2:3] offset:-128 glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: global_max_saddr_i64_rtn_neg128:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_smax_x2 v[0:1], v0, v[1:2], s[2:3] offset:-128 glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128
%cast.gep1 = bitcast i8 addrspace(1)* %gep1 to i64 addrspace(1)*
%rtn = atomicrmw max i64 addrspace(1)* %cast.gep1, i64 %data seq_cst
%cast.rtn = bitcast i64 %rtn to <2 x float>
ret <2 x float> %cast.rtn
}
define amdgpu_ps void @global_max_saddr_i64_nortn(i8 addrspace(1)* inreg %sbase, i32 %voffset, i64 %data) {
; GFX9-LABEL: global_max_saddr_i64_nortn:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_smax_x2 v0, v[1:2], s[2:3]
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: s_endpgm
;
; GFX10-LABEL: global_max_saddr_i64_nortn:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_smax_x2 v0, v[1:2], s[2:3]
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%cast.gep0 = bitcast i8 addrspace(1)* %gep0 to i64 addrspace(1)*
%unused = atomicrmw max i64 addrspace(1)* %cast.gep0, i64 %data seq_cst
ret void
}
define amdgpu_ps void @global_max_saddr_i64_nortn_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, i64 %data) {
; GFX9-LABEL: global_max_saddr_i64_nortn_neg128:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_smax_x2 v0, v[1:2], s[2:3] offset:-128
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: s_endpgm
;
; GFX10-LABEL: global_max_saddr_i64_nortn_neg128:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_smax_x2 v0, v[1:2], s[2:3] offset:-128
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128
%cast.gep1 = bitcast i8 addrspace(1)* %gep1 to i64 addrspace(1)*
%unused = atomicrmw max i64 addrspace(1)* %cast.gep1, i64 %data seq_cst
ret void
}
; --------------------------------------------------------------------------------
; atomicrmw min
; --------------------------------------------------------------------------------
define amdgpu_ps float @global_min_saddr_i32_rtn(i8 addrspace(1)* inreg %sbase, i32 %voffset, i32 %data) {
; GFX9-LABEL: global_min_saddr_i32_rtn:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_smin v0, v0, v1, s[2:3] glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: global_min_saddr_i32_rtn:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_smin v0, v0, v1, s[2:3] glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%cast.gep0 = bitcast i8 addrspace(1)* %gep0 to i32 addrspace(1)*
%rtn = atomicrmw min i32 addrspace(1)* %cast.gep0, i32 %data seq_cst
%cast.rtn = bitcast i32 %rtn to float
ret float %cast.rtn
}
define amdgpu_ps float @global_min_saddr_i32_rtn_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, i32 %data) {
; GFX9-LABEL: global_min_saddr_i32_rtn_neg128:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_smin v0, v0, v1, s[2:3] offset:-128 glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: global_min_saddr_i32_rtn_neg128:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_smin v0, v0, v1, s[2:3] offset:-128 glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128
%cast.gep1 = bitcast i8 addrspace(1)* %gep1 to i32 addrspace(1)*
%rtn = atomicrmw min i32 addrspace(1)* %cast.gep1, i32 %data seq_cst
%cast.rtn = bitcast i32 %rtn to float
ret float %cast.rtn
}
define amdgpu_ps void @global_min_saddr_i32_nortn(i8 addrspace(1)* inreg %sbase, i32 %voffset, i32 %data) {
; GFX9-LABEL: global_min_saddr_i32_nortn:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_smin v0, v1, s[2:3]
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: s_endpgm
;
; GFX10-LABEL: global_min_saddr_i32_nortn:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_smin v0, v1, s[2:3]
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%cast.gep0 = bitcast i8 addrspace(1)* %gep0 to i32 addrspace(1)*
%unused = atomicrmw min i32 addrspace(1)* %cast.gep0, i32 %data seq_cst
ret void
}
define amdgpu_ps void @global_min_saddr_i32_nortn_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, i32 %data) {
; GFX9-LABEL: global_min_saddr_i32_nortn_neg128:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_smin v0, v1, s[2:3] offset:-128
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: s_endpgm
;
; GFX10-LABEL: global_min_saddr_i32_nortn_neg128:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_smin v0, v1, s[2:3] offset:-128
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128
%cast.gep1 = bitcast i8 addrspace(1)* %gep1 to i32 addrspace(1)*
%unused = atomicrmw min i32 addrspace(1)* %cast.gep1, i32 %data seq_cst
ret void
}
define amdgpu_ps <2 x float> @global_min_saddr_i64_rtn(i8 addrspace(1)* inreg %sbase, i32 %voffset, i64 %data) {
; GFX9-LABEL: global_min_saddr_i64_rtn:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_smin_x2 v[0:1], v0, v[1:2], s[2:3] glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: global_min_saddr_i64_rtn:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_smin_x2 v[0:1], v0, v[1:2], s[2:3] glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%cast.gep0 = bitcast i8 addrspace(1)* %gep0 to i64 addrspace(1)*
%rtn = atomicrmw min i64 addrspace(1)* %cast.gep0, i64 %data seq_cst
%cast.rtn = bitcast i64 %rtn to <2 x float>
ret <2 x float> %cast.rtn
}
define amdgpu_ps <2 x float> @global_min_saddr_i64_rtn_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, i64 %data) {
; GFX9-LABEL: global_min_saddr_i64_rtn_neg128:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_smin_x2 v[0:1], v0, v[1:2], s[2:3] offset:-128 glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: global_min_saddr_i64_rtn_neg128:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_smin_x2 v[0:1], v0, v[1:2], s[2:3] offset:-128 glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128
%cast.gep1 = bitcast i8 addrspace(1)* %gep1 to i64 addrspace(1)*
%rtn = atomicrmw min i64 addrspace(1)* %cast.gep1, i64 %data seq_cst
%cast.rtn = bitcast i64 %rtn to <2 x float>
ret <2 x float> %cast.rtn
}
define amdgpu_ps void @global_min_saddr_i64_nortn(i8 addrspace(1)* inreg %sbase, i32 %voffset, i64 %data) {
; GFX9-LABEL: global_min_saddr_i64_nortn:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_smin_x2 v0, v[1:2], s[2:3]
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: s_endpgm
;
; GFX10-LABEL: global_min_saddr_i64_nortn:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_smin_x2 v0, v[1:2], s[2:3]
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%cast.gep0 = bitcast i8 addrspace(1)* %gep0 to i64 addrspace(1)*
%unused = atomicrmw min i64 addrspace(1)* %cast.gep0, i64 %data seq_cst
ret void
}
define amdgpu_ps void @global_min_saddr_i64_nortn_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, i64 %data) {
; GFX9-LABEL: global_min_saddr_i64_nortn_neg128:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_smin_x2 v0, v[1:2], s[2:3] offset:-128
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: s_endpgm
;
; GFX10-LABEL: global_min_saddr_i64_nortn_neg128:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_smin_x2 v0, v[1:2], s[2:3] offset:-128
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128
%cast.gep1 = bitcast i8 addrspace(1)* %gep1 to i64 addrspace(1)*
%unused = atomicrmw min i64 addrspace(1)* %cast.gep1, i64 %data seq_cst
ret void
}
; --------------------------------------------------------------------------------
; atomicrmw umax
; --------------------------------------------------------------------------------
define amdgpu_ps float @global_umax_saddr_i32_rtn(i8 addrspace(1)* inreg %sbase, i32 %voffset, i32 %data) {
; GFX9-LABEL: global_umax_saddr_i32_rtn:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_umax v0, v0, v1, s[2:3] glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: global_umax_saddr_i32_rtn:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_umax v0, v0, v1, s[2:3] glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%cast.gep0 = bitcast i8 addrspace(1)* %gep0 to i32 addrspace(1)*
%rtn = atomicrmw umax i32 addrspace(1)* %cast.gep0, i32 %data seq_cst
%cast.rtn = bitcast i32 %rtn to float
ret float %cast.rtn
}
define amdgpu_ps float @global_umax_saddr_i32_rtn_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, i32 %data) {
; GFX9-LABEL: global_umax_saddr_i32_rtn_neg128:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_umax v0, v0, v1, s[2:3] offset:-128 glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: global_umax_saddr_i32_rtn_neg128:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_umax v0, v0, v1, s[2:3] offset:-128 glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128
%cast.gep1 = bitcast i8 addrspace(1)* %gep1 to i32 addrspace(1)*
%rtn = atomicrmw umax i32 addrspace(1)* %cast.gep1, i32 %data seq_cst
%cast.rtn = bitcast i32 %rtn to float
ret float %cast.rtn
}
define amdgpu_ps void @global_umax_saddr_i32_nortn(i8 addrspace(1)* inreg %sbase, i32 %voffset, i32 %data) {
; GFX9-LABEL: global_umax_saddr_i32_nortn:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_umax v0, v1, s[2:3]
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: s_endpgm
;
; GFX10-LABEL: global_umax_saddr_i32_nortn:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_umax v0, v1, s[2:3]
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%cast.gep0 = bitcast i8 addrspace(1)* %gep0 to i32 addrspace(1)*
%unused = atomicrmw umax i32 addrspace(1)* %cast.gep0, i32 %data seq_cst
ret void
}
define amdgpu_ps void @global_umax_saddr_i32_nortn_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, i32 %data) {
; GFX9-LABEL: global_umax_saddr_i32_nortn_neg128:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_umax v0, v1, s[2:3] offset:-128
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: s_endpgm
;
; GFX10-LABEL: global_umax_saddr_i32_nortn_neg128:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_umax v0, v1, s[2:3] offset:-128
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128
%cast.gep1 = bitcast i8 addrspace(1)* %gep1 to i32 addrspace(1)*
%unused = atomicrmw umax i32 addrspace(1)* %cast.gep1, i32 %data seq_cst
ret void
}
define amdgpu_ps <2 x float> @global_umax_saddr_i64_rtn(i8 addrspace(1)* inreg %sbase, i32 %voffset, i64 %data) {
; GFX9-LABEL: global_umax_saddr_i64_rtn:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_umax_x2 v[0:1], v0, v[1:2], s[2:3] glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: global_umax_saddr_i64_rtn:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_umax_x2 v[0:1], v0, v[1:2], s[2:3] glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%cast.gep0 = bitcast i8 addrspace(1)* %gep0 to i64 addrspace(1)*
%rtn = atomicrmw umax i64 addrspace(1)* %cast.gep0, i64 %data seq_cst
%cast.rtn = bitcast i64 %rtn to <2 x float>
ret <2 x float> %cast.rtn
}
define amdgpu_ps <2 x float> @global_umax_saddr_i64_rtn_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, i64 %data) {
; GFX9-LABEL: global_umax_saddr_i64_rtn_neg128:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_umax_x2 v[0:1], v0, v[1:2], s[2:3] offset:-128 glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: global_umax_saddr_i64_rtn_neg128:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_umax_x2 v[0:1], v0, v[1:2], s[2:3] offset:-128 glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128
%cast.gep1 = bitcast i8 addrspace(1)* %gep1 to i64 addrspace(1)*
%rtn = atomicrmw umax i64 addrspace(1)* %cast.gep1, i64 %data seq_cst
%cast.rtn = bitcast i64 %rtn to <2 x float>
ret <2 x float> %cast.rtn
}
define amdgpu_ps void @global_umax_saddr_i64_nortn(i8 addrspace(1)* inreg %sbase, i32 %voffset, i64 %data) {
; GFX9-LABEL: global_umax_saddr_i64_nortn:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_umax_x2 v0, v[1:2], s[2:3]
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: s_endpgm
;
; GFX10-LABEL: global_umax_saddr_i64_nortn:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_umax_x2 v0, v[1:2], s[2:3]
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%cast.gep0 = bitcast i8 addrspace(1)* %gep0 to i64 addrspace(1)*
%unused = atomicrmw umax i64 addrspace(1)* %cast.gep0, i64 %data seq_cst
ret void
}
define amdgpu_ps void @global_umax_saddr_i64_nortn_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, i64 %data) {
; GFX9-LABEL: global_umax_saddr_i64_nortn_neg128:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_umax_x2 v0, v[1:2], s[2:3] offset:-128
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: s_endpgm
;
; GFX10-LABEL: global_umax_saddr_i64_nortn_neg128:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_umax_x2 v0, v[1:2], s[2:3] offset:-128
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128
%cast.gep1 = bitcast i8 addrspace(1)* %gep1 to i64 addrspace(1)*
%unused = atomicrmw umax i64 addrspace(1)* %cast.gep1, i64 %data seq_cst
ret void
}
; --------------------------------------------------------------------------------
; atomicrmw umin
; --------------------------------------------------------------------------------
define amdgpu_ps float @global_umin_saddr_i32_rtn(i8 addrspace(1)* inreg %sbase, i32 %voffset, i32 %data) {
; GFX9-LABEL: global_umin_saddr_i32_rtn:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_umin v0, v0, v1, s[2:3] glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: global_umin_saddr_i32_rtn:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_umin v0, v0, v1, s[2:3] glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%cast.gep0 = bitcast i8 addrspace(1)* %gep0 to i32 addrspace(1)*
%rtn = atomicrmw umin i32 addrspace(1)* %cast.gep0, i32 %data seq_cst
%cast.rtn = bitcast i32 %rtn to float
ret float %cast.rtn
}
define amdgpu_ps float @global_umin_saddr_i32_rtn_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, i32 %data) {
; GFX9-LABEL: global_umin_saddr_i32_rtn_neg128:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_umin v0, v0, v1, s[2:3] offset:-128 glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: global_umin_saddr_i32_rtn_neg128:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_umin v0, v0, v1, s[2:3] offset:-128 glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128
%cast.gep1 = bitcast i8 addrspace(1)* %gep1 to i32 addrspace(1)*
%rtn = atomicrmw umin i32 addrspace(1)* %cast.gep1, i32 %data seq_cst
%cast.rtn = bitcast i32 %rtn to float
ret float %cast.rtn
}
define amdgpu_ps void @global_umin_saddr_i32_nortn(i8 addrspace(1)* inreg %sbase, i32 %voffset, i32 %data) {
; GFX9-LABEL: global_umin_saddr_i32_nortn:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_umin v0, v1, s[2:3]
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: s_endpgm
;
; GFX10-LABEL: global_umin_saddr_i32_nortn:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_umin v0, v1, s[2:3]
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%cast.gep0 = bitcast i8 addrspace(1)* %gep0 to i32 addrspace(1)*
%unused = atomicrmw umin i32 addrspace(1)* %cast.gep0, i32 %data seq_cst
ret void
}
define amdgpu_ps void @global_umin_saddr_i32_nortn_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, i32 %data) {
; GFX9-LABEL: global_umin_saddr_i32_nortn_neg128:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_umin v0, v1, s[2:3] offset:-128
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: s_endpgm
;
; GFX10-LABEL: global_umin_saddr_i32_nortn_neg128:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_umin v0, v1, s[2:3] offset:-128
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128
%cast.gep1 = bitcast i8 addrspace(1)* %gep1 to i32 addrspace(1)*
%unused = atomicrmw umin i32 addrspace(1)* %cast.gep1, i32 %data seq_cst
ret void
}
define amdgpu_ps <2 x float> @global_umin_saddr_i64_rtn(i8 addrspace(1)* inreg %sbase, i32 %voffset, i64 %data) {
; GFX9-LABEL: global_umin_saddr_i64_rtn:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_umin_x2 v[0:1], v0, v[1:2], s[2:3] glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: global_umin_saddr_i64_rtn:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_umin_x2 v[0:1], v0, v[1:2], s[2:3] glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%cast.gep0 = bitcast i8 addrspace(1)* %gep0 to i64 addrspace(1)*
%rtn = atomicrmw umin i64 addrspace(1)* %cast.gep0, i64 %data seq_cst
%cast.rtn = bitcast i64 %rtn to <2 x float>
ret <2 x float> %cast.rtn
}
define amdgpu_ps <2 x float> @global_umin_saddr_i64_rtn_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, i64 %data) {
; GFX9-LABEL: global_umin_saddr_i64_rtn_neg128:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_umin_x2 v[0:1], v0, v[1:2], s[2:3] offset:-128 glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: global_umin_saddr_i64_rtn_neg128:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_umin_x2 v[0:1], v0, v[1:2], s[2:3] offset:-128 glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128
%cast.gep1 = bitcast i8 addrspace(1)* %gep1 to i64 addrspace(1)*
%rtn = atomicrmw umin i64 addrspace(1)* %cast.gep1, i64 %data seq_cst
%cast.rtn = bitcast i64 %rtn to <2 x float>
ret <2 x float> %cast.rtn
}
define amdgpu_ps void @global_umin_saddr_i64_nortn(i8 addrspace(1)* inreg %sbase, i32 %voffset, i64 %data) {
; GFX9-LABEL: global_umin_saddr_i64_nortn:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_umin_x2 v0, v[1:2], s[2:3]
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: s_endpgm
;
; GFX10-LABEL: global_umin_saddr_i64_nortn:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_umin_x2 v0, v[1:2], s[2:3]
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%cast.gep0 = bitcast i8 addrspace(1)* %gep0 to i64 addrspace(1)*
%unused = atomicrmw umin i64 addrspace(1)* %cast.gep0, i64 %data seq_cst
ret void
}
define amdgpu_ps void @global_umin_saddr_i64_nortn_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, i64 %data) {
; GFX9-LABEL: global_umin_saddr_i64_nortn_neg128:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_umin_x2 v0, v[1:2], s[2:3] offset:-128
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: s_endpgm
;
; GFX10-LABEL: global_umin_saddr_i64_nortn_neg128:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_umin_x2 v0, v[1:2], s[2:3] offset:-128
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128
%cast.gep1 = bitcast i8 addrspace(1)* %gep1 to i64 addrspace(1)*
%unused = atomicrmw umin i64 addrspace(1)* %cast.gep1, i64 %data seq_cst
ret void
}
; --------------------------------------------------------------------------------
; cmpxchg
; --------------------------------------------------------------------------------
define amdgpu_ps float @global_cmpxchg_saddr_i32_rtn(i8 addrspace(1)* inreg %sbase, i32 %voffset, i32 %cmp, i32 %data) {
; GFX9-LABEL: global_cmpxchg_saddr_i32_rtn:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_mov_b32_e32 v3, v1
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_cmpswap v0, v0, v[2:3], s[2:3] glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: global_cmpxchg_saddr_i32_rtn:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_mov_b32_e32 v3, v1
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_cmpswap v0, v0, v[2:3], s[2:3] glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%cast.gep0 = bitcast i8 addrspace(1)* %gep0 to i32 addrspace(1)*
%cmpxchg = cmpxchg i32 addrspace(1)* %cast.gep0, i32 %cmp, i32 %data seq_cst seq_cst
%rtn = extractvalue { i32, i1 } %cmpxchg, 0
%cast.rtn = bitcast i32 %rtn to float
ret float %cast.rtn
}
define amdgpu_ps float @global_cmpxchg_saddr_i32_rtn_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, i32 %cmp, i32 %data) {
; GFX9-LABEL: global_cmpxchg_saddr_i32_rtn_neg128:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_mov_b32_e32 v3, v1
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_cmpswap v0, v0, v[2:3], s[2:3] offset:-128 glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: global_cmpxchg_saddr_i32_rtn_neg128:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_mov_b32_e32 v3, v1
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_cmpswap v0, v0, v[2:3], s[2:3] offset:-128 glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128
%cast.gep1 = bitcast i8 addrspace(1)* %gep1 to i32 addrspace(1)*
%cmpxchg = cmpxchg i32 addrspace(1)* %cast.gep1, i32 %cmp, i32 %data seq_cst seq_cst
%rtn = extractvalue { i32, i1 } %cmpxchg, 0
%cast.rtn = bitcast i32 %rtn to float
ret float %cast.rtn
}
define amdgpu_ps void @global_cmpxchg_saddr_i32_nortn(i8 addrspace(1)* inreg %sbase, i32 %voffset, i32 %cmp, i32 %data) {
; GFX9-LABEL: global_cmpxchg_saddr_i32_nortn:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_mov_b32_e32 v3, v1
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_cmpswap v0, v[2:3], s[2:3]
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: s_endpgm
;
; GFX10-LABEL: global_cmpxchg_saddr_i32_nortn:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_mov_b32_e32 v3, v1
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_cmpswap v0, v[2:3], s[2:3]
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%cast.gep0 = bitcast i8 addrspace(1)* %gep0 to i32 addrspace(1)*
%unused = cmpxchg i32 addrspace(1)* %cast.gep0, i32 %cmp, i32 %data seq_cst seq_cst
ret void
}
define amdgpu_ps void @global_cmpxchg_saddr_i32_nortn_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, i32 %cmp, i32 %data) {
; GFX9-LABEL: global_cmpxchg_saddr_i32_nortn_neg128:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_mov_b32_e32 v3, v1
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_cmpswap v0, v[2:3], s[2:3] offset:-128
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: s_endpgm
;
; GFX10-LABEL: global_cmpxchg_saddr_i32_nortn_neg128:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_mov_b32_e32 v3, v1
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_cmpswap v0, v[2:3], s[2:3] offset:-128
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128
%cast.gep1 = bitcast i8 addrspace(1)* %gep1 to i32 addrspace(1)*
%unused = cmpxchg i32 addrspace(1)* %cast.gep1, i32 %cmp, i32 %data seq_cst seq_cst
ret void
}
define amdgpu_ps <2 x float> @global_cmpxchg_saddr_i64_rtn(i8 addrspace(1)* inreg %sbase, i32 %voffset, i64 %cmp, i64 %data) {
; GFX9-LABEL: global_cmpxchg_saddr_i64_rtn:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_mov_b32_e32 v6, v2
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: v_mov_b32_e32 v5, v1
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_cmpswap_x2 v[0:1], v0, v[3:6], s[2:3] glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: global_cmpxchg_saddr_i64_rtn:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_mov_b32_e32 v6, v2
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: v_mov_b32_e32 v5, v1
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_cmpswap_x2 v[0:1], v0, v[3:6], s[2:3] glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%cast.gep0 = bitcast i8 addrspace(1)* %gep0 to i64 addrspace(1)*
%cmpxchg = cmpxchg i64 addrspace(1)* %cast.gep0, i64 %cmp, i64 %data seq_cst seq_cst
%rtn = extractvalue { i64, i1 } %cmpxchg, 0
%cast.rtn = bitcast i64 %rtn to <2 x float>
ret <2 x float> %cast.rtn
}
define amdgpu_ps <2 x float> @global_cmpxchg_saddr_i64_rtn_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, i64 %cmp, i64 %data) {
; GFX9-LABEL: global_cmpxchg_saddr_i64_rtn_neg128:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_mov_b32_e32 v6, v2
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: v_mov_b32_e32 v5, v1
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_cmpswap_x2 v[0:1], v0, v[3:6], s[2:3] offset:-128 glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: global_cmpxchg_saddr_i64_rtn_neg128:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_mov_b32_e32 v6, v2
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: v_mov_b32_e32 v5, v1
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_cmpswap_x2 v[0:1], v0, v[3:6], s[2:3] offset:-128 glc
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128
%cast.gep1 = bitcast i8 addrspace(1)* %gep1 to i64 addrspace(1)*
%cmpxchg = cmpxchg i64 addrspace(1)* %cast.gep1, i64 %cmp, i64 %data seq_cst seq_cst
%rtn = extractvalue { i64, i1 } %cmpxchg, 0
%cast.rtn = bitcast i64 %rtn to <2 x float>
ret <2 x float> %cast.rtn
}
define amdgpu_ps void @global_cmpxchg_saddr_i64_nortn(i8 addrspace(1)* inreg %sbase, i32 %voffset, i64 %cmp, i64 %data) {
; GFX9-LABEL: global_cmpxchg_saddr_i64_nortn:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_mov_b32_e32 v6, v2
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: v_mov_b32_e32 v5, v1
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_cmpswap_x2 v0, v[3:6], s[2:3]
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: s_endpgm
;
; GFX10-LABEL: global_cmpxchg_saddr_i64_nortn:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_mov_b32_e32 v6, v2
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: v_mov_b32_e32 v5, v1
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_cmpswap_x2 v0, v[3:6], s[2:3]
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%cast.gep0 = bitcast i8 addrspace(1)* %gep0 to i64 addrspace(1)*
%unused = cmpxchg i64 addrspace(1)* %cast.gep0, i64 %cmp, i64 %data seq_cst seq_cst
ret void
}
define amdgpu_ps void @global_cmpxchg_saddr_i64_nortn_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, i64 %cmp, i64 %data) {
; GFX9-LABEL: global_cmpxchg_saddr_i64_nortn_neg128:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_mov_b32_e32 v6, v2
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: v_mov_b32_e32 v5, v1
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX9-NEXT: global_atomic_cmpswap_x2 v0, v[3:6], s[2:3] offset:-128
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1
; GFX9-NEXT: s_endpgm
;
; GFX10-LABEL: global_cmpxchg_saddr_i64_nortn_neg128:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_mov_b32_e32 v6, v2
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: v_mov_b32_e32 v5, v1
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GFX10-NEXT: global_atomic_cmpswap_x2 v0, v[3:6], s[2:3] offset:-128
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128
%cast.gep1 = bitcast i8 addrspace(1)* %gep1 to i64 addrspace(1)*
%unused = cmpxchg i64 addrspace(1)* %cast.gep1, i64 %cmp, i64 %data seq_cst seq_cst
ret void
}
; --------------------------------------------------------------------------------
; amdgcn atomic inc
; --------------------------------------------------------------------------------
declare i32 @llvm.amdgcn.atomic.inc.i32.p1i32(i32 addrspace(1)* nocapture, i32, i32 immarg, i32 immarg, i1 immarg) #0
declare i64 @llvm.amdgcn.atomic.inc.i64.p1i64(i64 addrspace(1)* nocapture, i64, i32 immarg, i32 immarg, i1 immarg) #0
define amdgpu_ps float @global_inc_saddr_i32_rtn(i8 addrspace(1)* inreg %sbase, i32 %voffset, i32 %data) {
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GCN-LABEL: global_inc_saddr_i32_rtn:
; GCN: ; %bb.0:
; GCN-NEXT: global_atomic_inc v0, v0, v1, s[2:3] glc
Revert "[AMDGPU] Insert waitcnt after returning from call" This reverts commit ca907bfb57d8ad3ec3bcc2cff2abab7b1b933af6. According to michel.daenzer, > This completely broke the Mesa radeonsi driver on Navi 14. Xorg + > xterm come up with major corruption & psychedelic colours.
2020-09-23 23:16:39 +08:00
; GCN-NEXT: s_waitcnt vmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GCN-NEXT: ; return to shader part epilog
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%cast.gep0 = bitcast i8 addrspace(1)* %gep0 to i32 addrspace(1)*
%rtn = call i32 @llvm.amdgcn.atomic.inc.i32.p1i32(i32 addrspace(1)* %cast.gep0, i32 %data, i32 0, i32 0, i1 false)
%cast.rtn = bitcast i32 %rtn to float
ret float %cast.rtn
}
define amdgpu_ps float @global_inc_saddr_i32_rtn_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, i32 %data) {
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GCN-LABEL: global_inc_saddr_i32_rtn_neg128:
; GCN: ; %bb.0:
; GCN-NEXT: global_atomic_inc v0, v0, v1, s[2:3] offset:-128 glc
Revert "[AMDGPU] Insert waitcnt after returning from call" This reverts commit ca907bfb57d8ad3ec3bcc2cff2abab7b1b933af6. According to michel.daenzer, > This completely broke the Mesa radeonsi driver on Navi 14. Xorg + > xterm come up with major corruption & psychedelic colours.
2020-09-23 23:16:39 +08:00
; GCN-NEXT: s_waitcnt vmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GCN-NEXT: ; return to shader part epilog
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128
%cast.gep1 = bitcast i8 addrspace(1)* %gep1 to i32 addrspace(1)*
%rtn = call i32 @llvm.amdgcn.atomic.inc.i32.p1i32(i32 addrspace(1)* %cast.gep1, i32 %data, i32 0, i32 0, i1 false)
%cast.rtn = bitcast i32 %rtn to float
ret float %cast.rtn
}
define amdgpu_ps void @global_inc_saddr_i32_nortn(i8 addrspace(1)* inreg %sbase, i32 %voffset, i32 %data) {
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GCN-LABEL: global_inc_saddr_i32_nortn:
; GCN: ; %bb.0:
; GCN-NEXT: global_atomic_inc v0, v1, s[2:3]
; GCN-NEXT: s_endpgm
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%cast.gep0 = bitcast i8 addrspace(1)* %gep0 to i32 addrspace(1)*
%unused = call i32 @llvm.amdgcn.atomic.inc.i32.p1i32(i32 addrspace(1)* %cast.gep0, i32 %data, i32 0, i32 0, i1 false)
ret void
}
define amdgpu_ps void @global_inc_saddr_i32_nortn_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, i32 %data) {
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GCN-LABEL: global_inc_saddr_i32_nortn_neg128:
; GCN: ; %bb.0:
; GCN-NEXT: global_atomic_inc v0, v1, s[2:3] offset:-128
; GCN-NEXT: s_endpgm
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128
%cast.gep1 = bitcast i8 addrspace(1)* %gep1 to i32 addrspace(1)*
%unused = call i32 @llvm.amdgcn.atomic.inc.i32.p1i32(i32 addrspace(1)* %cast.gep1, i32 %data, i32 0, i32 0, i1 false)
ret void
}
define amdgpu_ps <2 x float> @global_inc_saddr_i64_rtn(i8 addrspace(1)* inreg %sbase, i32 %voffset, i64 %data) {
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GCN-LABEL: global_inc_saddr_i64_rtn:
; GCN: ; %bb.0:
; GCN-NEXT: global_atomic_inc_x2 v[0:1], v0, v[1:2], s[2:3] glc
Revert "[AMDGPU] Insert waitcnt after returning from call" This reverts commit ca907bfb57d8ad3ec3bcc2cff2abab7b1b933af6. According to michel.daenzer, > This completely broke the Mesa radeonsi driver on Navi 14. Xorg + > xterm come up with major corruption & psychedelic colours.
2020-09-23 23:16:39 +08:00
; GCN-NEXT: s_waitcnt vmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GCN-NEXT: ; return to shader part epilog
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%cast.gep0 = bitcast i8 addrspace(1)* %gep0 to i64 addrspace(1)*
%rtn = call i64 @llvm.amdgcn.atomic.inc.i64.p1i64(i64 addrspace(1)* %cast.gep0, i64 %data, i32 0, i32 0, i1 false)
%cast.rtn = bitcast i64 %rtn to <2 x float>
ret <2 x float> %cast.rtn
}
define amdgpu_ps <2 x float> @global_inc_saddr_i64_rtn_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, i64 %data) {
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GCN-LABEL: global_inc_saddr_i64_rtn_neg128:
; GCN: ; %bb.0:
; GCN-NEXT: global_atomic_inc_x2 v[0:1], v0, v[1:2], s[2:3] offset:-128 glc
Revert "[AMDGPU] Insert waitcnt after returning from call" This reverts commit ca907bfb57d8ad3ec3bcc2cff2abab7b1b933af6. According to michel.daenzer, > This completely broke the Mesa radeonsi driver on Navi 14. Xorg + > xterm come up with major corruption & psychedelic colours.
2020-09-23 23:16:39 +08:00
; GCN-NEXT: s_waitcnt vmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GCN-NEXT: ; return to shader part epilog
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128
%cast.gep1 = bitcast i8 addrspace(1)* %gep1 to i64 addrspace(1)*
%rtn = call i64 @llvm.amdgcn.atomic.inc.i64.p1i64(i64 addrspace(1)* %cast.gep1, i64 %data, i32 0, i32 0, i1 false)
%cast.rtn = bitcast i64 %rtn to <2 x float>
ret <2 x float> %cast.rtn
}
define amdgpu_ps void @global_inc_saddr_i64_nortn(i8 addrspace(1)* inreg %sbase, i32 %voffset, i64 %data) {
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GCN-LABEL: global_inc_saddr_i64_nortn:
; GCN: ; %bb.0:
; GCN-NEXT: global_atomic_inc_x2 v0, v[1:2], s[2:3]
; GCN-NEXT: s_endpgm
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%cast.gep0 = bitcast i8 addrspace(1)* %gep0 to i64 addrspace(1)*
%unused = call i64 @llvm.amdgcn.atomic.inc.i64.p1i64(i64 addrspace(1)* %cast.gep0, i64 %data, i32 0, i32 0, i1 false)
ret void
}
define amdgpu_ps void @global_inc_saddr_i64_nortn_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, i64 %data) {
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GCN-LABEL: global_inc_saddr_i64_nortn_neg128:
; GCN: ; %bb.0:
; GCN-NEXT: global_atomic_inc_x2 v0, v[1:2], s[2:3] offset:-128
; GCN-NEXT: s_endpgm
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128
%cast.gep1 = bitcast i8 addrspace(1)* %gep1 to i64 addrspace(1)*
%unused = call i64 @llvm.amdgcn.atomic.inc.i64.p1i64(i64 addrspace(1)* %cast.gep1, i64 %data, i32 0, i32 0, i1 false)
ret void
}
; --------------------------------------------------------------------------------
; amdgcn atomic dec
; --------------------------------------------------------------------------------
declare i32 @llvm.amdgcn.atomic.dec.i32.p1i32(i32 addrspace(1)* nocapture, i32, i32 immarg, i32 immarg, i1 immarg) #0
declare i64 @llvm.amdgcn.atomic.dec.i64.p1i64(i64 addrspace(1)* nocapture, i64, i32 immarg, i32 immarg, i1 immarg) #0
define amdgpu_ps float @global_dec_saddr_i32_rtn(i8 addrspace(1)* inreg %sbase, i32 %voffset, i32 %data) {
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GCN-LABEL: global_dec_saddr_i32_rtn:
; GCN: ; %bb.0:
; GCN-NEXT: global_atomic_dec v0, v0, v1, s[2:3] glc
Revert "[AMDGPU] Insert waitcnt after returning from call" This reverts commit ca907bfb57d8ad3ec3bcc2cff2abab7b1b933af6. According to michel.daenzer, > This completely broke the Mesa radeonsi driver on Navi 14. Xorg + > xterm come up with major corruption & psychedelic colours.
2020-09-23 23:16:39 +08:00
; GCN-NEXT: s_waitcnt vmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GCN-NEXT: ; return to shader part epilog
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%cast.gep0 = bitcast i8 addrspace(1)* %gep0 to i32 addrspace(1)*
%rtn = call i32 @llvm.amdgcn.atomic.dec.i32.p1i32(i32 addrspace(1)* %cast.gep0, i32 %data, i32 0, i32 0, i1 false)
%cast.rtn = bitcast i32 %rtn to float
ret float %cast.rtn
}
define amdgpu_ps float @global_dec_saddr_i32_rtn_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, i32 %data) {
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GCN-LABEL: global_dec_saddr_i32_rtn_neg128:
; GCN: ; %bb.0:
; GCN-NEXT: global_atomic_dec v0, v0, v1, s[2:3] offset:-128 glc
Revert "[AMDGPU] Insert waitcnt after returning from call" This reverts commit ca907bfb57d8ad3ec3bcc2cff2abab7b1b933af6. According to michel.daenzer, > This completely broke the Mesa radeonsi driver on Navi 14. Xorg + > xterm come up with major corruption & psychedelic colours.
2020-09-23 23:16:39 +08:00
; GCN-NEXT: s_waitcnt vmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GCN-NEXT: ; return to shader part epilog
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128
%cast.gep1 = bitcast i8 addrspace(1)* %gep1 to i32 addrspace(1)*
%rtn = call i32 @llvm.amdgcn.atomic.dec.i32.p1i32(i32 addrspace(1)* %cast.gep1, i32 %data, i32 0, i32 0, i1 false)
%cast.rtn = bitcast i32 %rtn to float
ret float %cast.rtn
}
define amdgpu_ps void @global_dec_saddr_i32_nortn(i8 addrspace(1)* inreg %sbase, i32 %voffset, i32 %data) {
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GCN-LABEL: global_dec_saddr_i32_nortn:
; GCN: ; %bb.0:
; GCN-NEXT: global_atomic_dec v0, v1, s[2:3]
; GCN-NEXT: s_endpgm
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%cast.gep0 = bitcast i8 addrspace(1)* %gep0 to i32 addrspace(1)*
%unused = call i32 @llvm.amdgcn.atomic.dec.i32.p1i32(i32 addrspace(1)* %cast.gep0, i32 %data, i32 0, i32 0, i1 false)
ret void
}
define amdgpu_ps void @global_dec_saddr_i32_nortn_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, i32 %data) {
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GCN-LABEL: global_dec_saddr_i32_nortn_neg128:
; GCN: ; %bb.0:
; GCN-NEXT: global_atomic_dec v0, v1, s[2:3] offset:-128
; GCN-NEXT: s_endpgm
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128
%cast.gep1 = bitcast i8 addrspace(1)* %gep1 to i32 addrspace(1)*
%unused = call i32 @llvm.amdgcn.atomic.dec.i32.p1i32(i32 addrspace(1)* %cast.gep1, i32 %data, i32 0, i32 0, i1 false)
ret void
}
define amdgpu_ps <2 x float> @global_dec_saddr_i64_rtn(i8 addrspace(1)* inreg %sbase, i32 %voffset, i64 %data) {
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GCN-LABEL: global_dec_saddr_i64_rtn:
; GCN: ; %bb.0:
; GCN-NEXT: global_atomic_dec_x2 v[0:1], v0, v[1:2], s[2:3] glc
Revert "[AMDGPU] Insert waitcnt after returning from call" This reverts commit ca907bfb57d8ad3ec3bcc2cff2abab7b1b933af6. According to michel.daenzer, > This completely broke the Mesa radeonsi driver on Navi 14. Xorg + > xterm come up with major corruption & psychedelic colours.
2020-09-23 23:16:39 +08:00
; GCN-NEXT: s_waitcnt vmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GCN-NEXT: ; return to shader part epilog
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%cast.gep0 = bitcast i8 addrspace(1)* %gep0 to i64 addrspace(1)*
%rtn = call i64 @llvm.amdgcn.atomic.dec.i64.p1i64(i64 addrspace(1)* %cast.gep0, i64 %data, i32 0, i32 0, i1 false)
%cast.rtn = bitcast i64 %rtn to <2 x float>
ret <2 x float> %cast.rtn
}
define amdgpu_ps <2 x float> @global_dec_saddr_i64_rtn_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, i64 %data) {
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GCN-LABEL: global_dec_saddr_i64_rtn_neg128:
; GCN: ; %bb.0:
; GCN-NEXT: global_atomic_dec_x2 v[0:1], v0, v[1:2], s[2:3] offset:-128 glc
Revert "[AMDGPU] Insert waitcnt after returning from call" This reverts commit ca907bfb57d8ad3ec3bcc2cff2abab7b1b933af6. According to michel.daenzer, > This completely broke the Mesa radeonsi driver on Navi 14. Xorg + > xterm come up with major corruption & psychedelic colours.
2020-09-23 23:16:39 +08:00
; GCN-NEXT: s_waitcnt vmcnt(0)
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GCN-NEXT: ; return to shader part epilog
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128
%cast.gep1 = bitcast i8 addrspace(1)* %gep1 to i64 addrspace(1)*
%rtn = call i64 @llvm.amdgcn.atomic.dec.i64.p1i64(i64 addrspace(1)* %cast.gep1, i64 %data, i32 0, i32 0, i1 false)
%cast.rtn = bitcast i64 %rtn to <2 x float>
ret <2 x float> %cast.rtn
}
define amdgpu_ps void @global_dec_saddr_i64_nortn(i8 addrspace(1)* inreg %sbase, i32 %voffset, i64 %data) {
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GCN-LABEL: global_dec_saddr_i64_nortn:
; GCN: ; %bb.0:
; GCN-NEXT: global_atomic_dec_x2 v0, v[1:2], s[2:3]
; GCN-NEXT: s_endpgm
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%cast.gep0 = bitcast i8 addrspace(1)* %gep0 to i64 addrspace(1)*
%unused = call i64 @llvm.amdgcn.atomic.dec.i64.p1i64(i64 addrspace(1)* %cast.gep0, i64 %data, i32 0, i32 0, i1 false)
ret void
}
define amdgpu_ps void @global_dec_saddr_i64_nortn_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, i64 %data) {
AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.
2020-08-14 04:51:07 +08:00
; GCN-LABEL: global_dec_saddr_i64_nortn_neg128:
; GCN: ; %bb.0:
; GCN-NEXT: global_atomic_dec_x2 v0, v[1:2], s[2:3] offset:-128
; GCN-NEXT: s_endpgm
AMDGPU: Add baseline tests for global saddr matching
2020-08-16 00:31:21 +08:00
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128
%cast.gep1 = bitcast i8 addrspace(1)* %gep1 to i64 addrspace(1)*
%unused = call i64 @llvm.amdgcn.atomic.dec.i64.p1i64(i64 addrspace(1)* %cast.gep1, i64 %data, i32 0, i32 0, i1 false)
ret void
}
attributes #0 = { argmemonly nounwind willreturn }