2011-09-24 09:40:18 +08:00
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//===- Mips64InstrInfo.td - Mips64 Instruction Information -*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes Mips64 instructions.
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//
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//===----------------------------------------------------------------------===//
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2011-09-29 01:50:27 +08:00
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2011-09-30 10:08:54 +08:00
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//===----------------------------------------------------------------------===//
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// Mips Operand, Complex Patterns and Transformations Definitions.
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//===----------------------------------------------------------------------===//
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// Instruction operand types
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2011-09-30 11:18:46 +08:00
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def shamt_64 : Operand<i64>;
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2011-09-30 10:08:54 +08:00
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// Unsigned Operand
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def uimm16_64 : Operand<i64> {
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let PrintMethod = "printUnsignedImm";
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}
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2011-09-30 11:18:46 +08:00
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// Transformation Function - get Imm - 32.
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def Subtract32 : SDNodeXForm<imm, [{
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2011-12-08 04:10:24 +08:00
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return getImm(N, (unsigned)N->getZExtValue() - 32);
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2011-09-30 11:18:46 +08:00
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}]>;
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2011-12-20 03:44:09 +08:00
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// shamt must fit in 6 bits.
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def immZExt6 : ImmLeaf<i32, [{return Imm == (Imm & 0x3f);}]>;
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2011-09-30 11:18:46 +08:00
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2011-09-30 04:37:56 +08:00
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//===----------------------------------------------------------------------===//
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// Instructions specific format
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//===----------------------------------------------------------------------===//
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2012-04-18 02:03:21 +08:00
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let DecoderNamespace = "Mips64" in {
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2011-09-30 11:18:46 +08:00
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2012-12-20 12:20:09 +08:00
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multiclass Atomic2Ops64<PatFrag Op> {
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2013-08-07 07:08:38 +08:00
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def NAME : Atomic2Ops<Op, GPR64, GPR32>, Requires<[NotN64, HasStdEnc]>;
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def _P8 : Atomic2Ops<Op, GPR64, GPR64>, Requires<[IsN64, HasStdEnc]>;
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2011-11-11 12:14:30 +08:00
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}
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2012-12-20 12:20:09 +08:00
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multiclass AtomicCmpSwap64<PatFrag Op> {
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2013-08-07 07:08:38 +08:00
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def NAME : AtomicCmpSwap<Op, GPR64, GPR32>,
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2013-01-07 13:45:56 +08:00
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Requires<[NotN64, HasStdEnc]>;
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2013-08-07 07:08:38 +08:00
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def _P8 : AtomicCmpSwap<Op, GPR64, GPR64>,
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2013-08-02 07:14:16 +08:00
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Requires<[IsN64, HasStdEnc]>;
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2011-11-11 12:14:30 +08:00
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}
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2012-04-18 02:03:21 +08:00
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}
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2012-12-07 11:06:09 +08:00
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let usesCustomInserter = 1, Predicates = [HasStdEnc],
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2012-04-18 02:03:21 +08:00
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DecoderNamespace = "Mips64" in {
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2012-12-20 12:20:09 +08:00
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defm ATOMIC_LOAD_ADD_I64 : Atomic2Ops64<atomic_load_add_64>;
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defm ATOMIC_LOAD_SUB_I64 : Atomic2Ops64<atomic_load_sub_64>;
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defm ATOMIC_LOAD_AND_I64 : Atomic2Ops64<atomic_load_and_64>;
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defm ATOMIC_LOAD_OR_I64 : Atomic2Ops64<atomic_load_or_64>;
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defm ATOMIC_LOAD_XOR_I64 : Atomic2Ops64<atomic_load_xor_64>;
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defm ATOMIC_LOAD_NAND_I64 : Atomic2Ops64<atomic_load_nand_64>;
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defm ATOMIC_SWAP_I64 : Atomic2Ops64<atomic_swap_64>;
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defm ATOMIC_CMP_SWAP_I64 : AtomicCmpSwap64<atomic_cmp_swap_64>;
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2011-11-11 12:14:30 +08:00
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}
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2013-05-01 07:22:09 +08:00
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/// Pseudo instructions for loading and storing accumulator registers.
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2013-08-02 07:14:16 +08:00
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let isPseudo = 1, isCodeGenOnly = 1 in {
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defm LOAD_AC128 : LoadM<"", ACRegs128>;
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defm STORE_AC128 : StoreM<"", ACRegs128>;
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2013-03-30 08:54:52 +08:00
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}
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2011-09-30 04:37:56 +08:00
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//===----------------------------------------------------------------------===//
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// Instruction definition
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//===----------------------------------------------------------------------===//
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2012-04-18 02:03:21 +08:00
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let DecoderNamespace = "Mips64" in {
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2011-09-30 10:08:54 +08:00
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/// Arithmetic Instructions (ALU Immediate)
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2013-08-07 07:08:38 +08:00
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def DADDi : ArithLogicI<"daddi", simm16_64, GPR64Opnd>, ADDI_FM<0x18>;
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def DADDiu : ArithLogicI<"daddiu", simm16_64, GPR64Opnd, IIArith,
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2013-07-31 08:55:34 +08:00
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immSExt16, add>,
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2012-12-20 11:40:03 +08:00
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ADDI_FM<0x19>, IsAsCheapAsAMove;
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2013-08-07 07:01:10 +08:00
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let isCodeGenOnly = 1 in {
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2013-08-07 07:08:38 +08:00
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def SLTi64 : SetCC_I<"slti", setlt, simm16_64, immSExt16, GPR64Opnd>,
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2012-12-20 12:27:52 +08:00
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SLTI_FM<0xa>;
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2013-08-07 07:08:38 +08:00
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def SLTiu64 : SetCC_I<"sltiu", setult, simm16_64, immSExt16, GPR64Opnd>,
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2012-12-20 12:27:52 +08:00
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SLTI_FM<0xb>;
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2013-08-07 07:08:38 +08:00
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def ANDi64 : ArithLogicI<"andi", uimm16_64, GPR64Opnd, IILogic, immZExt16,
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2013-07-31 08:57:41 +08:00
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and>,
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ADDI_FM<0xc>;
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2013-08-07 07:08:38 +08:00
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def ORi64 : ArithLogicI<"ori", uimm16_64, GPR64Opnd, IILogic, immZExt16,
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2013-07-31 08:55:34 +08:00
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or>,
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2012-12-20 11:40:03 +08:00
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ADDI_FM<0xd>;
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2013-08-07 07:08:38 +08:00
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def XORi64 : ArithLogicI<"xori", uimm16_64, GPR64Opnd, IILogic, immZExt16,
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2013-07-31 08:55:34 +08:00
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xor>,
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2012-12-20 11:40:03 +08:00
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ADDI_FM<0xe>;
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2013-08-07 07:08:38 +08:00
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def LUi64 : LoadUpper<"lui", GPR64Opnd, uimm16_64>, LUI_FM;
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2013-08-07 07:01:10 +08:00
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}
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2011-09-30 10:08:54 +08:00
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2011-09-30 04:37:56 +08:00
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/// Arithmetic Instructions (3-Operand, R-Type)
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2013-08-07 07:08:38 +08:00
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def DADD : ArithLogicR<"dadd", GPR64Opnd>, ADD_FM<0, 0x2c>;
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def DADDu : ArithLogicR<"daddu", GPR64Opnd, 1, IIArith, add>,
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2013-01-12 09:03:14 +08:00
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ADD_FM<0, 0x2d>;
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2013-08-07 07:08:38 +08:00
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def DSUBu : ArithLogicR<"dsubu", GPR64Opnd, 0, IIArith, sub>,
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2013-01-12 09:03:14 +08:00
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ADD_FM<0, 0x2f>;
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2013-08-07 06:35:29 +08:00
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let isCodeGenOnly = 1 in {
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2013-08-07 07:08:38 +08:00
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def SLT64 : SetCC_R<"slt", setlt, GPR64Opnd>, ADD_FM<0, 0x2a>;
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def SLTu64 : SetCC_R<"sltu", setult, GPR64Opnd>, ADD_FM<0, 0x2b>;
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def AND64 : ArithLogicR<"and", GPR64Opnd, 1, IIArith, and>, ADD_FM<0, 0x24>;
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def OR64 : ArithLogicR<"or", GPR64Opnd, 1, IIArith, or>, ADD_FM<0, 0x25>;
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def XOR64 : ArithLogicR<"xor", GPR64Opnd, 1, IIArith, xor>, ADD_FM<0, 0x26>;
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def NOR64 : LogicNOR<"nor", GPR64Opnd>, ADD_FM<0, 0x27>;
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2013-08-07 06:35:29 +08:00
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}
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2011-09-30 11:18:46 +08:00
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/// Shift Instructions
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2013-08-07 07:08:38 +08:00
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def DSLL : shift_rotate_imm<"dsll", shamt, GPR64Opnd, shl, immZExt6>,
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2013-01-05 03:25:46 +08:00
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SRA_FM<0x38, 0>;
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2013-08-07 07:08:38 +08:00
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def DSRL : shift_rotate_imm<"dsrl", shamt, GPR64Opnd, srl, immZExt6>,
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2013-01-05 03:25:46 +08:00
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SRA_FM<0x3a, 0>;
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2013-08-07 07:08:38 +08:00
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def DSRA : shift_rotate_imm<"dsra", shamt, GPR64Opnd, sra, immZExt6>,
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2013-01-05 03:25:46 +08:00
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SRA_FM<0x3b, 0>;
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2013-08-07 07:08:38 +08:00
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def DSLLV : shift_rotate_reg<"dsllv", GPR64Opnd, shl>, SRLV_FM<0x14, 0>;
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def DSRLV : shift_rotate_reg<"dsrlv", GPR64Opnd, srl>, SRLV_FM<0x16, 0>;
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def DSRAV : shift_rotate_reg<"dsrav", GPR64Opnd, sra>, SRLV_FM<0x17, 0>;
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def DSLL32 : shift_rotate_imm<"dsll32", shamt, GPR64Opnd>, SRA_FM<0x3c, 0>;
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def DSRL32 : shift_rotate_imm<"dsrl32", shamt, GPR64Opnd>, SRA_FM<0x3e, 0>;
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def DSRA32 : shift_rotate_imm<"dsra32", shamt, GPR64Opnd>, SRA_FM<0x3f, 0>;
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2013-08-07 07:01:10 +08:00
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2011-10-01 02:51:46 +08:00
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// Rotate Instructions
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2013-08-07 07:01:10 +08:00
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let Predicates = [HasMips64r2, HasStdEnc] in {
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2013-08-07 07:08:38 +08:00
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def DROTR : shift_rotate_imm<"drotr", shamt, GPR64Opnd, rotr, immZExt6>,
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2013-01-19 04:15:06 +08:00
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SRA_FM<0x3a, 1>;
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2013-08-07 07:08:38 +08:00
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def DROTRV : shift_rotate_reg<"drotrv", GPR64Opnd, rotr>,
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2013-01-19 04:15:06 +08:00
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SRLV_FM<0x16, 1>;
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2011-10-01 02:51:46 +08:00
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}
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2011-10-11 08:27:28 +08:00
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/// Load and Store Instructions
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2012-02-28 15:46:26 +08:00
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/// aligned
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2013-08-07 07:01:10 +08:00
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let isCodeGenOnly = 1 in {
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2013-08-07 07:08:38 +08:00
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defm LB64 : LoadM<"lb", GPR64Opnd, sextloadi8, IILoad>, LW_FM<0x20>;
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defm LBu64 : LoadM<"lbu", GPR64Opnd, zextloadi8, IILoad>, LW_FM<0x24>;
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defm LH64 : LoadM<"lh", GPR64Opnd, sextloadi16, IILoad>, LW_FM<0x21>;
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defm LHu64 : LoadM<"lhu", GPR64Opnd, zextloadi16, IILoad>, LW_FM<0x25>;
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defm LW64 : LoadM<"lw", GPR64Opnd, sextloadi32, IILoad>, LW_FM<0x23>;
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defm SB64 : StoreM<"sb", GPR64Opnd, truncstorei8, IIStore>, LW_FM<0x28>;
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defm SH64 : StoreM<"sh", GPR64Opnd, truncstorei16, IIStore>, LW_FM<0x29>;
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defm SW64 : StoreM<"sw", GPR64Opnd, truncstorei32, IIStore>, LW_FM<0x2b>;
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2013-08-07 07:01:10 +08:00
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}
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2013-08-07 07:08:38 +08:00
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defm LWu : LoadM<"lwu", GPR64Opnd, zextloadi32, IILoad>, LW_FM<0x27>;
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defm LD : LoadM<"ld", GPR64Opnd, load, IILoad>, LW_FM<0x37>;
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defm SD : StoreM<"sd", GPR64Opnd, store, IIStore>, LW_FM<0x3f>;
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2011-10-11 08:27:28 +08:00
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2012-06-02 08:04:19 +08:00
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/// load/store left/right
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2013-08-07 07:01:10 +08:00
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let isCodeGenOnly = 1 in {
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2013-08-07 07:08:38 +08:00
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defm LWL64 : LoadLeftRightM<"lwl", MipsLWL, GPR64Opnd>, LW_FM<0x22>;
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defm LWR64 : LoadLeftRightM<"lwr", MipsLWR, GPR64Opnd>, LW_FM<0x26>;
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defm SWL64 : StoreLeftRightM<"swl", MipsSWL, GPR64Opnd>, LW_FM<0x2a>;
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defm SWR64 : StoreLeftRightM<"swr", MipsSWR, GPR64Opnd>, LW_FM<0x2e>;
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2013-08-07 07:01:10 +08:00
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}
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2013-01-12 09:03:14 +08:00
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2013-08-07 07:08:38 +08:00
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defm LDL : LoadLeftRightM<"ldl", MipsLDL, GPR64Opnd>, LW_FM<0x1a>;
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defm LDR : LoadLeftRightM<"ldr", MipsLDR, GPR64Opnd>, LW_FM<0x1b>;
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defm SDL : StoreLeftRightM<"sdl", MipsSDL, GPR64Opnd>, LW_FM<0x2c>;
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defm SDR : StoreLeftRightM<"sdr", MipsSDR, GPR64Opnd>, LW_FM<0x2d>;
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2012-06-02 08:04:19 +08:00
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2011-11-11 12:14:30 +08:00
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/// Load-linked, Store-conditional
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2012-12-22 07:01:24 +08:00
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let Predicates = [NotN64, HasStdEnc] in {
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2013-08-07 07:08:38 +08:00
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def LLD : LLBase<"lld", GPR64Opnd, mem>, LW_FM<0x34>;
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def SCD : SCBase<"scd", GPR64Opnd, mem>, LW_FM<0x3c>;
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2012-04-18 02:03:21 +08:00
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}
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2012-12-22 07:01:24 +08:00
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let Predicates = [IsN64, HasStdEnc], isCodeGenOnly = 1 in {
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2013-08-07 07:08:38 +08:00
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def LLD_P8 : LLBase<"lld", GPR64Opnd, mem64>, LW_FM<0x34>;
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def SCD_P8 : SCBase<"scd", GPR64Opnd, mem64>, LW_FM<0x3c>;
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2012-04-18 02:03:21 +08:00
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}
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2011-11-11 12:14:30 +08:00
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2011-10-12 02:49:17 +08:00
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/// Jump and Branch Instructions
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2013-08-07 07:01:10 +08:00
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let isCodeGenOnly = 1 in {
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2013-08-07 07:08:38 +08:00
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def JR64 : IndirectBranch<GPR64Opnd>, MTLO_FM<8>;
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def BEQ64 : CBranch<"beq", seteq, GPR64Opnd>, BEQ_FM<4>;
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def BNE64 : CBranch<"bne", setne, GPR64Opnd>, BEQ_FM<5>;
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def BGEZ64 : CBranchZero<"bgez", setge, GPR64Opnd>, BGEZ_FM<1, 1>;
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def BGTZ64 : CBranchZero<"bgtz", setgt, GPR64Opnd>, BGEZ_FM<7, 0>;
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def BLEZ64 : CBranchZero<"blez", setle, GPR64Opnd>, BGEZ_FM<6, 0>;
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def BLTZ64 : CBranchZero<"bltz", setlt, GPR64Opnd>, BGEZ_FM<1, 0>;
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def JALR64 : JumpLinkReg<"jalr", GPR64Opnd>, JALR_FM;
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def JALR64Pseudo : JumpLinkRegPseudo<GPR64Opnd, JALR, RA, GPR32Opnd>;
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def TAILCALL64_R : JumpFR<GPR64Opnd, MipsTailCall>, MTLO_FM<8>, IsTailCall;
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2013-08-07 07:01:10 +08:00
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}
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2012-01-04 11:02:47 +08:00
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2011-10-04 04:01:11 +08:00
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/// Multiply and Divide Instructions.
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2013-08-07 07:08:38 +08:00
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def DMULT : Mult<"dmult", IIImult, GPR64Opnd, [HI64, LO64]>,
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2013-01-19 04:15:06 +08:00
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MULT_FM<0, 0x1c>;
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2013-08-07 07:08:38 +08:00
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def DMULTu : Mult<"dmultu", IIImult, GPR64Opnd, [HI64, LO64]>,
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2013-01-19 04:15:06 +08:00
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MULT_FM<0, 0x1d>;
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2013-08-07 07:08:38 +08:00
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def PseudoDMULT : MultDivPseudo<DMULT, ACRegs128, GPR64Opnd, MipsMult,
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2013-07-13 06:43:20 +08:00
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IIImult>;
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2013-08-07 07:08:38 +08:00
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def PseudoDMULTu : MultDivPseudo<DMULTu, ACRegs128, GPR64Opnd, MipsMultu,
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2013-07-13 06:43:20 +08:00
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IIImult>;
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2013-08-07 07:08:38 +08:00
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def DSDIV : Div<"ddiv", IIIdiv, GPR64Opnd, [HI64, LO64]>, MULT_FM<0, 0x1e>;
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def DUDIV : Div<"ddivu", IIIdiv, GPR64Opnd, [HI64, LO64]>, MULT_FM<0, 0x1f>;
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def PseudoDSDIV : MultDivPseudo<DSDIV, ACRegs128, GPR64Opnd, MipsDivRem,
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2013-05-21 02:07:43 +08:00
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IIIdiv, 0, 1, 1>;
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2013-08-07 07:08:38 +08:00
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def PseudoDUDIV : MultDivPseudo<DUDIV, ACRegs128, GPR64Opnd, MipsDivRemU,
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2013-05-21 02:07:43 +08:00
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IIIdiv, 0, 1, 1>;
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2011-10-04 04:01:11 +08:00
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2013-08-07 07:01:10 +08:00
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let isCodeGenOnly = 1 in {
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2013-08-07 07:08:38 +08:00
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def MTHI64 : MoveToLOHI<"mthi", GPR64Opnd, [HI64]>, MTLO_FM<0x11>;
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def MTLO64 : MoveToLOHI<"mtlo", GPR64Opnd, [LO64]>, MTLO_FM<0x13>;
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def MFHI64 : MoveFromLOHI<"mfhi", GPR64Opnd, [HI64]>, MFLO_FM<0x10>;
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def MFLO64 : MoveFromLOHI<"mflo", GPR64Opnd, [LO64]>, MFLO_FM<0x12>;
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2011-10-04 03:28:44 +08:00
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2012-01-25 05:41:09 +08:00
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/// Sign Ext In Register Instructions.
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2013-08-07 07:08:38 +08:00
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def SEB64 : SignExtInReg<"seb", i8, GPR64Opnd>, SEB_FM<0x10, 0x20>;
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def SEH64 : SignExtInReg<"seh", i16, GPR64Opnd>, SEB_FM<0x18, 0x20>;
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2013-08-07 07:01:10 +08:00
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}
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2012-01-25 05:41:09 +08:00
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2011-10-04 05:16:50 +08:00
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/// Count Leading
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2013-08-07 07:08:38 +08:00
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def DCLZ : CountLeading0<"dclz", GPR64Opnd>, CLO_FM<0x24>;
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def DCLO : CountLeading1<"dclo", GPR64Opnd>, CLO_FM<0x25>;
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2011-10-04 05:16:50 +08:00
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2011-12-21 07:56:43 +08:00
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/// Double Word Swap Bytes/HalfWords
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2013-08-07 07:08:38 +08:00
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def DSBH : SubwordSwap<"dsbh", GPR64Opnd>, SEB_FM<2, 0x24>;
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def DSHD : SubwordSwap<"dshd", GPR64Opnd>, SEB_FM<5, 0x24>;
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2012-12-22 07:21:32 +08:00
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2013-08-07 07:08:38 +08:00
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def LEA_ADDiu64 : EffectiveAddress<"daddiu", GPR64Opnd, mem_ea_64>, LW_FM<0x19>;
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2011-12-21 07:56:43 +08:00
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2013-08-07 07:01:10 +08:00
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let isCodeGenOnly = 1 in
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2013-08-07 07:08:38 +08:00
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def RDHWR64 : ReadHardware<GPR64Opnd, HW64RegsOpnd>, RDHWR_FM;
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2011-12-08 07:31:26 +08:00
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2013-08-07 07:08:38 +08:00
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def DEXT : ExtBase<"dext", GPR64Opnd>, EXT_FM<3>;
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2012-08-29 04:07:41 +08:00
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let Pattern = []<dag> in {
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2013-08-07 07:08:38 +08:00
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def DEXTU : ExtBase<"dextu", GPR64Opnd>, EXT_FM<2>;
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def DEXTM : ExtBase<"dextm", GPR64Opnd>, EXT_FM<1>;
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2012-08-29 04:07:41 +08:00
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}
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2013-08-07 07:08:38 +08:00
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def DINS : InsBase<"dins", GPR64Opnd>, EXT_FM<7>;
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2012-09-01 02:06:48 +08:00
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let Pattern = []<dag> in {
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2013-08-07 07:08:38 +08:00
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def DINSU : InsBase<"dinsu", GPR64Opnd>, EXT_FM<6>;
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def DINSM : InsBase<"dinsm", GPR64Opnd>, EXT_FM<5>;
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2012-09-01 02:06:48 +08:00
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}
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2011-12-06 05:26:34 +08:00
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2012-08-07 08:35:22 +08:00
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let isCodeGenOnly = 1, rs = 0, shamt = 0 in {
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2013-08-07 07:08:38 +08:00
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def DSLL64_32 : FR<0x00, 0x3c, (outs GPR64:$rd), (ins GPR32:$rt),
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2013-07-31 08:55:34 +08:00
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"dsll\t$rd, $rt, 32", [], IIArith>;
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2013-08-07 07:08:38 +08:00
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def SLL64_32 : FR<0x0, 0x00, (outs GPR64:$rd), (ins GPR32:$rt),
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2013-07-31 08:55:34 +08:00
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"sll\t$rd, $rt, 0", [], IIArith>;
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2013-08-07 07:08:38 +08:00
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def SLL64_64 : FR<0x0, 0x00, (outs GPR64:$rd), (ins GPR64:$rt),
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2013-07-31 08:55:34 +08:00
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"sll\t$rd, $rt, 0", [], IIArith>;
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2012-08-07 08:35:22 +08:00
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}
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2012-04-18 02:03:21 +08:00
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}
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2011-10-01 02:51:46 +08:00
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//===----------------------------------------------------------------------===//
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// Arbitrary patterns that map to one or more instructions
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//===----------------------------------------------------------------------===//
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2011-11-15 03:06:14 +08:00
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// extended loads
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2012-12-07 11:06:09 +08:00
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let Predicates = [NotN64, HasStdEnc] in {
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2012-06-15 05:03:23 +08:00
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def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64 addr:$src)>;
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def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64 addr:$src)>;
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2012-09-15 09:52:08 +08:00
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def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64 addr:$src)>;
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def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64 addr:$src)>;
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2011-11-15 03:06:14 +08:00
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}
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2012-12-07 11:06:09 +08:00
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let Predicates = [IsN64, HasStdEnc] in {
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2012-06-15 05:03:23 +08:00
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def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64_P8 addr:$src)>;
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def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64_P8 addr:$src)>;
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2012-09-15 09:52:08 +08:00
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def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64_P8 addr:$src)>;
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def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64_P8 addr:$src)>;
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2011-11-15 03:06:14 +08:00
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}
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2011-10-11 08:55:05 +08:00
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// hi/lo relocs
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2012-06-15 05:03:23 +08:00
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def : MipsPat<(MipsHi tglobaladdr:$in), (LUi64 tglobaladdr:$in)>;
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def : MipsPat<(MipsHi tblockaddress:$in), (LUi64 tblockaddress:$in)>;
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def : MipsPat<(MipsHi tjumptable:$in), (LUi64 tjumptable:$in)>;
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def : MipsPat<(MipsHi tconstpool:$in), (LUi64 tconstpool:$in)>;
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def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi64 tglobaltlsaddr:$in)>;
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2012-11-22 04:40:38 +08:00
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def : MipsPat<(MipsHi texternalsym:$in), (LUi64 texternalsym:$in)>;
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2012-06-15 05:03:23 +08:00
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def : MipsPat<(MipsLo tglobaladdr:$in), (DADDiu ZERO_64, tglobaladdr:$in)>;
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def : MipsPat<(MipsLo tblockaddress:$in), (DADDiu ZERO_64, tblockaddress:$in)>;
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def : MipsPat<(MipsLo tjumptable:$in), (DADDiu ZERO_64, tjumptable:$in)>;
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def : MipsPat<(MipsLo tconstpool:$in), (DADDiu ZERO_64, tconstpool:$in)>;
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def : MipsPat<(MipsLo tglobaltlsaddr:$in),
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(DADDiu ZERO_64, tglobaltlsaddr:$in)>;
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2012-11-22 04:40:38 +08:00
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def : MipsPat<(MipsLo texternalsym:$in), (DADDiu ZERO_64, texternalsym:$in)>;
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2012-06-15 05:03:23 +08:00
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2013-08-07 07:08:38 +08:00
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def : MipsPat<(add GPR64:$hi, (MipsLo tglobaladdr:$lo)),
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(DADDiu GPR64:$hi, tglobaladdr:$lo)>;
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def : MipsPat<(add GPR64:$hi, (MipsLo tblockaddress:$lo)),
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(DADDiu GPR64:$hi, tblockaddress:$lo)>;
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def : MipsPat<(add GPR64:$hi, (MipsLo tjumptable:$lo)),
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(DADDiu GPR64:$hi, tjumptable:$lo)>;
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def : MipsPat<(add GPR64:$hi, (MipsLo tconstpool:$lo)),
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(DADDiu GPR64:$hi, tconstpool:$lo)>;
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def : MipsPat<(add GPR64:$hi, (MipsLo tglobaltlsaddr:$lo)),
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(DADDiu GPR64:$hi, tglobaltlsaddr:$lo)>;
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def : WrapperPat<tglobaladdr, DADDiu, GPR64>;
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def : WrapperPat<tconstpool, DADDiu, GPR64>;
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def : WrapperPat<texternalsym, DADDiu, GPR64>;
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def : WrapperPat<tblockaddress, DADDiu, GPR64>;
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def : WrapperPat<tjumptable, DADDiu, GPR64>;
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def : WrapperPat<tglobaltlsaddr, DADDiu, GPR64>;
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defm : BrcondPats<GPR64, BEQ64, BNE64, SLT64, SLTu64, SLTi64, SLTiu64,
|
2011-10-12 03:09:09 +08:00
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ZERO_64>;
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|
2013-05-22 01:13:47 +08:00
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def : MipsPat<(brcond (i32 (setlt i64:$lhs, 1)), bb:$dst),
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(BLEZ64 i64:$lhs, bb:$dst)>;
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def : MipsPat<(brcond (i32 (setgt i64:$lhs, -1)), bb:$dst),
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(BGEZ64 i64:$lhs, bb:$dst)>;
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|
2011-10-12 02:53:46 +08:00
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// setcc patterns
|
2013-08-07 07:08:38 +08:00
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defm : SeteqPats<GPR64, SLTiu64, XOR64, SLTu64, ZERO_64>;
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defm : SetlePats<GPR64, SLT64, SLTu64>;
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defm : SetgtPats<GPR64, SLT64, SLTu64>;
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defm : SetgePats<GPR64, SLT64, SLTu64>;
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defm : SetgeImmPats<GPR64, SLTi64, SLTiu64>;
|
2011-11-08 02:57:41 +08:00
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// truncate
|
2013-08-07 07:08:38 +08:00
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def : MipsPat<(i32 (trunc GPR64:$src)),
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(SLL (EXTRACT_SUBREG GPR64:$src, sub_32), 0)>,
|
2012-12-07 11:06:09 +08:00
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Requires<[IsN64, HasStdEnc]>;
|
2012-02-28 15:46:26 +08:00
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2011-12-08 07:14:41 +08:00
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// 32-to-64-bit extension
|
2013-08-07 07:08:38 +08:00
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def : MipsPat<(i64 (anyext GPR32:$src)), (SLL64_32 GPR32:$src)>;
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def : MipsPat<(i64 (zext GPR32:$src)), (DSRL (DSLL64_32 GPR32:$src), 32)>;
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def : MipsPat<(i64 (sext GPR32:$src)), (SLL64_32 GPR32:$src)>;
|
2011-12-21 06:06:20 +08:00
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2011-12-21 06:40:40 +08:00
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// Sign extend in register
|
2013-08-07 07:08:38 +08:00
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def : MipsPat<(i64 (sext_inreg GPR64:$src, i32)),
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(SLL64_64 GPR64:$src)>;
|
2011-12-21 06:40:40 +08:00
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2012-06-15 05:03:23 +08:00
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// bswap MipsPattern
|
2013-08-07 07:08:38 +08:00
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def : MipsPat<(bswap GPR64:$rt), (DSHD (DSBH GPR64:$rt))>;
|
2012-10-10 00:27:43 +08:00
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2013-03-30 09:36:35 +08:00
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// mflo/hi patterns.
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def : MipsPat<(i64 (ExtractLOHI ACRegs128:$ac, imm:$lohi_idx)),
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(EXTRACT_SUBREG ACRegs128:$ac, imm:$lohi_idx)>;
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|
2012-10-10 00:27:43 +08:00
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//===----------------------------------------------------------------------===//
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// Instruction aliases
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//===----------------------------------------------------------------------===//
|
2013-02-05 16:32:10 +08:00
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def : InstAlias<"move $dst, $src",
|
2013-08-07 07:08:38 +08:00
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(DADDu GPR64Opnd:$dst, GPR64Opnd:$src, ZERO_64), 1>,
|
2013-01-19 04:15:06 +08:00
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Requires<[HasMips64]>;
|
2013-01-12 09:03:14 +08:00
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def : InstAlias<"daddu $rs, $rt, $imm",
|
2013-08-07 07:08:38 +08:00
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(DADDiu GPR64Opnd:$rs, GPR64Opnd:$rt, simm16_64:$imm),
|
2013-08-07 06:35:29 +08:00
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0>;
|
2013-01-12 09:03:14 +08:00
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def : InstAlias<"dadd $rs, $rt, $imm",
|
2013-08-07 07:08:38 +08:00
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(DADDi GPR64Opnd:$rs, GPR64Opnd:$rt, simm16_64:$imm),
|
2013-08-07 06:35:29 +08:00
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0>;
|
2013-01-19 04:15:06 +08:00
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2013-05-17 03:40:19 +08:00
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/// Move between CPU and coprocessor registers
|
2012-10-11 18:21:34 +08:00
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let DecoderNamespace = "Mips64" in {
|
2013-08-07 07:08:38 +08:00
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def DMFC0_3OP64 : MFC3OP<(outs GPR64Opnd:$rt),
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(ins GPR64Opnd:$rd, uimm16:$sel),
|
2013-01-05 03:13:49 +08:00
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"dmfc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 1>;
|
2013-08-07 07:08:38 +08:00
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def DMTC0_3OP64 : MFC3OP<(outs GPR64Opnd:$rd, uimm16:$sel),
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(ins GPR64Opnd:$rt),
|
2013-01-05 03:13:49 +08:00
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"dmtc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 5>;
|
2013-08-07 07:08:38 +08:00
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def DMFC2_3OP64 : MFC3OP<(outs GPR64Opnd:$rt),
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(ins GPR64Opnd:$rd, uimm16:$sel),
|
2013-01-05 03:13:49 +08:00
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"dmfc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 1>;
|
2013-08-07 07:08:38 +08:00
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def DMTC2_3OP64 : MFC3OP<(outs GPR64Opnd:$rd, uimm16:$sel),
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(ins GPR64Opnd:$rt),
|
2013-01-05 03:13:49 +08:00
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"dmtc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 5>;
|
2012-10-11 18:21:34 +08:00
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}
|
2013-01-19 04:15:06 +08:00
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|
2012-10-11 18:21:34 +08:00
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// Two operand (implicit 0 selector) versions:
|
2013-01-05 03:38:05 +08:00
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def : InstAlias<"dmfc0 $rt, $rd",
|
2013-08-07 07:08:38 +08:00
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(DMFC0_3OP64 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>;
|
2013-01-05 03:38:05 +08:00
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def : InstAlias<"dmtc0 $rt, $rd",
|
2013-08-07 07:08:38 +08:00
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(DMTC0_3OP64 GPR64Opnd:$rd, 0, GPR64Opnd:$rt), 0>;
|
2013-01-05 03:38:05 +08:00
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def : InstAlias<"dmfc2 $rt, $rd",
|
2013-08-07 07:08:38 +08:00
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(DMFC2_3OP64 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>;
|
2013-01-05 03:38:05 +08:00
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|
def : InstAlias<"dmtc2 $rt, $rd",
|
2013-08-07 07:08:38 +08:00
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(DMTC2_3OP64 GPR64Opnd:$rd, 0, GPR64Opnd:$rt), 0>;
|
2012-10-11 18:21:34 +08:00
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