2017-05-31 09:10:10 +08:00
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//===- lib/CodeGen/MachineInstr.cpp ---------------------------------------===//
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2005-04-22 06:36:52 +08:00
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//
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2003-10-21 03:43:21 +08:00
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// The LLVM Compiler Infrastructure
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//
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2007-12-30 04:36:04 +08:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2005-04-22 06:36:52 +08:00
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//
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2003-10-21 03:43:21 +08:00
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//===----------------------------------------------------------------------===//
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2004-02-13 12:39:32 +08:00
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//
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// Methods common to all machine instructions.
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//
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2002-08-10 04:08:06 +08:00
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//===----------------------------------------------------------------------===//
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2001-07-21 20:41:50 +08:00
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2017-06-06 19:49:48 +08:00
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#include "llvm/CodeGen/MachineInstr.h"
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2017-05-31 09:10:10 +08:00
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#include "llvm/ADT/APFloat.h"
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#include "llvm/ADT/ArrayRef.h"
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2012-12-04 00:50:05 +08:00
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#include "llvm/ADT/FoldingSet.h"
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#include "llvm/ADT/Hashing.h"
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2017-05-31 09:10:10 +08:00
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#include "llvm/ADT/None.h"
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2017-06-06 19:49:48 +08:00
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#include "llvm/ADT/STLExtras.h"
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2017-05-31 09:10:10 +08:00
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#include "llvm/ADT/SmallString.h"
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#include "llvm/ADT/SmallVector.h"
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2012-12-04 00:50:05 +08:00
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#include "llvm/Analysis/AliasAnalysis.h"
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2017-06-24 23:17:38 +08:00
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#include "llvm/Analysis/Loads.h"
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2017-05-31 09:10:10 +08:00
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#include "llvm/Analysis/MemoryLocation.h"
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#include "llvm/CodeGen/GlobalISel/RegisterBank.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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2004-02-20 00:17:08 +08:00
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#include "llvm/CodeGen/MachineFunction.h"
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2016-04-15 02:29:59 +08:00
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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2017-05-31 09:10:10 +08:00
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#include "llvm/CodeGen/MachineInstrBundle.h"
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2009-09-26 04:36:54 +08:00
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#include "llvm/CodeGen/MachineMemOperand.h"
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2011-07-02 11:53:34 +08:00
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#include "llvm/CodeGen/MachineModuleInfo.h"
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2017-05-31 09:10:10 +08:00
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#include "llvm/CodeGen/MachineOperand.h"
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2008-01-01 09:12:31 +08:00
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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2008-02-07 06:27:42 +08:00
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#include "llvm/CodeGen/PseudoSourceValue.h"
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2013-01-02 19:36:10 +08:00
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#include "llvm/IR/Constants.h"
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2017-05-31 09:10:10 +08:00
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#include "llvm/IR/DebugInfoMetadata.h"
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#include "llvm/IR/DebugLoc.h"
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#include "llvm/IR/DerivedTypes.h"
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2013-01-02 19:36:10 +08:00
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#include "llvm/IR/Function.h"
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#include "llvm/IR/InlineAsm.h"
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2017-05-31 09:10:10 +08:00
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#include "llvm/IR/InstrTypes.h"
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2016-07-30 04:32:59 +08:00
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#include "llvm/IR/Intrinsics.h"
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2013-01-02 19:36:10 +08:00
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#include "llvm/IR/LLVMContext.h"
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#include "llvm/IR/Metadata.h"
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#include "llvm/IR/Module.h"
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2015-06-27 06:06:47 +08:00
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#include "llvm/IR/ModuleSlotTracker.h"
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2013-01-02 19:36:10 +08:00
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#include "llvm/IR/Type.h"
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#include "llvm/IR/Value.h"
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2011-06-29 03:10:37 +08:00
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#include "llvm/MC/MCInstrDesc.h"
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2017-05-31 09:10:10 +08:00
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#include "llvm/MC/MCRegisterInfo.h"
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2017-06-06 19:49:48 +08:00
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#include "llvm/MC/MCSymbol.h"
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2017-05-31 09:10:10 +08:00
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#include "llvm/Support/Casting.h"
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2015-08-19 20:03:04 +08:00
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#include "llvm/Support/CommandLine.h"
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2017-05-31 09:10:10 +08:00
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#include "llvm/Support/Compiler.h"
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2010-01-05 07:48:20 +08:00
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#include "llvm/Support/Debug.h"
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2009-07-12 04:10:48 +08:00
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#include "llvm/Support/ErrorHandling.h"
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2017-05-31 09:10:10 +08:00
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#include "llvm/Support/LowLevelTypeImpl.h"
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2008-07-08 04:32:02 +08:00
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#include "llvm/Support/MathExtras.h"
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2008-08-25 04:37:32 +08:00
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#include "llvm/Support/raw_ostream.h"
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2012-12-04 00:50:05 +08:00
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#include "llvm/Target/TargetInstrInfo.h"
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2016-07-30 04:32:59 +08:00
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#include "llvm/Target/TargetIntrinsicInfo.h"
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2012-12-04 00:50:05 +08:00
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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2014-08-05 05:25:23 +08:00
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#include "llvm/Target/TargetSubtargetInfo.h"
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2017-05-31 09:10:10 +08:00
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#include <algorithm>
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#include <cassert>
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#include <cstddef>
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#include <cstdint>
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#include <cstring>
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#include <iterator>
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#include <utility>
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2004-02-24 02:38:20 +08:00
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using namespace llvm;
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2003-11-12 06:41:34 +08:00
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2017-07-20 08:37:31 +08:00
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static cl::opt<int> PrintRegMaskNumRegs(
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"print-regmask-num-regs",
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cl::desc("Number of registers to limit to when "
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"printing regmask operands in IR dumps. "
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"unlimited = -1"),
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cl::init(32), cl::Hidden);
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2015-08-19 20:03:04 +08:00
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2007-12-31 05:56:09 +08:00
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//===----------------------------------------------------------------------===//
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// MachineOperand Implementation
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//===----------------------------------------------------------------------===//
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2008-01-01 09:12:31 +08:00
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void MachineOperand::setReg(unsigned Reg) {
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if (getReg() == Reg) return; // No change.
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2011-08-25 00:44:17 +08:00
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2008-01-01 09:12:31 +08:00
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// Otherwise, we have to change the register. If this operand is embedded
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// into a machine function, we need to update the old and new register's
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// use/def lists.
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if (MachineInstr *MI = getParent())
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if (MachineBasicBlock *MBB = MI->getParent())
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if (MachineFunction *MF = MBB->getParent()) {
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2012-08-10 06:49:37 +08:00
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MachineRegisterInfo &MRI = MF->getRegInfo();
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MRI.removeRegOperandFromUseList(this);
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2010-10-20 04:56:32 +08:00
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SmallContents.RegNo = Reg;
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2012-08-10 06:49:37 +08:00
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MRI.addRegOperandToUseList(this);
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2008-01-01 09:12:31 +08:00
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return;
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}
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2011-08-25 00:44:17 +08:00
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2008-01-01 09:12:31 +08:00
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// Otherwise, just change the register, no problem. :)
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2010-10-20 04:56:32 +08:00
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SmallContents.RegNo = Reg;
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2008-01-01 09:12:31 +08:00
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}
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2010-05-29 02:18:53 +08:00
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void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx,
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const TargetRegisterInfo &TRI) {
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assert(TargetRegisterInfo::isVirtualRegister(Reg));
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if (SubIdx && getSubReg())
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SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
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setReg(Reg);
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2010-06-02 06:39:25 +08:00
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if (SubIdx)
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setSubReg(SubIdx);
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2010-05-29 02:18:53 +08:00
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}
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void MachineOperand::substPhysReg(unsigned Reg, const TargetRegisterInfo &TRI) {
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assert(TargetRegisterInfo::isPhysicalRegister(Reg));
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if (getSubReg()) {
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Reg = TRI.getSubReg(Reg, getSubReg());
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2011-05-09 03:21:08 +08:00
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// Note that getSubReg() may return 0 if the sub-register doesn't exist.
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// That won't happen in legal code.
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2010-05-29 02:18:53 +08:00
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setSubReg(0);
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2016-08-22 22:50:12 +08:00
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if (isDef())
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setIsUndef(false);
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2010-05-29 02:18:53 +08:00
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}
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setReg(Reg);
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}
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2012-08-10 08:21:26 +08:00
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/// Change a def to a use, or a use to a def.
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void MachineOperand::setIsDef(bool Val) {
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assert(isReg() && "Wrong MachineOperand accessor");
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assert((!Val || !isDebug()) && "Marking a debug operation as def");
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if (IsDef == Val)
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return;
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// MRI may keep uses and defs in different list positions.
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if (MachineInstr *MI = getParent())
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if (MachineBasicBlock *MBB = MI->getParent())
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if (MachineFunction *MF = MBB->getParent()) {
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MachineRegisterInfo &MRI = MF->getRegInfo();
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MRI.removeRegOperandFromUseList(this);
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IsDef = Val;
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MRI.addRegOperandToUseList(this);
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return;
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}
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IsDef = Val;
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}
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2014-09-29 03:24:59 +08:00
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// If this operand is currently a register operand, and if this is in a
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// function, deregister the operand from the register's use/def list.
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void MachineOperand::removeRegFromUses() {
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if (!isReg() || !isOnRegUseList())
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return;
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if (MachineInstr *MI = getParent()) {
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if (MachineBasicBlock *MBB = MI->getParent()) {
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if (MachineFunction *MF = MBB->getParent())
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MF->getRegInfo().removeRegOperandFromUseList(this);
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}
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}
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}
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2008-01-01 09:12:31 +08:00
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/// ChangeToImmediate - Replace this operand with a new immediate operand of
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/// the specified value. If an operand is known to be an immediate already,
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/// the setImm method should be used.
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void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
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2012-08-29 08:37:58 +08:00
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assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
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2014-09-29 03:24:59 +08:00
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removeRegFromUses();
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2011-08-25 00:44:17 +08:00
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2008-01-01 09:12:31 +08:00
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OpKind = MO_Immediate;
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Contents.ImmVal = ImmVal;
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}
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2014-09-29 03:24:59 +08:00
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void MachineOperand::ChangeToFPImmediate(const ConstantFP *FPImm) {
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assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
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removeRegFromUses();
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OpKind = MO_FPImmediate;
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Contents.CFP = FPImm;
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}
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2015-05-07 01:05:54 +08:00
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void MachineOperand::ChangeToES(const char *SymName, unsigned char TargetFlags) {
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assert((!isReg() || !isTied()) &&
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"Cannot change a tied operand into an external symbol");
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removeRegFromUses();
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OpKind = MO_ExternalSymbol;
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Contents.OffsetedInfo.Val.SymbolName = SymName;
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setOffset(0); // Offset is always 0.
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setTargetFlags(TargetFlags);
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}
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void MachineOperand::ChangeToMCSymbol(MCSymbol *Sym) {
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assert((!isReg() || !isTied()) &&
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"Cannot change a tied operand into an MCSymbol");
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removeRegFromUses();
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OpKind = MO_MCSymbol;
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Contents.Sym = Sym;
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}
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2016-09-14 03:03:12 +08:00
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void MachineOperand::ChangeToFrameIndex(int Idx) {
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assert((!isReg() || !isTied()) &&
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"Cannot change a tied operand into a FrameIndex");
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removeRegFromUses();
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OpKind = MO_FrameIndex;
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setIndex(Idx);
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}
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2017-08-05 02:24:09 +08:00
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void MachineOperand::ChangeToTargetIndex(unsigned Idx, int64_t Offset,
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unsigned char TargetFlags) {
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assert((!isReg() || !isTied()) &&
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"Cannot change a tied operand into a FrameIndex");
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removeRegFromUses();
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OpKind = MO_TargetIndex;
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setIndex(Idx);
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setOffset(Offset);
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setTargetFlags(TargetFlags);
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}
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2008-01-01 09:12:31 +08:00
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/// ChangeToRegister - Replace this operand with a new register operand of
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/// the specified value. If an operand is known to be an register already,
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/// the setReg method should be used.
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void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
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2010-02-10 08:41:49 +08:00
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bool isKill, bool isDead, bool isUndef,
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bool isDebug) {
|
2014-04-14 08:51:57 +08:00
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MachineRegisterInfo *RegInfo = nullptr;
|
2012-08-10 08:21:26 +08:00
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if (MachineInstr *MI = getParent())
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if (MachineBasicBlock *MBB = MI->getParent())
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if (MachineFunction *MF = MBB->getParent())
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RegInfo = &MF->getRegInfo();
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// If this operand is already a register operand, remove it from the
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2008-01-01 09:12:31 +08:00
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// register's use/def lists.
|
2012-08-29 08:37:58 +08:00
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bool WasReg = isReg();
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if (RegInfo && WasReg)
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2012-08-10 08:21:26 +08:00
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RegInfo->removeRegOperandFromUseList(this);
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2008-01-01 09:12:31 +08:00
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2012-08-10 08:21:26 +08:00
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// Change this to a register and set the reg#.
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OpKind = MO_Register;
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SmallContents.RegNo = Reg;
|
2013-01-08 07:21:44 +08:00
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SubReg_TargetFlags = 0;
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2008-01-01 09:12:31 +08:00
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IsDef = isDef;
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IsImp = isImp;
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IsKill = isKill;
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IsDead = isDead;
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2009-06-30 16:49:04 +08:00
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IsUndef = isUndef;
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2011-12-07 08:22:07 +08:00
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IsInternalRead = false;
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2008-09-14 09:44:36 +08:00
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IsEarlyClobber = false;
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2010-02-10 08:41:49 +08:00
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IsDebug = isDebug;
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2012-08-10 08:21:26 +08:00
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// Ensure isOnRegUseList() returns false.
|
2014-04-14 08:51:57 +08:00
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Contents.Reg.Prev = nullptr;
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2012-09-05 02:36:28 +08:00
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// Preserve the tie when the operand was already a register.
|
2012-08-29 08:37:58 +08:00
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if (!WasReg)
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2012-09-05 02:36:28 +08:00
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TiedTo = 0;
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2012-08-10 08:21:26 +08:00
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// If this operand is embedded in a function, add the operand to the
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// register's use/def list.
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if (RegInfo)
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RegInfo->addRegOperandToUseList(this);
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2008-01-01 09:12:31 +08:00
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}
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|
2007-12-31 05:56:09 +08:00
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/// isIdenticalTo - Return true if this operand is identical to the specified
|
2012-07-05 19:06:22 +08:00
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/// operand. Note that this should stay in sync with the hash_value overload
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/// below.
|
2007-12-31 05:56:09 +08:00
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bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
|
2009-06-25 01:54:48 +08:00
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if (getType() != Other.getType() ||
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getTargetFlags() != Other.getTargetFlags())
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return false;
|
2011-08-25 00:44:17 +08:00
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|
2007-12-31 05:56:09 +08:00
|
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|
switch (getType()) {
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case MachineOperand::MO_Register:
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return getReg() == Other.getReg() && isDef() == Other.isDef() &&
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getSubReg() == Other.getSubReg();
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case MachineOperand::MO_Immediate:
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|
|
return getImm() == Other.getImm();
|
2011-07-02 07:45:21 +08:00
|
|
|
case MachineOperand::MO_CImmediate:
|
|
|
|
return getCImm() == Other.getCImm();
|
2008-02-14 15:39:30 +08:00
|
|
|
case MachineOperand::MO_FPImmediate:
|
|
|
|
return getFPImm() == Other.getFPImm();
|
2007-12-31 05:56:09 +08:00
|
|
|
case MachineOperand::MO_MachineBasicBlock:
|
|
|
|
return getMBB() == Other.getMBB();
|
|
|
|
case MachineOperand::MO_FrameIndex:
|
2007-12-31 07:10:15 +08:00
|
|
|
return getIndex() == Other.getIndex();
|
2007-12-31 05:56:09 +08:00
|
|
|
case MachineOperand::MO_ConstantPoolIndex:
|
2012-08-08 02:56:39 +08:00
|
|
|
case MachineOperand::MO_TargetIndex:
|
2007-12-31 07:10:15 +08:00
|
|
|
return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
|
2007-12-31 05:56:09 +08:00
|
|
|
case MachineOperand::MO_JumpTableIndex:
|
2007-12-31 07:10:15 +08:00
|
|
|
return getIndex() == Other.getIndex();
|
2007-12-31 05:56:09 +08:00
|
|
|
case MachineOperand::MO_GlobalAddress:
|
|
|
|
return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
|
|
|
|
case MachineOperand::MO_ExternalSymbol:
|
2017-05-31 09:10:10 +08:00
|
|
|
return strcmp(getSymbolName(), Other.getSymbolName()) == 0 &&
|
2007-12-31 05:56:09 +08:00
|
|
|
getOffset() == Other.getOffset();
|
2009-10-30 09:27:03 +08:00
|
|
|
case MachineOperand::MO_BlockAddress:
|
2012-09-13 05:43:09 +08:00
|
|
|
return getBlockAddress() == Other.getBlockAddress() &&
|
|
|
|
getOffset() == Other.getOffset();
|
2013-12-14 14:53:06 +08:00
|
|
|
case MachineOperand::MO_RegisterMask:
|
2017-03-14 17:09:26 +08:00
|
|
|
case MachineOperand::MO_RegisterLiveOut: {
|
|
|
|
// Shallow compare of the two RegMasks
|
|
|
|
const uint32_t *RegMask = getRegMask();
|
|
|
|
const uint32_t *OtherRegMask = Other.getRegMask();
|
|
|
|
if (RegMask == OtherRegMask)
|
|
|
|
return true;
|
|
|
|
|
|
|
|
// Calculate the size of the RegMask
|
2017-10-11 07:50:49 +08:00
|
|
|
const MachineFunction *MF = getParent()->getMF();
|
2017-03-14 17:09:26 +08:00
|
|
|
const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
|
|
|
|
unsigned RegMaskSize = (TRI->getNumRegs() + 31) / 32;
|
|
|
|
|
|
|
|
// Deep compare of the two RegMasks
|
|
|
|
return std::equal(RegMask, RegMask + RegMaskSize, OtherRegMask);
|
|
|
|
}
|
2010-03-13 16:14:18 +08:00
|
|
|
case MachineOperand::MO_MCSymbol:
|
|
|
|
return getMCSymbol() == Other.getMCSymbol();
|
2017-06-29 21:58:24 +08:00
|
|
|
case MachineOperand::MO_CFIIndex:
|
|
|
|
return getCFIIndex() == Other.getCFIIndex();
|
2010-04-08 02:03:19 +08:00
|
|
|
case MachineOperand::MO_Metadata:
|
|
|
|
return getMetadata() == Other.getMetadata();
|
2016-07-30 04:32:59 +08:00
|
|
|
case MachineOperand::MO_IntrinsicID:
|
|
|
|
return getIntrinsicID() == Other.getIntrinsicID();
|
2016-08-18 04:25:25 +08:00
|
|
|
case MachineOperand::MO_Predicate:
|
|
|
|
return getPredicate() == Other.getPredicate();
|
2007-12-31 05:56:09 +08:00
|
|
|
}
|
2012-01-11 02:08:01 +08:00
|
|
|
llvm_unreachable("Invalid machine operand type");
|
2007-12-31 05:56:09 +08:00
|
|
|
}
|
|
|
|
|
2012-07-05 19:06:22 +08:00
|
|
|
// Note: this must stay exactly in sync with isIdenticalTo above.
|
|
|
|
hash_code llvm::hash_value(const MachineOperand &MO) {
|
|
|
|
switch (MO.getType()) {
|
|
|
|
case MachineOperand::MO_Register:
|
2012-08-29 02:05:48 +08:00
|
|
|
// Register operands don't have target flags.
|
|
|
|
return hash_combine(MO.getType(), MO.getReg(), MO.getSubReg(), MO.isDef());
|
2012-07-05 19:06:22 +08:00
|
|
|
case MachineOperand::MO_Immediate:
|
|
|
|
return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getImm());
|
|
|
|
case MachineOperand::MO_CImmediate:
|
|
|
|
return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCImm());
|
|
|
|
case MachineOperand::MO_FPImmediate:
|
|
|
|
return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getFPImm());
|
|
|
|
case MachineOperand::MO_MachineBasicBlock:
|
|
|
|
return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMBB());
|
|
|
|
case MachineOperand::MO_FrameIndex:
|
|
|
|
return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
|
|
|
|
case MachineOperand::MO_ConstantPoolIndex:
|
2012-08-08 02:56:39 +08:00
|
|
|
case MachineOperand::MO_TargetIndex:
|
2012-07-05 19:06:22 +08:00
|
|
|
return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex(),
|
|
|
|
MO.getOffset());
|
|
|
|
case MachineOperand::MO_JumpTableIndex:
|
|
|
|
return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
|
|
|
|
case MachineOperand::MO_ExternalSymbol:
|
|
|
|
return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getOffset(),
|
|
|
|
MO.getSymbolName());
|
|
|
|
case MachineOperand::MO_GlobalAddress:
|
|
|
|
return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getGlobal(),
|
|
|
|
MO.getOffset());
|
|
|
|
case MachineOperand::MO_BlockAddress:
|
|
|
|
return hash_combine(MO.getType(), MO.getTargetFlags(),
|
2012-09-13 05:43:09 +08:00
|
|
|
MO.getBlockAddress(), MO.getOffset());
|
2012-07-05 19:06:22 +08:00
|
|
|
case MachineOperand::MO_RegisterMask:
|
2013-12-14 14:53:06 +08:00
|
|
|
case MachineOperand::MO_RegisterLiveOut:
|
2012-07-05 19:06:22 +08:00
|
|
|
return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getRegMask());
|
|
|
|
case MachineOperand::MO_Metadata:
|
|
|
|
return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMetadata());
|
|
|
|
case MachineOperand::MO_MCSymbol:
|
|
|
|
return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMCSymbol());
|
2017-06-29 21:58:24 +08:00
|
|
|
case MachineOperand::MO_CFIIndex:
|
|
|
|
return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCFIIndex());
|
2016-07-30 04:32:59 +08:00
|
|
|
case MachineOperand::MO_IntrinsicID:
|
|
|
|
return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIntrinsicID());
|
2016-08-18 04:25:25 +08:00
|
|
|
case MachineOperand::MO_Predicate:
|
|
|
|
return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getPredicate());
|
2012-07-05 19:06:22 +08:00
|
|
|
}
|
|
|
|
llvm_unreachable("Invalid machine operand type");
|
|
|
|
}
|
|
|
|
|
2016-07-30 04:32:59 +08:00
|
|
|
void MachineOperand::print(raw_ostream &OS, const TargetRegisterInfo *TRI,
|
|
|
|
const TargetIntrinsicInfo *IntrinsicInfo) const {
|
2015-06-27 06:06:47 +08:00
|
|
|
ModuleSlotTracker DummyMST(nullptr);
|
2016-07-30 04:32:59 +08:00
|
|
|
print(OS, DummyMST, TRI, IntrinsicInfo);
|
2015-06-27 06:06:47 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
void MachineOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
|
2016-07-30 04:32:59 +08:00
|
|
|
const TargetRegisterInfo *TRI,
|
|
|
|
const TargetIntrinsicInfo *IntrinsicInfo) const {
|
2007-12-31 05:56:09 +08:00
|
|
|
switch (getType()) {
|
|
|
|
case MachineOperand::MO_Register:
|
2011-01-09 11:05:53 +08:00
|
|
|
OS << PrintReg(getReg(), TRI, getSubReg());
|
2008-12-19 05:51:27 +08:00
|
|
|
|
2009-06-30 16:49:04 +08:00
|
|
|
if (isDef() || isKill() || isDead() || isImplicit() || isUndef() ||
|
Add a MachineOperand::isTied() flag.
While in SSA form, a MachineInstr can have pairs of tied defs and uses.
The tied operands are used to represent read-modify-write operands that
must be assigned the same physical register.
Previously, tied operand pairs were computed from fixed MCInstrDesc
fields, or by using black magic on inline assembly instructions.
The isTied flag makes it possible to add tied operands to any
instruction while getting rid of (some of) the inlineasm magic.
Tied operands on normal instructions are needed to represent predicated
individual instructions in SSA form. An extra <tied,imp-use> operand is
required to represent the output value when the instruction predicate is
false.
Adding a predicate to:
%vreg0<def> = ADD %vreg1, %vreg2
Will look like:
%vreg0<tied,def> = ADD %vreg1, %vreg2, pred:3, %vreg7<tied,imp-use>
The virtual register %vreg7 is the value given to %vreg0 when the
predicate is false. It will be assigned the same physreg as %vreg0.
This commit adds the isTied flag and sets it based on MCInstrDesc when
building an instruction. The flag is not used for anything yet.
llvm-svn: 162774
2012-08-29 02:34:41 +08:00
|
|
|
isInternalRead() || isEarlyClobber() || isTied()) {
|
2009-06-25 01:54:48 +08:00
|
|
|
OS << '<';
|
2007-12-31 05:56:09 +08:00
|
|
|
bool NeedComma = false;
|
2009-10-15 07:37:31 +08:00
|
|
|
if (isDef()) {
|
2009-06-25 01:54:48 +08:00
|
|
|
if (NeedComma) OS << ',';
|
2008-09-13 01:49:03 +08:00
|
|
|
if (isEarlyClobber())
|
|
|
|
OS << "earlyclobber,";
|
2009-10-15 07:37:31 +08:00
|
|
|
if (isImplicit())
|
|
|
|
OS << "imp-";
|
2007-12-31 05:56:09 +08:00
|
|
|
OS << "def";
|
|
|
|
NeedComma = true;
|
2012-04-21 05:45:33 +08:00
|
|
|
// <def,read-undef> only makes sense when getSubReg() is set.
|
|
|
|
// Don't clutter the output otherwise.
|
|
|
|
if (isUndef() && getSubReg())
|
|
|
|
OS << ",read-undef";
|
2009-10-21 15:56:02 +08:00
|
|
|
} else if (isImplicit()) {
|
2015-05-16 13:42:08 +08:00
|
|
|
OS << "imp-use";
|
|
|
|
NeedComma = true;
|
2009-10-21 15:56:02 +08:00
|
|
|
}
|
2009-10-15 07:37:31 +08:00
|
|
|
|
Add a MachineOperand::isTied() flag.
While in SSA form, a MachineInstr can have pairs of tied defs and uses.
The tied operands are used to represent read-modify-write operands that
must be assigned the same physical register.
Previously, tied operand pairs were computed from fixed MCInstrDesc
fields, or by using black magic on inline assembly instructions.
The isTied flag makes it possible to add tied operands to any
instruction while getting rid of (some of) the inlineasm magic.
Tied operands on normal instructions are needed to represent predicated
individual instructions in SSA form. An extra <tied,imp-use> operand is
required to represent the output value when the instruction predicate is
false.
Adding a predicate to:
%vreg0<def> = ADD %vreg1, %vreg2
Will look like:
%vreg0<tied,def> = ADD %vreg1, %vreg2, pred:3, %vreg7<tied,imp-use>
The virtual register %vreg7 is the value given to %vreg0 when the
predicate is false. It will be assigned the same physreg as %vreg0.
This commit adds the isTied flag and sets it based on MCInstrDesc when
building an instruction. The flag is not used for anything yet.
llvm-svn: 162774
2012-08-29 02:34:41 +08:00
|
|
|
if (isKill()) {
|
2009-06-25 01:54:48 +08:00
|
|
|
if (NeedComma) OS << ',';
|
Add a MachineOperand::isTied() flag.
While in SSA form, a MachineInstr can have pairs of tied defs and uses.
The tied operands are used to represent read-modify-write operands that
must be assigned the same physical register.
Previously, tied operand pairs were computed from fixed MCInstrDesc
fields, or by using black magic on inline assembly instructions.
The isTied flag makes it possible to add tied operands to any
instruction while getting rid of (some of) the inlineasm magic.
Tied operands on normal instructions are needed to represent predicated
individual instructions in SSA form. An extra <tied,imp-use> operand is
required to represent the output value when the instruction predicate is
false.
Adding a predicate to:
%vreg0<def> = ADD %vreg1, %vreg2
Will look like:
%vreg0<tied,def> = ADD %vreg1, %vreg2, pred:3, %vreg7<tied,imp-use>
The virtual register %vreg7 is the value given to %vreg0 when the
predicate is false. It will be assigned the same physreg as %vreg0.
This commit adds the isTied flag and sets it based on MCInstrDesc when
building an instruction. The flag is not used for anything yet.
llvm-svn: 162774
2012-08-29 02:34:41 +08:00
|
|
|
OS << "kill";
|
|
|
|
NeedComma = true;
|
|
|
|
}
|
|
|
|
if (isDead()) {
|
|
|
|
if (NeedComma) OS << ',';
|
|
|
|
OS << "dead";
|
|
|
|
NeedComma = true;
|
|
|
|
}
|
|
|
|
if (isUndef() && isUse()) {
|
|
|
|
if (NeedComma) OS << ',';
|
|
|
|
OS << "undef";
|
|
|
|
NeedComma = true;
|
|
|
|
}
|
|
|
|
if (isInternalRead()) {
|
|
|
|
if (NeedComma) OS << ',';
|
|
|
|
OS << "internal";
|
|
|
|
NeedComma = true;
|
|
|
|
}
|
|
|
|
if (isTied()) {
|
|
|
|
if (NeedComma) OS << ',';
|
|
|
|
OS << "tied";
|
2012-09-05 02:36:28 +08:00
|
|
|
if (TiedTo != 15)
|
|
|
|
OS << unsigned(TiedTo - 1);
|
2007-12-31 05:56:09 +08:00
|
|
|
}
|
2009-06-25 01:54:48 +08:00
|
|
|
OS << '>';
|
2007-12-31 05:56:09 +08:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
case MachineOperand::MO_Immediate:
|
|
|
|
OS << getImm();
|
|
|
|
break;
|
2011-06-25 04:46:11 +08:00
|
|
|
case MachineOperand::MO_CImmediate:
|
|
|
|
getCImm()->getValue().print(OS, false);
|
|
|
|
break;
|
2008-02-14 15:39:30 +08:00
|
|
|
case MachineOperand::MO_FPImmediate:
|
2016-02-05 08:50:18 +08:00
|
|
|
if (getFPImm()->getType()->isFloatTy()) {
|
2008-02-14 15:39:30 +08:00
|
|
|
OS << getFPImm()->getValueAPF().convertToFloat();
|
2016-02-05 08:50:18 +08:00
|
|
|
} else if (getFPImm()->getType()->isHalfTy()) {
|
|
|
|
APFloat APF = getFPImm()->getValueAPF();
|
|
|
|
bool Unused;
|
2016-12-14 19:57:17 +08:00
|
|
|
APF.convert(APFloat::IEEEsingle(), APFloat::rmNearestTiesToEven, &Unused);
|
2016-02-05 08:50:18 +08:00
|
|
|
OS << "half " << APF.convertToFloat();
|
2017-03-21 00:52:08 +08:00
|
|
|
} else if (getFPImm()->getType()->isFP128Ty()) {
|
|
|
|
APFloat APF = getFPImm()->getValueAPF();
|
|
|
|
SmallString<16> Str;
|
|
|
|
getFPImm()->getValueAPF().toString(Str);
|
|
|
|
OS << "quad " << Str;
|
2017-07-05 19:11:10 +08:00
|
|
|
} else if (getFPImm()->getType()->isX86_FP80Ty()) {
|
|
|
|
APFloat APF = getFPImm()->getValueAPF();
|
|
|
|
OS << "x86_fp80 0xK";
|
|
|
|
APInt API = APF.bitcastToAPInt();
|
|
|
|
OS << format_hex_no_prefix(API.getHiBits(16).getZExtValue(), 4,
|
|
|
|
/*Upper=*/true);
|
|
|
|
OS << format_hex_no_prefix(API.getLoBits(64).getZExtValue(), 16,
|
|
|
|
/*Upper=*/true);
|
2016-02-05 08:50:18 +08:00
|
|
|
} else {
|
2008-02-14 15:39:30 +08:00
|
|
|
OS << getFPImm()->getValueAPF().convertToDouble();
|
2016-02-05 08:50:18 +08:00
|
|
|
}
|
2008-02-14 15:39:30 +08:00
|
|
|
break;
|
2007-12-31 05:56:09 +08:00
|
|
|
case MachineOperand::MO_MachineBasicBlock:
|
2009-11-01 04:19:03 +08:00
|
|
|
OS << "<BB#" << getMBB()->getNumber() << ">";
|
2007-12-31 05:56:09 +08:00
|
|
|
break;
|
|
|
|
case MachineOperand::MO_FrameIndex:
|
2009-06-25 01:54:48 +08:00
|
|
|
OS << "<fi#" << getIndex() << '>';
|
2007-12-31 05:56:09 +08:00
|
|
|
break;
|
|
|
|
case MachineOperand::MO_ConstantPoolIndex:
|
2007-12-31 07:10:15 +08:00
|
|
|
OS << "<cp#" << getIndex();
|
2007-12-31 05:56:09 +08:00
|
|
|
if (getOffset()) OS << "+" << getOffset();
|
2009-06-25 01:54:48 +08:00
|
|
|
OS << '>';
|
2007-12-31 05:56:09 +08:00
|
|
|
break;
|
2012-08-08 02:56:39 +08:00
|
|
|
case MachineOperand::MO_TargetIndex:
|
|
|
|
OS << "<ti#" << getIndex();
|
|
|
|
if (getOffset()) OS << "+" << getOffset();
|
|
|
|
OS << '>';
|
|
|
|
break;
|
2007-12-31 05:56:09 +08:00
|
|
|
case MachineOperand::MO_JumpTableIndex:
|
2009-06-25 01:54:48 +08:00
|
|
|
OS << "<jt#" << getIndex() << '>';
|
2007-12-31 05:56:09 +08:00
|
|
|
break;
|
|
|
|
case MachineOperand::MO_GlobalAddress:
|
2009-11-07 02:03:10 +08:00
|
|
|
OS << "<ga:";
|
2015-06-27 06:06:47 +08:00
|
|
|
getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST);
|
2007-12-31 05:56:09 +08:00
|
|
|
if (getOffset()) OS << "+" << getOffset();
|
2009-06-25 01:54:48 +08:00
|
|
|
OS << '>';
|
2007-12-31 05:56:09 +08:00
|
|
|
break;
|
|
|
|
case MachineOperand::MO_ExternalSymbol:
|
|
|
|
OS << "<es:" << getSymbolName();
|
|
|
|
if (getOffset()) OS << "+" << getOffset();
|
2009-06-25 01:54:48 +08:00
|
|
|
OS << '>';
|
2007-12-31 05:56:09 +08:00
|
|
|
break;
|
2009-10-30 09:27:03 +08:00
|
|
|
case MachineOperand::MO_BlockAddress:
|
2010-01-13 08:00:24 +08:00
|
|
|
OS << '<';
|
2015-06-27 06:06:47 +08:00
|
|
|
getBlockAddress()->printAsOperand(OS, /*PrintType=*/false, MST);
|
2012-09-13 05:43:09 +08:00
|
|
|
if (getOffset()) OS << "+" << getOffset();
|
2009-10-30 09:27:03 +08:00
|
|
|
OS << '>';
|
|
|
|
break;
|
2015-08-19 20:03:04 +08:00
|
|
|
case MachineOperand::MO_RegisterMask: {
|
|
|
|
unsigned NumRegsInMask = 0;
|
|
|
|
unsigned NumRegsEmitted = 0;
|
|
|
|
OS << "<regmask";
|
|
|
|
for (unsigned i = 0; i < TRI->getNumRegs(); ++i) {
|
|
|
|
unsigned MaskWord = i / 32;
|
|
|
|
unsigned MaskBit = i % 32;
|
|
|
|
if (getRegMask()[MaskWord] & (1 << MaskBit)) {
|
2017-07-20 08:37:31 +08:00
|
|
|
if (PrintRegMaskNumRegs < 0 ||
|
|
|
|
NumRegsEmitted <= static_cast<unsigned>(PrintRegMaskNumRegs)) {
|
2015-08-19 20:03:04 +08:00
|
|
|
OS << " " << PrintReg(i, TRI);
|
|
|
|
NumRegsEmitted++;
|
|
|
|
}
|
|
|
|
NumRegsInMask++;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (NumRegsEmitted != NumRegsInMask)
|
|
|
|
OS << " and " << (NumRegsInMask - NumRegsEmitted) << " more...";
|
|
|
|
OS << ">";
|
2012-01-17 03:22:00 +08:00
|
|
|
break;
|
2015-08-19 20:03:04 +08:00
|
|
|
}
|
2013-12-14 14:53:06 +08:00
|
|
|
case MachineOperand::MO_RegisterLiveOut:
|
|
|
|
OS << "<regliveout>";
|
|
|
|
break;
|
2010-01-13 08:00:24 +08:00
|
|
|
case MachineOperand::MO_Metadata:
|
|
|
|
OS << '<';
|
2015-06-27 06:28:47 +08:00
|
|
|
getMetadata()->printAsOperand(OS, MST);
|
2010-01-13 08:00:24 +08:00
|
|
|
OS << '>';
|
|
|
|
break;
|
2010-03-13 16:14:18 +08:00
|
|
|
case MachineOperand::MO_MCSymbol:
|
|
|
|
OS << "<MCSym=" << *getMCSymbol() << '>';
|
|
|
|
break;
|
2014-03-07 14:08:31 +08:00
|
|
|
case MachineOperand::MO_CFIIndex:
|
|
|
|
OS << "<call frame instruction>";
|
|
|
|
break;
|
2016-07-30 04:32:59 +08:00
|
|
|
case MachineOperand::MO_IntrinsicID: {
|
|
|
|
Intrinsic::ID ID = getIntrinsicID();
|
|
|
|
if (ID < Intrinsic::num_intrinsics)
|
2016-09-13 00:21:49 +08:00
|
|
|
OS << "<intrinsic:@" << Intrinsic::getName(ID, None) << '>';
|
2016-07-30 04:32:59 +08:00
|
|
|
else if (IntrinsicInfo)
|
2016-09-13 00:21:49 +08:00
|
|
|
OS << "<intrinsic:@" << IntrinsicInfo->getName(ID) << '>';
|
2016-07-30 04:32:59 +08:00
|
|
|
else
|
|
|
|
OS << "<intrinsic:" << ID << '>';
|
|
|
|
break;
|
|
|
|
}
|
2016-08-18 04:25:25 +08:00
|
|
|
case MachineOperand::MO_Predicate: {
|
|
|
|
auto Pred = static_cast<CmpInst::Predicate>(getPredicate());
|
|
|
|
OS << '<' << (CmpInst::isIntPredicate(Pred) ? "intpred" : "floatpred")
|
|
|
|
<< CmpInst::getPredicateName(Pred) << '>';
|
2017-03-15 05:32:08 +08:00
|
|
|
break;
|
2016-08-18 04:25:25 +08:00
|
|
|
}
|
2007-12-31 05:56:09 +08:00
|
|
|
}
|
2009-06-25 01:54:48 +08:00
|
|
|
if (unsigned TF = getTargetFlags())
|
|
|
|
OS << "[TF=" << TF << ']';
|
2007-12-31 05:56:09 +08:00
|
|
|
}
|
|
|
|
|
2017-10-13 00:16:06 +08:00
|
|
|
#ifdef LLVM_ENABLE_DUMP
|
2016-11-18 10:40:40 +08:00
|
|
|
LLVM_DUMP_METHOD void MachineOperand::dump() const {
|
|
|
|
dbgs() << *this << '\n';
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2008-07-08 04:32:02 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// MachineMemOperand Implementation
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
2010-09-21 13:39:30 +08:00
|
|
|
/// getAddrSpace - Return the LLVM IR address space number that this pointer
|
|
|
|
/// points into.
|
|
|
|
unsigned MachinePointerInfo::getAddrSpace() const {
|
2017-09-15 04:53:51 +08:00
|
|
|
if (V.isNull()) return 0;
|
|
|
|
|
|
|
|
if (V.is<const PseudoSourceValue*>())
|
|
|
|
return V.get<const PseudoSourceValue*>()->getAddressSpace();
|
|
|
|
|
2014-04-15 15:22:52 +08:00
|
|
|
return cast<PointerType>(V.get<const Value*>()->getType())->getAddressSpace();
|
2010-09-21 13:39:30 +08:00
|
|
|
}
|
|
|
|
|
2017-06-24 23:17:38 +08:00
|
|
|
/// isDereferenceable - Return true if V is always dereferenceable for
|
|
|
|
/// Offset + Size byte.
|
|
|
|
bool MachinePointerInfo::isDereferenceable(unsigned Size, LLVMContext &C,
|
|
|
|
const DataLayout &DL) const {
|
|
|
|
if (!V.is<const Value*>())
|
|
|
|
return false;
|
|
|
|
|
|
|
|
const Value *BasePtr = V.get<const Value*>();
|
|
|
|
if (BasePtr == nullptr)
|
|
|
|
return false;
|
|
|
|
|
2017-08-03 17:38:46 +08:00
|
|
|
return isDereferenceableAndAlignedPointer(
|
|
|
|
BasePtr, 1, APInt(DL.getPointerSizeInBits(), Offset + Size), DL);
|
2017-06-24 23:17:38 +08:00
|
|
|
}
|
|
|
|
|
2010-09-21 14:22:23 +08:00
|
|
|
/// getConstantPool - Return a MachinePointerInfo record that refers to the
|
|
|
|
/// constant pool.
|
2015-08-12 07:09:45 +08:00
|
|
|
MachinePointerInfo MachinePointerInfo::getConstantPool(MachineFunction &MF) {
|
|
|
|
return MachinePointerInfo(MF.getPSVManager().getConstantPool());
|
2010-09-21 14:22:23 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/// getFixedStack - Return a MachinePointerInfo record that refers to the
|
|
|
|
/// the specified FrameIndex.
|
2015-08-12 07:09:45 +08:00
|
|
|
MachinePointerInfo MachinePointerInfo::getFixedStack(MachineFunction &MF,
|
|
|
|
int FI, int64_t Offset) {
|
|
|
|
return MachinePointerInfo(MF.getPSVManager().getFixedStack(FI), Offset);
|
2010-09-21 14:22:23 +08:00
|
|
|
}
|
|
|
|
|
2015-08-12 07:09:45 +08:00
|
|
|
MachinePointerInfo MachinePointerInfo::getJumpTable(MachineFunction &MF) {
|
|
|
|
return MachinePointerInfo(MF.getPSVManager().getJumpTable());
|
2010-09-21 14:43:24 +08:00
|
|
|
}
|
|
|
|
|
2015-08-12 07:09:45 +08:00
|
|
|
MachinePointerInfo MachinePointerInfo::getGOT(MachineFunction &MF) {
|
|
|
|
return MachinePointerInfo(MF.getPSVManager().getGOT());
|
2010-09-21 14:43:24 +08:00
|
|
|
}
|
2010-09-21 13:39:30 +08:00
|
|
|
|
2015-08-12 07:09:45 +08:00
|
|
|
MachinePointerInfo MachinePointerInfo::getStack(MachineFunction &MF,
|
2017-07-21 05:03:45 +08:00
|
|
|
int64_t Offset,
|
|
|
|
uint8_t ID) {
|
|
|
|
return MachinePointerInfo(MF.getPSVManager().getStack(), Offset,ID);
|
2010-09-22 02:51:21 +08:00
|
|
|
}
|
|
|
|
|
2016-07-15 01:07:44 +08:00
|
|
|
MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, Flags f,
|
2010-10-20 08:31:05 +08:00
|
|
|
uint64_t s, unsigned int a,
|
2014-07-24 20:16:19 +08:00
|
|
|
const AAMDNodes &AAInfo,
|
2016-10-16 06:01:18 +08:00
|
|
|
const MDNode *Ranges,
|
2017-07-12 06:23:00 +08:00
|
|
|
SyncScope::ID SSID,
|
2016-10-16 06:01:18 +08:00
|
|
|
AtomicOrdering Ordering,
|
|
|
|
AtomicOrdering FailureOrdering)
|
2016-07-15 01:07:44 +08:00
|
|
|
: PtrInfo(ptrinfo), Size(s), FlagVals(f), BaseAlignLog2(Log2_32(a) + 1),
|
|
|
|
AAInfo(AAInfo), Ranges(Ranges) {
|
2014-04-15 15:22:52 +08:00
|
|
|
assert((PtrInfo.V.isNull() || PtrInfo.V.is<const PseudoSourceValue*>() ||
|
|
|
|
isa<PointerType>(PtrInfo.V.get<const Value*>()->getType())) &&
|
2010-09-21 12:32:08 +08:00
|
|
|
"invalid pointer value");
|
2009-09-22 03:47:04 +08:00
|
|
|
assert(getBaseAlignment() == a && "Alignment is not a power of 2!");
|
2008-07-16 23:56:42 +08:00
|
|
|
assert((isLoad() || isStore()) && "Not a load/store!");
|
2016-10-16 06:01:18 +08:00
|
|
|
|
2017-07-12 06:23:00 +08:00
|
|
|
AtomicInfo.SSID = static_cast<unsigned>(SSID);
|
|
|
|
assert(getSyncScopeID() == SSID && "Value truncated");
|
2016-10-16 06:01:18 +08:00
|
|
|
AtomicInfo.Ordering = static_cast<unsigned>(Ordering);
|
|
|
|
assert(getOrdering() == Ordering && "Value truncated");
|
|
|
|
AtomicInfo.FailureOrdering = static_cast<unsigned>(FailureOrdering);
|
|
|
|
assert(getFailureOrdering() == FailureOrdering && "Value truncated");
|
2008-07-08 04:32:02 +08:00
|
|
|
}
|
|
|
|
|
2008-08-20 23:58:01 +08:00
|
|
|
/// Profile - Gather unique data for the object.
|
|
|
|
///
|
|
|
|
void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
|
2010-09-21 12:23:39 +08:00
|
|
|
ID.AddInteger(getOffset());
|
2008-08-20 23:58:01 +08:00
|
|
|
ID.AddInteger(Size);
|
2014-04-15 15:22:52 +08:00
|
|
|
ID.AddPointer(getOpaqueValue());
|
2016-07-15 01:07:44 +08:00
|
|
|
ID.AddInteger(getFlags());
|
|
|
|
ID.AddInteger(getBaseAlignment());
|
2008-08-20 23:58:01 +08:00
|
|
|
}
|
|
|
|
|
2009-09-26 04:36:54 +08:00
|
|
|
void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) {
|
|
|
|
// The Value and Offset may differ due to CSE. But the flags and size
|
|
|
|
// should be the same.
|
|
|
|
assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
|
|
|
|
assert(MMO->getSize() == getSize() && "Size mismatch!");
|
|
|
|
|
|
|
|
if (MMO->getBaseAlignment() >= getBaseAlignment()) {
|
|
|
|
// Update the alignment value.
|
2016-07-15 01:07:44 +08:00
|
|
|
BaseAlignLog2 = Log2_32(MMO->getBaseAlignment()) + 1;
|
2009-09-26 04:36:54 +08:00
|
|
|
// Also update the base and offset, because the new alignment may
|
|
|
|
// not be applicable with the old ones.
|
2010-09-21 12:23:39 +08:00
|
|
|
PtrInfo = MMO->PtrInfo;
|
2009-09-26 04:36:54 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2009-09-26 07:33:20 +08:00
|
|
|
/// getAlignment - Return the minimum known alignment in bytes of the
|
|
|
|
/// actual memory reference.
|
|
|
|
uint64_t MachineMemOperand::getAlignment() const {
|
|
|
|
return MinAlign(getBaseAlignment(), getOffset());
|
|
|
|
}
|
|
|
|
|
2015-06-27 06:06:47 +08:00
|
|
|
void MachineMemOperand::print(raw_ostream &OS) const {
|
|
|
|
ModuleSlotTracker DummyMST(nullptr);
|
|
|
|
print(OS, DummyMST);
|
|
|
|
}
|
|
|
|
void MachineMemOperand::print(raw_ostream &OS, ModuleSlotTracker &MST) const {
|
|
|
|
assert((isLoad() || isStore()) &&
|
2009-09-23 09:33:16 +08:00
|
|
|
"SV has to be a load, store or both.");
|
2011-08-25 00:44:17 +08:00
|
|
|
|
2015-06-27 06:06:47 +08:00
|
|
|
if (isVolatile())
|
2009-09-23 09:33:16 +08:00
|
|
|
OS << "Volatile ";
|
|
|
|
|
2015-06-27 06:06:47 +08:00
|
|
|
if (isLoad())
|
2009-09-23 09:33:16 +08:00
|
|
|
OS << "LD";
|
2015-06-27 06:06:47 +08:00
|
|
|
if (isStore())
|
2009-09-23 09:33:16 +08:00
|
|
|
OS << "ST";
|
2015-06-27 06:06:47 +08:00
|
|
|
OS << getSize();
|
2011-08-25 00:44:17 +08:00
|
|
|
|
2009-09-23 09:33:16 +08:00
|
|
|
// Print the address information.
|
|
|
|
OS << "[";
|
2015-06-27 06:06:47 +08:00
|
|
|
if (const Value *V = getValue())
|
|
|
|
V->printAsOperand(OS, /*PrintType=*/false, MST);
|
|
|
|
else if (const PseudoSourceValue *PSV = getPseudoValue())
|
2014-04-15 15:22:52 +08:00
|
|
|
PSV->printCustom(OS);
|
2009-09-23 09:33:16 +08:00
|
|
|
else
|
2014-04-15 15:22:52 +08:00
|
|
|
OS << "<unknown>";
|
2009-09-23 09:33:16 +08:00
|
|
|
|
2015-06-27 06:06:47 +08:00
|
|
|
unsigned AS = getAddrSpace();
|
2013-12-14 08:24:02 +08:00
|
|
|
if (AS != 0)
|
|
|
|
OS << "(addrspace=" << AS << ')';
|
|
|
|
|
2009-09-23 09:33:16 +08:00
|
|
|
// If the alignment of the memory reference itself differs from the alignment
|
|
|
|
// of the base pointer, print the base alignment explicitly, next to the base
|
|
|
|
// pointer.
|
2015-06-27 06:06:47 +08:00
|
|
|
if (getBaseAlignment() != getAlignment())
|
|
|
|
OS << "(align=" << getBaseAlignment() << ")";
|
2009-09-23 09:33:16 +08:00
|
|
|
|
2015-06-27 06:06:47 +08:00
|
|
|
if (getOffset() != 0)
|
|
|
|
OS << "+" << getOffset();
|
2009-09-23 09:33:16 +08:00
|
|
|
OS << "]";
|
|
|
|
|
|
|
|
// Print the alignment of the reference.
|
2015-06-27 06:06:47 +08:00
|
|
|
if (getBaseAlignment() != getAlignment() || getBaseAlignment() != getSize())
|
|
|
|
OS << "(align=" << getAlignment() << ")";
|
2009-09-23 09:33:16 +08:00
|
|
|
|
2010-10-20 08:31:05 +08:00
|
|
|
// Print TBAA info.
|
2015-06-27 06:06:47 +08:00
|
|
|
if (const MDNode *TBAAInfo = getAAInfo().TBAA) {
|
2010-10-20 08:31:05 +08:00
|
|
|
OS << "(tbaa=";
|
|
|
|
if (TBAAInfo->getNumOperands() > 0)
|
2015-06-27 06:28:47 +08:00
|
|
|
TBAAInfo->getOperand(0)->printAsOperand(OS, MST);
|
2010-10-20 08:31:05 +08:00
|
|
|
else
|
|
|
|
OS << "<unknown>";
|
|
|
|
OS << ")";
|
|
|
|
}
|
|
|
|
|
Add scoped-noalias metadata
This commit adds scoped noalias metadata. The primary motivations for this
feature are:
1. To preserve noalias function attribute information when inlining
2. To provide the ability to model block-scope C99 restrict pointers
Neither of these two abilities are added here, only the necessary
infrastructure. In fact, there should be no change to existing functionality,
only the addition of new features. The logic that converts noalias function
parameters into this metadata during inlining will come in a follow-up commit.
What is added here is the ability to generally specify noalias memory-access
sets. Regarding the metadata, alias-analysis scopes are defined similar to TBAA
nodes:
!scope0 = metadata !{ metadata !"scope of foo()" }
!scope1 = metadata !{ metadata !"scope 1", metadata !scope0 }
!scope2 = metadata !{ metadata !"scope 2", metadata !scope0 }
!scope3 = metadata !{ metadata !"scope 2.1", metadata !scope2 }
!scope4 = metadata !{ metadata !"scope 2.2", metadata !scope2 }
Loads and stores can be tagged with an alias-analysis scope, and also, with a
noalias tag for a specific scope:
... = load %ptr1, !alias.scope !{ !scope1 }
... = load %ptr2, !alias.scope !{ !scope1, !scope2 }, !noalias !{ !scope1 }
When evaluating an aliasing query, if one of the instructions is associated
with an alias.scope id that is identical to the noalias scope associated with
the other instruction, or is a descendant (in the scope hierarchy) of the
noalias scope associated with the other instruction, then the two memory
accesses are assumed not to alias.
Note that is the first element of the scope metadata is a string, then it can
be combined accross functions and translation units. The string can be replaced
by a self-reference to create globally unqiue scope identifiers.
[Note: This overview is slightly stylized, since the metadata nodes really need
to just be numbers (!0 instead of !scope0), and the scope lists are also global
unnamed metadata.]
Existing noalias metadata in a callee is "cloned" for use by the inlined code.
This is necessary because the aliasing scopes are unique to each call site
(because of possible control dependencies on the aliasing properties). For
example, consider a function: foo(noalias a, noalias b) { *a = *b; } that gets
inlined into bar() { ... if (...) foo(a1, b1); ... if (...) foo(a2, b2); } --
now just because we know that a1 does not alias with b1 at the first call site,
and a2 does not alias with b2 at the second call site, we cannot let inlining
these functons have the metadata imply that a1 does not alias with b2.
llvm-svn: 213864
2014-07-24 22:25:39 +08:00
|
|
|
// Print AA scope info.
|
2015-06-27 06:06:47 +08:00
|
|
|
if (const MDNode *ScopeInfo = getAAInfo().Scope) {
|
Add scoped-noalias metadata
This commit adds scoped noalias metadata. The primary motivations for this
feature are:
1. To preserve noalias function attribute information when inlining
2. To provide the ability to model block-scope C99 restrict pointers
Neither of these two abilities are added here, only the necessary
infrastructure. In fact, there should be no change to existing functionality,
only the addition of new features. The logic that converts noalias function
parameters into this metadata during inlining will come in a follow-up commit.
What is added here is the ability to generally specify noalias memory-access
sets. Regarding the metadata, alias-analysis scopes are defined similar to TBAA
nodes:
!scope0 = metadata !{ metadata !"scope of foo()" }
!scope1 = metadata !{ metadata !"scope 1", metadata !scope0 }
!scope2 = metadata !{ metadata !"scope 2", metadata !scope0 }
!scope3 = metadata !{ metadata !"scope 2.1", metadata !scope2 }
!scope4 = metadata !{ metadata !"scope 2.2", metadata !scope2 }
Loads and stores can be tagged with an alias-analysis scope, and also, with a
noalias tag for a specific scope:
... = load %ptr1, !alias.scope !{ !scope1 }
... = load %ptr2, !alias.scope !{ !scope1, !scope2 }, !noalias !{ !scope1 }
When evaluating an aliasing query, if one of the instructions is associated
with an alias.scope id that is identical to the noalias scope associated with
the other instruction, or is a descendant (in the scope hierarchy) of the
noalias scope associated with the other instruction, then the two memory
accesses are assumed not to alias.
Note that is the first element of the scope metadata is a string, then it can
be combined accross functions and translation units. The string can be replaced
by a self-reference to create globally unqiue scope identifiers.
[Note: This overview is slightly stylized, since the metadata nodes really need
to just be numbers (!0 instead of !scope0), and the scope lists are also global
unnamed metadata.]
Existing noalias metadata in a callee is "cloned" for use by the inlined code.
This is necessary because the aliasing scopes are unique to each call site
(because of possible control dependencies on the aliasing properties). For
example, consider a function: foo(noalias a, noalias b) { *a = *b; } that gets
inlined into bar() { ... if (...) foo(a1, b1); ... if (...) foo(a2, b2); } --
now just because we know that a1 does not alias with b1 at the first call site,
and a2 does not alias with b2 at the second call site, we cannot let inlining
these functons have the metadata imply that a1 does not alias with b2.
llvm-svn: 213864
2014-07-24 22:25:39 +08:00
|
|
|
OS << "(alias.scope=";
|
|
|
|
if (ScopeInfo->getNumOperands() > 0)
|
|
|
|
for (unsigned i = 0, ie = ScopeInfo->getNumOperands(); i != ie; ++i) {
|
2015-06-27 06:28:47 +08:00
|
|
|
ScopeInfo->getOperand(i)->printAsOperand(OS, MST);
|
Add scoped-noalias metadata
This commit adds scoped noalias metadata. The primary motivations for this
feature are:
1. To preserve noalias function attribute information when inlining
2. To provide the ability to model block-scope C99 restrict pointers
Neither of these two abilities are added here, only the necessary
infrastructure. In fact, there should be no change to existing functionality,
only the addition of new features. The logic that converts noalias function
parameters into this metadata during inlining will come in a follow-up commit.
What is added here is the ability to generally specify noalias memory-access
sets. Regarding the metadata, alias-analysis scopes are defined similar to TBAA
nodes:
!scope0 = metadata !{ metadata !"scope of foo()" }
!scope1 = metadata !{ metadata !"scope 1", metadata !scope0 }
!scope2 = metadata !{ metadata !"scope 2", metadata !scope0 }
!scope3 = metadata !{ metadata !"scope 2.1", metadata !scope2 }
!scope4 = metadata !{ metadata !"scope 2.2", metadata !scope2 }
Loads and stores can be tagged with an alias-analysis scope, and also, with a
noalias tag for a specific scope:
... = load %ptr1, !alias.scope !{ !scope1 }
... = load %ptr2, !alias.scope !{ !scope1, !scope2 }, !noalias !{ !scope1 }
When evaluating an aliasing query, if one of the instructions is associated
with an alias.scope id that is identical to the noalias scope associated with
the other instruction, or is a descendant (in the scope hierarchy) of the
noalias scope associated with the other instruction, then the two memory
accesses are assumed not to alias.
Note that is the first element of the scope metadata is a string, then it can
be combined accross functions and translation units. The string can be replaced
by a self-reference to create globally unqiue scope identifiers.
[Note: This overview is slightly stylized, since the metadata nodes really need
to just be numbers (!0 instead of !scope0), and the scope lists are also global
unnamed metadata.]
Existing noalias metadata in a callee is "cloned" for use by the inlined code.
This is necessary because the aliasing scopes are unique to each call site
(because of possible control dependencies on the aliasing properties). For
example, consider a function: foo(noalias a, noalias b) { *a = *b; } that gets
inlined into bar() { ... if (...) foo(a1, b1); ... if (...) foo(a2, b2); } --
now just because we know that a1 does not alias with b1 at the first call site,
and a2 does not alias with b2 at the second call site, we cannot let inlining
these functons have the metadata imply that a1 does not alias with b2.
llvm-svn: 213864
2014-07-24 22:25:39 +08:00
|
|
|
if (i != ie-1)
|
|
|
|
OS << ",";
|
|
|
|
}
|
|
|
|
else
|
|
|
|
OS << "<unknown>";
|
|
|
|
OS << ")";
|
|
|
|
}
|
|
|
|
|
|
|
|
// Print AA noalias scope info.
|
2015-06-27 06:06:47 +08:00
|
|
|
if (const MDNode *NoAliasInfo = getAAInfo().NoAlias) {
|
Add scoped-noalias metadata
This commit adds scoped noalias metadata. The primary motivations for this
feature are:
1. To preserve noalias function attribute information when inlining
2. To provide the ability to model block-scope C99 restrict pointers
Neither of these two abilities are added here, only the necessary
infrastructure. In fact, there should be no change to existing functionality,
only the addition of new features. The logic that converts noalias function
parameters into this metadata during inlining will come in a follow-up commit.
What is added here is the ability to generally specify noalias memory-access
sets. Regarding the metadata, alias-analysis scopes are defined similar to TBAA
nodes:
!scope0 = metadata !{ metadata !"scope of foo()" }
!scope1 = metadata !{ metadata !"scope 1", metadata !scope0 }
!scope2 = metadata !{ metadata !"scope 2", metadata !scope0 }
!scope3 = metadata !{ metadata !"scope 2.1", metadata !scope2 }
!scope4 = metadata !{ metadata !"scope 2.2", metadata !scope2 }
Loads and stores can be tagged with an alias-analysis scope, and also, with a
noalias tag for a specific scope:
... = load %ptr1, !alias.scope !{ !scope1 }
... = load %ptr2, !alias.scope !{ !scope1, !scope2 }, !noalias !{ !scope1 }
When evaluating an aliasing query, if one of the instructions is associated
with an alias.scope id that is identical to the noalias scope associated with
the other instruction, or is a descendant (in the scope hierarchy) of the
noalias scope associated with the other instruction, then the two memory
accesses are assumed not to alias.
Note that is the first element of the scope metadata is a string, then it can
be combined accross functions and translation units. The string can be replaced
by a self-reference to create globally unqiue scope identifiers.
[Note: This overview is slightly stylized, since the metadata nodes really need
to just be numbers (!0 instead of !scope0), and the scope lists are also global
unnamed metadata.]
Existing noalias metadata in a callee is "cloned" for use by the inlined code.
This is necessary because the aliasing scopes are unique to each call site
(because of possible control dependencies on the aliasing properties). For
example, consider a function: foo(noalias a, noalias b) { *a = *b; } that gets
inlined into bar() { ... if (...) foo(a1, b1); ... if (...) foo(a2, b2); } --
now just because we know that a1 does not alias with b1 at the first call site,
and a2 does not alias with b2 at the second call site, we cannot let inlining
these functons have the metadata imply that a1 does not alias with b2.
llvm-svn: 213864
2014-07-24 22:25:39 +08:00
|
|
|
OS << "(noalias=";
|
|
|
|
if (NoAliasInfo->getNumOperands() > 0)
|
|
|
|
for (unsigned i = 0, ie = NoAliasInfo->getNumOperands(); i != ie; ++i) {
|
2015-06-27 06:28:47 +08:00
|
|
|
NoAliasInfo->getOperand(i)->printAsOperand(OS, MST);
|
Add scoped-noalias metadata
This commit adds scoped noalias metadata. The primary motivations for this
feature are:
1. To preserve noalias function attribute information when inlining
2. To provide the ability to model block-scope C99 restrict pointers
Neither of these two abilities are added here, only the necessary
infrastructure. In fact, there should be no change to existing functionality,
only the addition of new features. The logic that converts noalias function
parameters into this metadata during inlining will come in a follow-up commit.
What is added here is the ability to generally specify noalias memory-access
sets. Regarding the metadata, alias-analysis scopes are defined similar to TBAA
nodes:
!scope0 = metadata !{ metadata !"scope of foo()" }
!scope1 = metadata !{ metadata !"scope 1", metadata !scope0 }
!scope2 = metadata !{ metadata !"scope 2", metadata !scope0 }
!scope3 = metadata !{ metadata !"scope 2.1", metadata !scope2 }
!scope4 = metadata !{ metadata !"scope 2.2", metadata !scope2 }
Loads and stores can be tagged with an alias-analysis scope, and also, with a
noalias tag for a specific scope:
... = load %ptr1, !alias.scope !{ !scope1 }
... = load %ptr2, !alias.scope !{ !scope1, !scope2 }, !noalias !{ !scope1 }
When evaluating an aliasing query, if one of the instructions is associated
with an alias.scope id that is identical to the noalias scope associated with
the other instruction, or is a descendant (in the scope hierarchy) of the
noalias scope associated with the other instruction, then the two memory
accesses are assumed not to alias.
Note that is the first element of the scope metadata is a string, then it can
be combined accross functions and translation units. The string can be replaced
by a self-reference to create globally unqiue scope identifiers.
[Note: This overview is slightly stylized, since the metadata nodes really need
to just be numbers (!0 instead of !scope0), and the scope lists are also global
unnamed metadata.]
Existing noalias metadata in a callee is "cloned" for use by the inlined code.
This is necessary because the aliasing scopes are unique to each call site
(because of possible control dependencies on the aliasing properties). For
example, consider a function: foo(noalias a, noalias b) { *a = *b; } that gets
inlined into bar() { ... if (...) foo(a1, b1); ... if (...) foo(a2, b2); } --
now just because we know that a1 does not alias with b1 at the first call site,
and a2 does not alias with b2 at the second call site, we cannot let inlining
these functons have the metadata imply that a1 does not alias with b2.
llvm-svn: 213864
2014-07-24 22:25:39 +08:00
|
|
|
if (i != ie-1)
|
|
|
|
OS << ",";
|
|
|
|
}
|
|
|
|
else
|
|
|
|
OS << "<unknown>";
|
|
|
|
OS << ")";
|
|
|
|
}
|
|
|
|
|
2015-06-27 06:06:47 +08:00
|
|
|
if (isNonTemporal())
|
2011-04-30 07:45:22 +08:00
|
|
|
OS << "(nontemporal)";
|
[CodeGen] Split out the notions of MI invariance and MI dereferenceability.
Summary:
An IR load can be invariant, dereferenceable, neither, or both. But
currently, MI's notion of invariance is IR-invariant &&
IR-dereferenceable.
This patch splits up the notions of invariance and dereferenceability at
the MI level. It's NFC, so adds some probably-unnecessary
"is-dereferenceable" checks, which we can remove later if desired.
Reviewers: chandlerc, tstellarAMD
Subscribers: jholewinski, arsenm, nemanjai, llvm-commits
Differential Revision: https://reviews.llvm.org/D23371
llvm-svn: 281151
2016-09-11 09:38:58 +08:00
|
|
|
if (isDereferenceable())
|
|
|
|
OS << "(dereferenceable)";
|
2015-06-27 06:06:47 +08:00
|
|
|
if (isInvariant())
|
2015-06-27 03:00:11 +08:00
|
|
|
OS << "(invariant)";
|
2017-07-13 10:28:54 +08:00
|
|
|
if (getFlags() & MOTargetFlag1)
|
|
|
|
OS << "(flag1)";
|
|
|
|
if (getFlags() & MOTargetFlag2)
|
|
|
|
OS << "(flag2)";
|
|
|
|
if (getFlags() & MOTargetFlag3)
|
|
|
|
OS << "(flag3)";
|
2009-09-23 09:33:16 +08:00
|
|
|
}
|
|
|
|
|
2007-12-31 05:56:09 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// MachineInstr Implementation
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
2012-12-21 06:53:58 +08:00
|
|
|
void MachineInstr::addImplicitDefUseOperands(MachineFunction &MF) {
|
2011-06-29 03:10:37 +08:00
|
|
|
if (MCID->ImplicitDefs)
|
2015-12-05 15:13:35 +08:00
|
|
|
for (const MCPhysReg *ImpDefs = MCID->getImplicitDefs(); *ImpDefs;
|
|
|
|
++ImpDefs)
|
2012-12-21 06:53:58 +08:00
|
|
|
addOperand(MF, MachineOperand::CreateReg(*ImpDefs, true, true));
|
2011-06-29 03:10:37 +08:00
|
|
|
if (MCID->ImplicitUses)
|
2015-12-05 15:13:35 +08:00
|
|
|
for (const MCPhysReg *ImpUses = MCID->getImplicitUses(); *ImpUses;
|
|
|
|
++ImpUses)
|
2012-12-21 06:53:58 +08:00
|
|
|
addOperand(MF, MachineOperand::CreateReg(*ImpUses, false, true));
|
2006-11-14 07:34:06 +08:00
|
|
|
}
|
|
|
|
|
2010-04-09 12:34:03 +08:00
|
|
|
/// MachineInstr ctor - This constructor creates a MachineInstr and adds the
|
|
|
|
/// implicit operands. It reserves space for the number of operands specified by
|
2011-06-29 03:10:37 +08:00
|
|
|
/// the MCInstrDesc.
|
2012-12-21 06:53:58 +08:00
|
|
|
MachineInstr::MachineInstr(MachineFunction &MF, const MCInstrDesc &tid,
|
2015-02-07 20:28:15 +08:00
|
|
|
DebugLoc dl, bool NoImp)
|
2017-05-31 09:10:10 +08:00
|
|
|
: MCID(&tid), debugLoc(std::move(dl)) {
|
IR: Split Metadata from Value
Split `Metadata` away from the `Value` class hierarchy, as part of
PR21532. Assembly and bitcode changes are in the wings, but this is the
bulk of the change for the IR C++ API.
I have a follow-up patch prepared for `clang`. If this breaks other
sub-projects, I apologize in advance :(. Help me compile it on Darwin
I'll try to fix it. FWIW, the errors should be easy to fix, so it may
be simpler to just fix it yourself.
This breaks the build for all metadata-related code that's out-of-tree.
Rest assured the transition is mechanical and the compiler should catch
almost all of the problems.
Here's a quick guide for updating your code:
- `Metadata` is the root of a class hierarchy with three main classes:
`MDNode`, `MDString`, and `ValueAsMetadata`. It is distinct from
the `Value` class hierarchy. It is typeless -- i.e., instances do
*not* have a `Type`.
- `MDNode`'s operands are all `Metadata *` (instead of `Value *`).
- `TrackingVH<MDNode>` and `WeakVH` referring to metadata can be
replaced with `TrackingMDNodeRef` and `TrackingMDRef`, respectively.
If you're referring solely to resolved `MDNode`s -- post graph
construction -- just use `MDNode*`.
- `MDNode` (and the rest of `Metadata`) have only limited support for
`replaceAllUsesWith()`.
As long as an `MDNode` is pointing at a forward declaration -- the
result of `MDNode::getTemporary()` -- it maintains a side map of its
uses and can RAUW itself. Once the forward declarations are fully
resolved RAUW support is dropped on the ground. This means that
uniquing collisions on changing operands cause nodes to become
"distinct". (This already happened fairly commonly, whenever an
operand went to null.)
If you're constructing complex (non self-reference) `MDNode` cycles,
you need to call `MDNode::resolveCycles()` on each node (or on a
top-level node that somehow references all of the nodes). Also,
don't do that. Metadata cycles (and the RAUW machinery needed to
construct them) are expensive.
- An `MDNode` can only refer to a `Constant` through a bridge called
`ConstantAsMetadata` (one of the subclasses of `ValueAsMetadata`).
As a side effect, accessing an operand of an `MDNode` that is known
to be, e.g., `ConstantInt`, takes three steps: first, cast from
`Metadata` to `ConstantAsMetadata`; second, extract the `Constant`;
third, cast down to `ConstantInt`.
The eventual goal is to introduce `MDInt`/`MDFloat`/etc. and have
metadata schema owners transition away from using `Constant`s when
the type isn't important (and they don't care about referring to
`GlobalValue`s).
In the meantime, I've added transitional API to the `mdconst`
namespace that matches semantics with the old code, in order to
avoid adding the error-prone three-step equivalent to every call
site. If your old code was:
MDNode *N = foo();
bar(isa <ConstantInt>(N->getOperand(0)));
baz(cast <ConstantInt>(N->getOperand(1)));
bak(cast_or_null <ConstantInt>(N->getOperand(2)));
bat(dyn_cast <ConstantInt>(N->getOperand(3)));
bay(dyn_cast_or_null<ConstantInt>(N->getOperand(4)));
you can trivially match its semantics with:
MDNode *N = foo();
bar(mdconst::hasa <ConstantInt>(N->getOperand(0)));
baz(mdconst::extract <ConstantInt>(N->getOperand(1)));
bak(mdconst::extract_or_null <ConstantInt>(N->getOperand(2)));
bat(mdconst::dyn_extract <ConstantInt>(N->getOperand(3)));
bay(mdconst::dyn_extract_or_null<ConstantInt>(N->getOperand(4)));
and when you transition your metadata schema to `MDInt`:
MDNode *N = foo();
bar(isa <MDInt>(N->getOperand(0)));
baz(cast <MDInt>(N->getOperand(1)));
bak(cast_or_null <MDInt>(N->getOperand(2)));
bat(dyn_cast <MDInt>(N->getOperand(3)));
bay(dyn_cast_or_null<MDInt>(N->getOperand(4)));
- A `CallInst` -- specifically, intrinsic instructions -- can refer to
metadata through a bridge called `MetadataAsValue`. This is a
subclass of `Value` where `getType()->isMetadataTy()`.
`MetadataAsValue` is the *only* class that can legally refer to a
`LocalAsMetadata`, which is a bridged form of non-`Constant` values
like `Argument` and `Instruction`. It can also refer to any other
`Metadata` subclass.
(I'll break all your testcases in a follow-up commit, when I propagate
this change to assembly.)
llvm-svn: 223802
2014-12-10 02:38:53 +08:00
|
|
|
assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor");
|
|
|
|
|
2013-01-05 13:00:09 +08:00
|
|
|
// Reserve space for the expected number of operands.
|
|
|
|
if (unsigned NumOps = MCID->getNumOperands() +
|
|
|
|
MCID->getNumImplicitDefs() + MCID->getNumImplicitUses()) {
|
|
|
|
CapOperands = OperandCapacity::get(NumOps);
|
|
|
|
Operands = MF.allocateOperandArray(CapOperands);
|
|
|
|
}
|
|
|
|
|
2009-01-28 07:20:29 +08:00
|
|
|
if (!NoImp)
|
2012-12-21 06:53:58 +08:00
|
|
|
addImplicitDefUseOperands(MF);
|
2009-01-28 07:20:29 +08:00
|
|
|
}
|
|
|
|
|
2004-07-09 22:45:17 +08:00
|
|
|
/// MachineInstr ctor - Copies MachineInstr arg exactly
|
|
|
|
///
|
2008-07-19 08:37:25 +08:00
|
|
|
MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
|
2017-05-31 09:10:10 +08:00
|
|
|
: MCID(&MI.getDesc()), NumMemRefs(MI.NumMemRefs), MemRefs(MI.MemRefs),
|
|
|
|
debugLoc(MI.getDebugLoc()) {
|
IR: Split Metadata from Value
Split `Metadata` away from the `Value` class hierarchy, as part of
PR21532. Assembly and bitcode changes are in the wings, but this is the
bulk of the change for the IR C++ API.
I have a follow-up patch prepared for `clang`. If this breaks other
sub-projects, I apologize in advance :(. Help me compile it on Darwin
I'll try to fix it. FWIW, the errors should be easy to fix, so it may
be simpler to just fix it yourself.
This breaks the build for all metadata-related code that's out-of-tree.
Rest assured the transition is mechanical and the compiler should catch
almost all of the problems.
Here's a quick guide for updating your code:
- `Metadata` is the root of a class hierarchy with three main classes:
`MDNode`, `MDString`, and `ValueAsMetadata`. It is distinct from
the `Value` class hierarchy. It is typeless -- i.e., instances do
*not* have a `Type`.
- `MDNode`'s operands are all `Metadata *` (instead of `Value *`).
- `TrackingVH<MDNode>` and `WeakVH` referring to metadata can be
replaced with `TrackingMDNodeRef` and `TrackingMDRef`, respectively.
If you're referring solely to resolved `MDNode`s -- post graph
construction -- just use `MDNode*`.
- `MDNode` (and the rest of `Metadata`) have only limited support for
`replaceAllUsesWith()`.
As long as an `MDNode` is pointing at a forward declaration -- the
result of `MDNode::getTemporary()` -- it maintains a side map of its
uses and can RAUW itself. Once the forward declarations are fully
resolved RAUW support is dropped on the ground. This means that
uniquing collisions on changing operands cause nodes to become
"distinct". (This already happened fairly commonly, whenever an
operand went to null.)
If you're constructing complex (non self-reference) `MDNode` cycles,
you need to call `MDNode::resolveCycles()` on each node (or on a
top-level node that somehow references all of the nodes). Also,
don't do that. Metadata cycles (and the RAUW machinery needed to
construct them) are expensive.
- An `MDNode` can only refer to a `Constant` through a bridge called
`ConstantAsMetadata` (one of the subclasses of `ValueAsMetadata`).
As a side effect, accessing an operand of an `MDNode` that is known
to be, e.g., `ConstantInt`, takes three steps: first, cast from
`Metadata` to `ConstantAsMetadata`; second, extract the `Constant`;
third, cast down to `ConstantInt`.
The eventual goal is to introduce `MDInt`/`MDFloat`/etc. and have
metadata schema owners transition away from using `Constant`s when
the type isn't important (and they don't care about referring to
`GlobalValue`s).
In the meantime, I've added transitional API to the `mdconst`
namespace that matches semantics with the old code, in order to
avoid adding the error-prone three-step equivalent to every call
site. If your old code was:
MDNode *N = foo();
bar(isa <ConstantInt>(N->getOperand(0)));
baz(cast <ConstantInt>(N->getOperand(1)));
bak(cast_or_null <ConstantInt>(N->getOperand(2)));
bat(dyn_cast <ConstantInt>(N->getOperand(3)));
bay(dyn_cast_or_null<ConstantInt>(N->getOperand(4)));
you can trivially match its semantics with:
MDNode *N = foo();
bar(mdconst::hasa <ConstantInt>(N->getOperand(0)));
baz(mdconst::extract <ConstantInt>(N->getOperand(1)));
bak(mdconst::extract_or_null <ConstantInt>(N->getOperand(2)));
bat(mdconst::dyn_extract <ConstantInt>(N->getOperand(3)));
bay(mdconst::dyn_extract_or_null<ConstantInt>(N->getOperand(4)));
and when you transition your metadata schema to `MDInt`:
MDNode *N = foo();
bar(isa <MDInt>(N->getOperand(0)));
baz(cast <MDInt>(N->getOperand(1)));
bak(cast_or_null <MDInt>(N->getOperand(2)));
bat(dyn_cast <MDInt>(N->getOperand(3)));
bay(dyn_cast_or_null<MDInt>(N->getOperand(4)));
- A `CallInst` -- specifically, intrinsic instructions -- can refer to
metadata through a bridge called `MetadataAsValue`. This is a
subclass of `Value` where `getType()->isMetadataTy()`.
`MetadataAsValue` is the *only* class that can legally refer to a
`LocalAsMetadata`, which is a bridged form of non-`Constant` values
like `Argument` and `Instruction`. It can also refer to any other
`Metadata` subclass.
(I'll break all your testcases in a follow-up commit, when I propagate
this change to assembly.)
llvm-svn: 223802
2014-12-10 02:38:53 +08:00
|
|
|
assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor");
|
|
|
|
|
2013-01-05 13:00:09 +08:00
|
|
|
CapOperands = OperandCapacity::get(MI.getNumOperands());
|
|
|
|
Operands = MF.allocateOperandArray(CapOperands);
|
2004-05-24 04:58:02 +08:00
|
|
|
|
2013-01-05 13:05:51 +08:00
|
|
|
// Copy operands.
|
2015-02-22 01:08:08 +08:00
|
|
|
for (const MachineOperand &MO : MI.operands())
|
|
|
|
addOperand(MF, MO);
|
2004-05-24 11:14:18 +08:00
|
|
|
|
2012-12-19 05:36:05 +08:00
|
|
|
// Copy all the sensible flags.
|
|
|
|
setFlags(MI.Flags);
|
2004-02-16 15:17:43 +08:00
|
|
|
}
|
|
|
|
|
2008-01-01 09:12:31 +08:00
|
|
|
/// getRegInfo - If this instruction is embedded into a MachineFunction,
|
|
|
|
/// return the MachineRegisterInfo object for the current function, otherwise
|
|
|
|
/// return null.
|
|
|
|
MachineRegisterInfo *MachineInstr::getRegInfo() {
|
|
|
|
if (MachineBasicBlock *MBB = getParent())
|
2008-07-09 07:59:09 +08:00
|
|
|
return &MBB->getParent()->getRegInfo();
|
2014-04-14 08:51:57 +08:00
|
|
|
return nullptr;
|
2008-01-01 09:12:31 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
|
|
|
|
/// this instruction from their respective use lists. This requires that the
|
|
|
|
/// operands already be on their use lists.
|
2012-08-10 06:49:37 +08:00
|
|
|
void MachineInstr::RemoveRegOperandsFromUseLists(MachineRegisterInfo &MRI) {
|
2015-02-22 01:08:08 +08:00
|
|
|
for (MachineOperand &MO : operands())
|
|
|
|
if (MO.isReg())
|
|
|
|
MRI.removeRegOperandFromUseList(&MO);
|
2008-01-01 09:12:31 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/// AddRegOperandsToUseLists - Add all of the register operands in
|
|
|
|
/// this instruction from their respective use lists. This requires that the
|
|
|
|
/// operands not be on their use lists yet.
|
2012-08-10 06:49:37 +08:00
|
|
|
void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &MRI) {
|
2015-02-22 01:08:08 +08:00
|
|
|
for (MachineOperand &MO : operands())
|
|
|
|
if (MO.isReg())
|
|
|
|
MRI.addRegOperandToUseList(&MO);
|
2008-01-01 09:12:31 +08:00
|
|
|
}
|
|
|
|
|
2012-12-21 06:54:05 +08:00
|
|
|
void MachineInstr::addOperand(const MachineOperand &Op) {
|
|
|
|
MachineBasicBlock *MBB = getParent();
|
|
|
|
assert(MBB && "Use MachineInstrBuilder to add operands to dangling instrs");
|
|
|
|
MachineFunction *MF = MBB->getParent();
|
|
|
|
assert(MF && "Use MachineInstrBuilder to add operands to dangling instrs");
|
|
|
|
addOperand(*MF, Op);
|
|
|
|
}
|
|
|
|
|
2013-01-05 13:00:09 +08:00
|
|
|
/// Move NumOps MachineOperands from Src to Dst, with support for overlapping
|
|
|
|
/// ranges. If MRI is non-null also update use-def chains.
|
|
|
|
static void moveOperands(MachineOperand *Dst, MachineOperand *Src,
|
|
|
|
unsigned NumOps, MachineRegisterInfo *MRI) {
|
|
|
|
if (MRI)
|
|
|
|
return MRI->moveOperands(Dst, Src, NumOps);
|
|
|
|
|
2016-03-27 02:20:02 +08:00
|
|
|
// MachineOperand is a trivially copyable type so we can just use memmove.
|
2015-02-22 00:22:48 +08:00
|
|
|
std::memmove(Dst, Src, NumOps * sizeof(MachineOperand));
|
2013-01-05 13:00:09 +08:00
|
|
|
}
|
|
|
|
|
2008-01-01 09:12:31 +08:00
|
|
|
/// addOperand - Add the specified operand to the instruction. If it is an
|
|
|
|
/// implicit operand, it is added to the end of the operand list. If it is
|
|
|
|
/// an explicit operand it is added at the end of the explicit operand list
|
2011-08-25 00:44:17 +08:00
|
|
|
/// (before the first implicit operand).
|
2012-12-21 06:54:05 +08:00
|
|
|
void MachineInstr::addOperand(MachineFunction &MF, const MachineOperand &Op) {
|
2011-09-29 08:40:51 +08:00
|
|
|
assert(MCID && "Cannot add operands before providing an instr descriptor");
|
2008-12-10 06:45:08 +08:00
|
|
|
|
2013-01-05 13:00:09 +08:00
|
|
|
// Check if we're adding one of our existing operands.
|
|
|
|
if (&Op >= Operands && &Op < Operands + NumOperands) {
|
|
|
|
// This is unusual: MI->addOperand(MI->getOperand(i)).
|
|
|
|
// If adding Op requires reallocating or moving existing operands around,
|
|
|
|
// the Op reference could go stale. Support it by copying Op.
|
|
|
|
MachineOperand CopyOp(Op);
|
|
|
|
return addOperand(MF, CopyOp);
|
|
|
|
}
|
2011-09-29 08:40:51 +08:00
|
|
|
|
|
|
|
// Find the insert location for the new operand. Implicit registers go at
|
2013-01-05 13:00:09 +08:00
|
|
|
// the end, everything else goes before the implicit regs.
|
|
|
|
//
|
2011-09-29 08:40:51 +08:00
|
|
|
// FIXME: Allow mixed explicit and implicit operands on inline asm.
|
|
|
|
// InstrEmitter::EmitSpecialNode() is marking inline asm clobbers as
|
|
|
|
// implicit-defs, but they must not be moved around. See the FIXME in
|
|
|
|
// InstrEmitter.cpp.
|
2013-01-05 13:00:09 +08:00
|
|
|
unsigned OpNo = getNumOperands();
|
|
|
|
bool isImpReg = Op.isReg() && Op.isImplicit();
|
2011-09-29 08:40:51 +08:00
|
|
|
if (!isImpReg && !isInlineAsm()) {
|
|
|
|
while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) {
|
|
|
|
--OpNo;
|
2012-09-05 02:36:28 +08:00
|
|
|
assert(!Operands[OpNo].isTied() && "Cannot move tied operands");
|
2008-01-01 09:12:31 +08:00
|
|
|
}
|
|
|
|
}
|
2011-08-25 00:44:17 +08:00
|
|
|
|
2013-10-15 22:40:46 +08:00
|
|
|
#ifndef NDEBUG
|
2013-10-15 22:18:10 +08:00
|
|
|
bool isMetaDataOp = Op.getType() == MachineOperand::MO_Metadata;
|
2011-09-29 08:40:51 +08:00
|
|
|
// OpNo now points as the desired insertion point. Unless this is a variadic
|
|
|
|
// instruction, only implicit regs are allowed beyond MCID->getNumOperands().
|
2012-07-05 07:53:23 +08:00
|
|
|
// RegMask operands go between the explicit and implicit operands.
|
|
|
|
assert((isImpReg || Op.isRegMask() || MCID->isVariadic() ||
|
2013-10-15 22:18:10 +08:00
|
|
|
OpNo < MCID->getNumOperands() || isMetaDataOp) &&
|
2011-09-29 08:40:51 +08:00
|
|
|
"Trying to add an operand to a machine instr that is already done!");
|
2013-10-15 22:40:46 +08:00
|
|
|
#endif
|
2008-01-01 09:12:31 +08:00
|
|
|
|
2013-01-05 13:00:09 +08:00
|
|
|
MachineRegisterInfo *MRI = getRegInfo();
|
|
|
|
|
|
|
|
// Determine if the Operands array needs to be reallocated.
|
|
|
|
// Save the old capacity and operand array.
|
|
|
|
OperandCapacity OldCap = CapOperands;
|
|
|
|
MachineOperand *OldOperands = Operands;
|
|
|
|
if (!OldOperands || OldCap.getSize() == getNumOperands()) {
|
|
|
|
CapOperands = OldOperands ? OldCap.getNext() : OldCap.get(1);
|
|
|
|
Operands = MF.allocateOperandArray(CapOperands);
|
|
|
|
// Move the operands before the insertion point.
|
|
|
|
if (OpNo)
|
|
|
|
moveOperands(Operands, OldOperands, OpNo, MRI);
|
|
|
|
}
|
|
|
|
|
|
|
|
// Move the operands following the insertion point.
|
|
|
|
if (OpNo != NumOperands)
|
|
|
|
moveOperands(Operands + OpNo + 1, OldOperands + OpNo, NumOperands - OpNo,
|
|
|
|
MRI);
|
|
|
|
++NumOperands;
|
|
|
|
|
|
|
|
// Deallocate the old operand array.
|
|
|
|
if (OldOperands != Operands && OldOperands)
|
|
|
|
MF.deallocateOperandArray(OldCap, OldOperands);
|
|
|
|
|
|
|
|
// Copy Op into place. It still needs to be inserted into the MRI use lists.
|
|
|
|
MachineOperand *NewMO = new (Operands + OpNo) MachineOperand(Op);
|
|
|
|
NewMO->ParentMI = this;
|
|
|
|
|
|
|
|
// When adding a register operand, tell MRI about it.
|
|
|
|
if (NewMO->isReg()) {
|
2012-08-10 06:49:37 +08:00
|
|
|
// Ensure isOnRegUseList() returns false, regardless of Op's status.
|
2014-04-14 08:51:57 +08:00
|
|
|
NewMO->Contents.Reg.Prev = nullptr;
|
2012-09-05 02:36:28 +08:00
|
|
|
// Ignore existing ties. This is not a property that can be copied.
|
2013-01-05 13:00:09 +08:00
|
|
|
NewMO->TiedTo = 0;
|
|
|
|
// Add the new operand to MRI, but only for instructions in an MBB.
|
|
|
|
if (MRI)
|
|
|
|
MRI->addRegOperandToUseList(NewMO);
|
2012-08-30 22:39:06 +08:00
|
|
|
// The MCID operand information isn't accurate until we start adding
|
|
|
|
// explicit operands. The implicit operands are added first, then the
|
|
|
|
// explicits are inserted before them.
|
|
|
|
if (!isImpReg) {
|
2012-09-05 02:36:28 +08:00
|
|
|
// Tie uses to defs as indicated in MCInstrDesc.
|
2013-01-05 13:00:09 +08:00
|
|
|
if (NewMO->isUse()) {
|
2012-08-30 22:39:06 +08:00
|
|
|
int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO);
|
2012-09-01 04:50:53 +08:00
|
|
|
if (DefIdx != -1)
|
|
|
|
tieOperands(DefIdx, OpNo);
|
Add a MachineOperand::isTied() flag.
While in SSA form, a MachineInstr can have pairs of tied defs and uses.
The tied operands are used to represent read-modify-write operands that
must be assigned the same physical register.
Previously, tied operand pairs were computed from fixed MCInstrDesc
fields, or by using black magic on inline assembly instructions.
The isTied flag makes it possible to add tied operands to any
instruction while getting rid of (some of) the inlineasm magic.
Tied operands on normal instructions are needed to represent predicated
individual instructions in SSA form. An extra <tied,imp-use> operand is
required to represent the output value when the instruction predicate is
false.
Adding a predicate to:
%vreg0<def> = ADD %vreg1, %vreg2
Will look like:
%vreg0<tied,def> = ADD %vreg1, %vreg2, pred:3, %vreg7<tied,imp-use>
The virtual register %vreg7 is the value given to %vreg0 when the
predicate is false. It will be assigned the same physreg as %vreg0.
This commit adds the isTied flag and sets it based on MCInstrDesc when
building an instruction. The flag is not used for anything yet.
llvm-svn: 162774
2012-08-29 02:34:41 +08:00
|
|
|
}
|
2012-08-30 22:39:06 +08:00
|
|
|
// If the register operand is flagged as early, mark the operand as such.
|
|
|
|
if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1)
|
2013-01-05 13:00:09 +08:00
|
|
|
NewMO->setIsEarlyClobber(true);
|
2008-01-01 09:12:31 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/// RemoveOperand - Erase an operand from an instruction, leaving it with one
|
|
|
|
/// fewer operand than it started with.
|
|
|
|
///
|
|
|
|
void MachineInstr::RemoveOperand(unsigned OpNo) {
|
2012-12-23 01:13:06 +08:00
|
|
|
assert(OpNo < getNumOperands() && "Invalid operand number");
|
2012-08-29 08:37:58 +08:00
|
|
|
untieRegOperand(OpNo);
|
2011-08-25 00:44:17 +08:00
|
|
|
|
2012-09-05 02:36:28 +08:00
|
|
|
#ifndef NDEBUG
|
|
|
|
// Moving tied operands would break the ties.
|
2012-12-23 01:13:06 +08:00
|
|
|
for (unsigned i = OpNo + 1, e = getNumOperands(); i != e; ++i)
|
2012-09-05 02:36:28 +08:00
|
|
|
if (Operands[i].isReg())
|
|
|
|
assert(!Operands[i].isTied() && "Cannot move tied operands");
|
|
|
|
#endif
|
|
|
|
|
2013-01-05 13:00:09 +08:00
|
|
|
MachineRegisterInfo *MRI = getRegInfo();
|
|
|
|
if (MRI && Operands[OpNo].isReg())
|
|
|
|
MRI->removeRegOperandFromUseList(Operands + OpNo);
|
2008-01-01 09:12:31 +08:00
|
|
|
|
2013-01-05 13:00:09 +08:00
|
|
|
// Don't call the MachineOperand destructor. A lot of this code depends on
|
|
|
|
// MachineOperand having a trivial destructor anyway, and adding a call here
|
|
|
|
// wouldn't make it 'destructor-correct'.
|
|
|
|
|
|
|
|
if (unsigned N = NumOperands - 1 - OpNo)
|
|
|
|
moveOperands(Operands + OpNo, Operands + OpNo + 1, N, MRI);
|
|
|
|
--NumOperands;
|
2008-01-01 09:12:31 +08:00
|
|
|
}
|
|
|
|
|
2009-09-26 04:36:54 +08:00
|
|
|
/// addMemOperand - Add a MachineMemOperand to the machine instruction.
|
|
|
|
/// This function should be used only occasionally. The setMemRefs function
|
|
|
|
/// is the primary method for setting up a MachineInstr's MemRefs list.
|
2008-07-08 07:14:23 +08:00
|
|
|
void MachineInstr::addMemOperand(MachineFunction &MF,
|
2009-09-26 04:36:54 +08:00
|
|
|
MachineMemOperand *MO) {
|
|
|
|
mmo_iterator OldMemRefs = MemRefs;
|
2013-01-08 07:21:41 +08:00
|
|
|
unsigned OldNumMemRefs = NumMemRefs;
|
2008-07-08 07:14:23 +08:00
|
|
|
|
2013-01-08 07:21:41 +08:00
|
|
|
unsigned NewNum = NumMemRefs + 1;
|
2009-09-26 04:36:54 +08:00
|
|
|
mmo_iterator NewMemRefs = MF.allocateMemRefsArray(NewNum);
|
2008-07-08 07:14:23 +08:00
|
|
|
|
2012-03-17 00:39:27 +08:00
|
|
|
std::copy(OldMemRefs, OldMemRefs + OldNumMemRefs, NewMemRefs);
|
2009-09-26 04:36:54 +08:00
|
|
|
NewMemRefs[NewNum - 1] = MO;
|
2013-01-08 07:21:41 +08:00
|
|
|
setMemRefs(NewMemRefs, NewMemRefs + NewNum);
|
2009-09-26 04:36:54 +08:00
|
|
|
}
|
2008-01-01 09:12:31 +08:00
|
|
|
|
2016-01-07 03:33:12 +08:00
|
|
|
/// Check to see if the MMOs pointed to by the two MemRefs arrays are
|
2016-02-26 10:07:36 +08:00
|
|
|
/// identical.
|
2016-01-07 03:33:12 +08:00
|
|
|
static bool hasIdenticalMMOs(const MachineInstr &MI1, const MachineInstr &MI2) {
|
|
|
|
auto I1 = MI1.memoperands_begin(), E1 = MI1.memoperands_end();
|
|
|
|
auto I2 = MI2.memoperands_begin(), E2 = MI2.memoperands_end();
|
|
|
|
if ((E1 - I1) != (E2 - I2))
|
|
|
|
return false;
|
|
|
|
for (; I1 != E1; ++I1, ++I2) {
|
|
|
|
if (**I1 != **I2)
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2016-01-06 12:39:03 +08:00
|
|
|
std::pair<MachineInstr::mmo_iterator, unsigned>
|
|
|
|
MachineInstr::mergeMemRefsWith(const MachineInstr& Other) {
|
2016-01-07 03:33:12 +08:00
|
|
|
|
|
|
|
// If either of the incoming memrefs are empty, we must be conservative and
|
|
|
|
// treat this as if we've exhausted our space for memrefs and dropped them.
|
|
|
|
if (memoperands_empty() || Other.memoperands_empty())
|
|
|
|
return std::make_pair(nullptr, 0);
|
|
|
|
|
|
|
|
// If both instructions have identical memrefs, we don't need to merge them.
|
|
|
|
// Since many instructions have a single memref, and we tend to merge things
|
|
|
|
// like pairs of loads from the same location, this catches a large number of
|
|
|
|
// cases in practice.
|
|
|
|
if (hasIdenticalMMOs(*this, Other))
|
|
|
|
return std::make_pair(MemRefs, NumMemRefs);
|
2016-02-26 10:07:36 +08:00
|
|
|
|
2016-01-06 12:39:03 +08:00
|
|
|
// TODO: consider uniquing elements within the operand lists to reduce
|
|
|
|
// space usage and fall back to conservative information less often.
|
2016-01-07 03:33:12 +08:00
|
|
|
size_t CombinedNumMemRefs = NumMemRefs + Other.NumMemRefs;
|
|
|
|
|
|
|
|
// If we don't have enough room to store this many memrefs, be conservative
|
|
|
|
// and drop them. Otherwise, we'd fail asserts when trying to add them to
|
|
|
|
// the new instruction.
|
|
|
|
if (CombinedNumMemRefs != uint8_t(CombinedNumMemRefs))
|
|
|
|
return std::make_pair(nullptr, 0);
|
2016-01-06 12:39:03 +08:00
|
|
|
|
2017-10-11 07:50:49 +08:00
|
|
|
MachineFunction *MF = getMF();
|
2016-01-06 12:39:03 +08:00
|
|
|
mmo_iterator MemBegin = MF->allocateMemRefsArray(CombinedNumMemRefs);
|
|
|
|
mmo_iterator MemEnd = std::copy(memoperands_begin(), memoperands_end(),
|
|
|
|
MemBegin);
|
|
|
|
MemEnd = std::copy(Other.memoperands_begin(), Other.memoperands_end(),
|
|
|
|
MemEnd);
|
2016-01-06 13:53:09 +08:00
|
|
|
assert(MemEnd - MemBegin == (ptrdiff_t)CombinedNumMemRefs &&
|
|
|
|
"missing memrefs");
|
2016-02-26 10:07:36 +08:00
|
|
|
|
2016-01-06 12:39:03 +08:00
|
|
|
return std::make_pair(MemBegin, CombinedNumMemRefs);
|
|
|
|
}
|
|
|
|
|
2012-03-18 01:03:45 +08:00
|
|
|
bool MachineInstr::hasPropertyInBundle(unsigned Mask, QueryType Type) const {
|
2013-01-11 02:42:44 +08:00
|
|
|
assert(!isBundledWithPred() && "Must be called on bundle header");
|
2016-02-23 04:49:58 +08:00
|
|
|
for (MachineBasicBlock::const_instr_iterator MII = getIterator();; ++MII) {
|
2012-03-18 01:03:45 +08:00
|
|
|
if (MII->getDesc().getFlags() & Mask) {
|
2011-12-09 03:23:10 +08:00
|
|
|
if (Type == AnyInBundle)
|
2011-12-07 15:15:52 +08:00
|
|
|
return true;
|
|
|
|
} else {
|
2013-01-10 09:29:42 +08:00
|
|
|
if (Type == AllInBundle && !MII->isBundle())
|
2011-12-07 15:15:52 +08:00
|
|
|
return false;
|
|
|
|
}
|
2013-01-10 09:29:42 +08:00
|
|
|
// This was the last instruction in the bundle.
|
|
|
|
if (!MII->isBundledWithSucc())
|
|
|
|
return Type == AllInBundle;
|
2011-12-07 06:12:01 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-02-28 04:01:33 +08:00
|
|
|
bool MachineInstr::isIdenticalTo(const MachineInstr &Other,
|
2010-03-03 09:44:33 +08:00
|
|
|
MICheckType Check) const {
|
2010-03-04 05:54:14 +08:00
|
|
|
// If opcodes or number of operands are not the same then the two
|
|
|
|
// instructions are obviously not identical.
|
2016-02-28 04:01:33 +08:00
|
|
|
if (Other.getOpcode() != getOpcode() ||
|
|
|
|
Other.getNumOperands() != getNumOperands())
|
2010-03-04 05:54:14 +08:00
|
|
|
return false;
|
|
|
|
|
2011-12-14 10:11:42 +08:00
|
|
|
if (isBundle()) {
|
2016-12-19 19:20:57 +08:00
|
|
|
// We have passed the test above that both instructions have the same
|
|
|
|
// opcode, so we know that both instructions are bundles here. Let's compare
|
|
|
|
// MIs inside the bundle.
|
|
|
|
assert(Other.isBundle() && "Expected that both instructions are bundles.");
|
2016-02-23 04:49:58 +08:00
|
|
|
MachineBasicBlock::const_instr_iterator I1 = getIterator();
|
2016-02-28 04:01:33 +08:00
|
|
|
MachineBasicBlock::const_instr_iterator I2 = Other.getIterator();
|
2016-12-19 19:20:57 +08:00
|
|
|
// Loop until we analysed the last intruction inside at least one of the
|
|
|
|
// bundles.
|
|
|
|
while (I1->isBundledWithSucc() && I2->isBundledWithSucc()) {
|
|
|
|
++I1;
|
2011-12-14 10:11:42 +08:00
|
|
|
++I2;
|
2016-12-19 19:20:57 +08:00
|
|
|
if (!I1->isIdenticalTo(*I2, Check))
|
2011-12-14 10:11:42 +08:00
|
|
|
return false;
|
|
|
|
}
|
2016-12-19 19:20:57 +08:00
|
|
|
// If we've reached the end of just one of the two bundles, but not both,
|
|
|
|
// the instructions are not identical.
|
|
|
|
if (I1->isBundledWithSucc() || I2->isBundledWithSucc())
|
|
|
|
return false;
|
2011-12-14 10:11:42 +08:00
|
|
|
}
|
|
|
|
|
2010-03-04 05:54:14 +08:00
|
|
|
// Check operands to make sure they match.
|
|
|
|
for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
|
|
|
|
const MachineOperand &MO = getOperand(i);
|
2016-02-28 04:01:33 +08:00
|
|
|
const MachineOperand &OMO = Other.getOperand(i);
|
2011-05-12 08:56:58 +08:00
|
|
|
if (!MO.isReg()) {
|
|
|
|
if (!MO.isIdenticalTo(OMO))
|
|
|
|
return false;
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
2010-03-04 05:54:14 +08:00
|
|
|
// Clients may or may not want to ignore defs when testing for equality.
|
|
|
|
// For example, machine CSE pass only cares about finding common
|
|
|
|
// subexpressions, so it's safe to ignore virtual register defs.
|
2011-05-12 08:56:58 +08:00
|
|
|
if (MO.isDef()) {
|
2010-03-04 05:54:14 +08:00
|
|
|
if (Check == IgnoreDefs)
|
|
|
|
continue;
|
2011-05-12 08:56:58 +08:00
|
|
|
else if (Check == IgnoreVRegDefs) {
|
MachineInstr: Make isEqual agree with getHashValue in MachineInstrExpressionTrait
MachineInstr::isIdenticalTo has a lot of logic for dealing with register
Defs (i.e. deciding whether to take them into account or ignore them).
This logic gets things wrong in some obscure cases, for instance if an
operand is not a Def for both the current MI and the one we are
comparing to.
I'm not sure if it's possible for this to happen for regular register
operands, but it may happen in the ARM backend for special operands
which use sentinel values for the register (i.e. 0, which is neither a
physical register nor a virtual one).
This causes MachineInstrExpressionTrait::isEqual (which uses
MachineInstr::isIdenticalTo) to return true for the following
instructions, which are the same except for the fact that one sets the
flags and the other one doesn't:
%1114 = ADDrsi %1113, %216, 17, 14, _, def _
%1115 = ADDrsi %1113, %216, 17, 14, _, _
OTOH, MachineInstrExpressionTrait::getHashValue returns different values
for the 2 instructions due to the different isDef on the last operand.
In practice this means that when trying to add those instructions to a
DenseMap, they will be considered different because of their different
hash values, but when growing the map we might get an assertion while
copying from the old buckets to the new buckets because isEqual
misleadingly returns true.
This patch makes sure that isEqual and getHashValue agree, by improving
the checks in MachineInstr::isIdenticalTo when we are ignoring virtual
register definitions (which is what the Trait uses). Firstly, instead of
checking isPhysicalRegister, we use !isVirtualRegister, so that we cover
both physical registers and sentinel values. Secondly, instead of
checking MachineOperand::isReg, we use MachineOperand::isIdenticalTo,
which checks isReg, isSubReg and isDef, which are the same values that
the hash function uses to compute the hash.
Note that the function is symmetric with this change, since if the
current operand is not a Def, we check MachineOperand::isIdenticalTo,
which returns false if the operands have different isDef's.
Differential Revision: https://reviews.llvm.org/D38789
llvm-svn: 315579
2017-10-12 21:59:51 +08:00
|
|
|
if (!TargetRegisterInfo::isVirtualRegister(MO.getReg()) ||
|
|
|
|
!TargetRegisterInfo::isVirtualRegister(OMO.getReg()))
|
|
|
|
if (!MO.isIdenticalTo(OMO))
|
2011-05-12 08:56:58 +08:00
|
|
|
return false;
|
|
|
|
} else {
|
|
|
|
if (!MO.isIdenticalTo(OMO))
|
|
|
|
return false;
|
|
|
|
if (Check == CheckKillDead && MO.isDead() != OMO.isDead())
|
2010-03-04 05:54:14 +08:00
|
|
|
return false;
|
2011-05-12 08:56:58 +08:00
|
|
|
}
|
|
|
|
} else {
|
|
|
|
if (!MO.isIdenticalTo(OMO))
|
|
|
|
return false;
|
|
|
|
if (Check == CheckKillDead && MO.isKill() != OMO.isKill())
|
|
|
|
return false;
|
|
|
|
}
|
2010-03-04 05:54:14 +08:00
|
|
|
}
|
2011-07-08 01:45:33 +08:00
|
|
|
// If DebugLoc does not match then two dbg.values are not identical.
|
|
|
|
if (isDebugValue())
|
2016-02-28 04:01:33 +08:00
|
|
|
if (getDebugLoc() && Other.getDebugLoc() &&
|
|
|
|
getDebugLoc() != Other.getDebugLoc())
|
2011-07-08 01:45:33 +08:00
|
|
|
return false;
|
2010-03-04 05:54:14 +08:00
|
|
|
return true;
|
2010-03-03 09:44:33 +08:00
|
|
|
}
|
|
|
|
|
2017-10-11 07:34:01 +08:00
|
|
|
const MachineFunction *MachineInstr::getMF() const {
|
|
|
|
return getParent()->getParent();
|
|
|
|
}
|
|
|
|
|
2006-04-18 05:35:41 +08:00
|
|
|
MachineInstr *MachineInstr::removeFromParent() {
|
|
|
|
assert(getParent() && "Not embedded in a basic block!");
|
2012-12-18 07:55:38 +08:00
|
|
|
return getParent()->remove(this);
|
2006-04-18 05:35:41 +08:00
|
|
|
}
|
|
|
|
|
2012-12-18 07:55:38 +08:00
|
|
|
MachineInstr *MachineInstr::removeFromBundle() {
|
|
|
|
assert(getParent() && "Not embedded in a basic block!");
|
|
|
|
return getParent()->remove_instr(this);
|
|
|
|
}
|
2006-04-18 05:35:41 +08:00
|
|
|
|
2008-07-08 07:14:23 +08:00
|
|
|
void MachineInstr::eraseFromParent() {
|
|
|
|
assert(getParent() && "Not embedded in a basic block!");
|
2012-12-18 07:55:38 +08:00
|
|
|
getParent()->erase(this);
|
2008-07-08 07:14:23 +08:00
|
|
|
}
|
|
|
|
|
2014-08-14 05:15:23 +08:00
|
|
|
void MachineInstr::eraseFromParentAndMarkDBGValuesForRemoval() {
|
|
|
|
assert(getParent() && "Not embedded in a basic block!");
|
|
|
|
MachineBasicBlock *MBB = getParent();
|
|
|
|
MachineFunction *MF = MBB->getParent();
|
|
|
|
assert(MF && "Not embedded in a function!");
|
|
|
|
|
|
|
|
MachineInstr *MI = (MachineInstr *)this;
|
|
|
|
MachineRegisterInfo &MRI = MF->getRegInfo();
|
|
|
|
|
2015-02-22 01:08:08 +08:00
|
|
|
for (const MachineOperand &MO : MI->operands()) {
|
2014-08-14 05:15:23 +08:00
|
|
|
if (!MO.isReg() || !MO.isDef())
|
|
|
|
continue;
|
|
|
|
unsigned Reg = MO.getReg();
|
|
|
|
if (!TargetRegisterInfo::isVirtualRegister(Reg))
|
|
|
|
continue;
|
|
|
|
MRI.markUsesInDebugValueAsUndef(Reg);
|
|
|
|
}
|
|
|
|
MI->eraseFromParent();
|
|
|
|
}
|
|
|
|
|
2012-12-18 07:55:38 +08:00
|
|
|
void MachineInstr::eraseFromBundle() {
|
|
|
|
assert(getParent() && "Not embedded in a basic block!");
|
|
|
|
getParent()->erase_instr(this);
|
|
|
|
}
|
2008-07-08 07:14:23 +08:00
|
|
|
|
2007-05-15 09:26:09 +08:00
|
|
|
/// getNumExplicitOperands - Returns the number of non-implicit operands.
|
|
|
|
///
|
|
|
|
unsigned MachineInstr::getNumExplicitOperands() const {
|
2011-06-29 03:10:37 +08:00
|
|
|
unsigned NumOperands = MCID->getNumOperands();
|
|
|
|
if (!MCID->isVariadic())
|
2007-05-15 09:26:09 +08:00
|
|
|
return NumOperands;
|
|
|
|
|
2009-04-16 01:59:11 +08:00
|
|
|
for (unsigned i = NumOperands, e = getNumOperands(); i != e; ++i) {
|
|
|
|
const MachineOperand &MO = getOperand(i);
|
2008-10-03 23:45:36 +08:00
|
|
|
if (!MO.isReg() || !MO.isImplicit())
|
2007-05-15 09:26:09 +08:00
|
|
|
NumOperands++;
|
|
|
|
}
|
|
|
|
return NumOperands;
|
|
|
|
}
|
|
|
|
|
2012-12-07 12:23:29 +08:00
|
|
|
void MachineInstr::bundleWithPred() {
|
|
|
|
assert(!isBundledWithPred() && "MI is already bundled with its predecessor");
|
|
|
|
setFlag(BundledPred);
|
2016-02-23 04:49:58 +08:00
|
|
|
MachineBasicBlock::instr_iterator Pred = getIterator();
|
|
|
|
--Pred;
|
2012-12-19 07:00:28 +08:00
|
|
|
assert(!Pred->isBundledWithSucc() && "Inconsistent bundle flags");
|
2012-12-07 12:23:29 +08:00
|
|
|
Pred->setFlag(BundledSucc);
|
|
|
|
}
|
|
|
|
|
|
|
|
void MachineInstr::bundleWithSucc() {
|
|
|
|
assert(!isBundledWithSucc() && "MI is already bundled with its successor");
|
|
|
|
setFlag(BundledSucc);
|
2016-02-23 04:49:58 +08:00
|
|
|
MachineBasicBlock::instr_iterator Succ = getIterator();
|
|
|
|
++Succ;
|
2012-12-19 07:00:28 +08:00
|
|
|
assert(!Succ->isBundledWithPred() && "Inconsistent bundle flags");
|
2012-12-07 12:23:29 +08:00
|
|
|
Succ->setFlag(BundledPred);
|
|
|
|
}
|
|
|
|
|
|
|
|
void MachineInstr::unbundleFromPred() {
|
|
|
|
assert(isBundledWithPred() && "MI isn't bundled with its predecessor");
|
|
|
|
clearFlag(BundledPred);
|
2016-02-23 04:49:58 +08:00
|
|
|
MachineBasicBlock::instr_iterator Pred = getIterator();
|
|
|
|
--Pred;
|
2012-12-19 07:00:28 +08:00
|
|
|
assert(Pred->isBundledWithSucc() && "Inconsistent bundle flags");
|
2012-12-07 12:23:29 +08:00
|
|
|
Pred->clearFlag(BundledSucc);
|
|
|
|
}
|
|
|
|
|
|
|
|
void MachineInstr::unbundleFromSucc() {
|
|
|
|
assert(isBundledWithSucc() && "MI isn't bundled with its successor");
|
|
|
|
clearFlag(BundledSucc);
|
2016-02-23 04:49:58 +08:00
|
|
|
MachineBasicBlock::instr_iterator Succ = getIterator();
|
|
|
|
++Succ;
|
2012-12-19 07:00:28 +08:00
|
|
|
assert(Succ->isBundledWithPred() && "Inconsistent bundle flags");
|
2012-12-07 12:23:29 +08:00
|
|
|
Succ->clearFlag(BundledPred);
|
|
|
|
}
|
|
|
|
|
2011-01-08 07:50:32 +08:00
|
|
|
bool MachineInstr::isStackAligningInlineAsm() const {
|
|
|
|
if (isInlineAsm()) {
|
|
|
|
unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
|
|
|
|
if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
return false;
|
|
|
|
}
|
2006-10-21 06:39:59 +08:00
|
|
|
|
2012-09-06 05:00:58 +08:00
|
|
|
InlineAsm::AsmDialect MachineInstr::getInlineAsmDialect() const {
|
|
|
|
assert(isInlineAsm() && "getInlineAsmDialect() only works for inline asms!");
|
|
|
|
unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
|
2012-09-06 06:40:13 +08:00
|
|
|
return InlineAsm::AsmDialect((ExtraInfo & InlineAsm::Extra_AsmDialect) != 0);
|
2012-09-06 05:00:58 +08:00
|
|
|
}
|
|
|
|
|
2011-10-13 07:37:33 +08:00
|
|
|
int MachineInstr::findInlineAsmFlagIdx(unsigned OpIdx,
|
|
|
|
unsigned *GroupNo) const {
|
|
|
|
assert(isInlineAsm() && "Expected an inline asm instruction");
|
|
|
|
assert(OpIdx < getNumOperands() && "OpIdx out of range");
|
|
|
|
|
|
|
|
// Ignore queries about the initial operands.
|
|
|
|
if (OpIdx < InlineAsm::MIOp_FirstOperand)
|
|
|
|
return -1;
|
|
|
|
|
|
|
|
unsigned Group = 0;
|
|
|
|
unsigned NumOps;
|
|
|
|
for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
|
|
|
|
i += NumOps) {
|
|
|
|
const MachineOperand &FlagMO = getOperand(i);
|
|
|
|
// If we reach the implicit register operands, stop looking.
|
|
|
|
if (!FlagMO.isImm())
|
|
|
|
return -1;
|
|
|
|
NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
|
|
|
|
if (i + NumOps > OpIdx) {
|
|
|
|
if (GroupNo)
|
|
|
|
*GroupNo = Group;
|
|
|
|
return i;
|
|
|
|
}
|
|
|
|
++Group;
|
|
|
|
}
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
2016-04-15 02:29:59 +08:00
|
|
|
const DILocalVariable *MachineInstr::getDebugVariable() const {
|
|
|
|
assert(isDebugValue() && "not a DBG_VALUE");
|
|
|
|
return cast<DILocalVariable>(getOperand(2).getMetadata());
|
|
|
|
}
|
|
|
|
|
|
|
|
const DIExpression *MachineInstr::getDebugExpression() const {
|
|
|
|
assert(isDebugValue() && "not a DBG_VALUE");
|
|
|
|
return cast<DIExpression>(getOperand(3).getMetadata());
|
|
|
|
}
|
|
|
|
|
2011-10-13 07:37:36 +08:00
|
|
|
const TargetRegisterClass*
|
|
|
|
MachineInstr::getRegClassConstraint(unsigned OpIdx,
|
|
|
|
const TargetInstrInfo *TII,
|
|
|
|
const TargetRegisterInfo *TRI) const {
|
2012-05-08 06:10:26 +08:00
|
|
|
assert(getParent() && "Can't have an MBB reference here!");
|
2017-10-11 07:50:49 +08:00
|
|
|
assert(getMF() && "Can't have an MF reference here!");
|
|
|
|
const MachineFunction &MF = *getMF();
|
2012-05-08 06:10:26 +08:00
|
|
|
|
2011-10-13 07:37:36 +08:00
|
|
|
// Most opcodes have fixed constraints in their MCInstrDesc.
|
|
|
|
if (!isInlineAsm())
|
2012-05-08 06:10:26 +08:00
|
|
|
return TII->getRegClass(getDesc(), OpIdx, TRI, MF);
|
2011-10-13 07:37:36 +08:00
|
|
|
|
|
|
|
if (!getOperand(OpIdx).isReg())
|
2014-04-14 08:51:57 +08:00
|
|
|
return nullptr;
|
2011-10-13 07:37:36 +08:00
|
|
|
|
|
|
|
// For tied uses on inline asm, get the constraint from the def.
|
|
|
|
unsigned DefIdx;
|
|
|
|
if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx))
|
|
|
|
OpIdx = DefIdx;
|
|
|
|
|
|
|
|
// Inline asm stores register class constraints in the flag word.
|
|
|
|
int FlagIdx = findInlineAsmFlagIdx(OpIdx);
|
|
|
|
if (FlagIdx < 0)
|
2014-04-14 08:51:57 +08:00
|
|
|
return nullptr;
|
2011-10-13 07:37:36 +08:00
|
|
|
|
|
|
|
unsigned Flag = getOperand(FlagIdx).getImm();
|
|
|
|
unsigned RCID;
|
2016-07-18 21:17:31 +08:00
|
|
|
if ((InlineAsm::getKind(Flag) == InlineAsm::Kind_RegUse ||
|
|
|
|
InlineAsm::getKind(Flag) == InlineAsm::Kind_RegDef ||
|
|
|
|
InlineAsm::getKind(Flag) == InlineAsm::Kind_RegDefEarlyClobber) &&
|
|
|
|
InlineAsm::hasRegClassConstraint(Flag, RCID))
|
2011-10-13 07:37:36 +08:00
|
|
|
return TRI->getRegClass(RCID);
|
|
|
|
|
|
|
|
// Assume that all registers in a memory operand are pointers.
|
|
|
|
if (InlineAsm::getKind(Flag) == InlineAsm::Kind_Mem)
|
2012-05-08 06:10:26 +08:00
|
|
|
return TRI->getPointerRegClass(MF);
|
2011-10-13 07:37:36 +08:00
|
|
|
|
2014-04-14 08:51:57 +08:00
|
|
|
return nullptr;
|
2011-10-13 07:37:36 +08:00
|
|
|
}
|
|
|
|
|
2014-01-03 06:47:22 +08:00
|
|
|
const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVReg(
|
|
|
|
unsigned Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII,
|
|
|
|
const TargetRegisterInfo *TRI, bool ExploreBundle) const {
|
|
|
|
// Check every operands inside the bundle if we have
|
|
|
|
// been asked to.
|
|
|
|
if (ExploreBundle)
|
2016-02-28 01:05:33 +08:00
|
|
|
for (ConstMIBundleOperands OpndIt(*this); OpndIt.isValid() && CurRC;
|
2014-01-03 06:47:22 +08:00
|
|
|
++OpndIt)
|
|
|
|
CurRC = OpndIt->getParent()->getRegClassConstraintEffectForVRegImpl(
|
|
|
|
OpndIt.getOperandNo(), Reg, CurRC, TII, TRI);
|
|
|
|
else
|
|
|
|
// Otherwise, just check the current operands.
|
2015-05-29 10:56:46 +08:00
|
|
|
for (unsigned i = 0, e = NumOperands; i < e && CurRC; ++i)
|
|
|
|
CurRC = getRegClassConstraintEffectForVRegImpl(i, Reg, CurRC, TII, TRI);
|
2014-01-03 06:47:22 +08:00
|
|
|
return CurRC;
|
|
|
|
}
|
|
|
|
|
|
|
|
const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVRegImpl(
|
|
|
|
unsigned OpIdx, unsigned Reg, const TargetRegisterClass *CurRC,
|
|
|
|
const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
|
|
|
|
assert(CurRC && "Invalid initial register class");
|
|
|
|
// Check if Reg is constrained by some of its use/def from MI.
|
|
|
|
const MachineOperand &MO = getOperand(OpIdx);
|
|
|
|
if (!MO.isReg() || MO.getReg() != Reg)
|
|
|
|
return CurRC;
|
|
|
|
// If yes, accumulate the constraints through the operand.
|
|
|
|
return getRegClassConstraintEffect(OpIdx, CurRC, TII, TRI);
|
|
|
|
}
|
|
|
|
|
|
|
|
const TargetRegisterClass *MachineInstr::getRegClassConstraintEffect(
|
|
|
|
unsigned OpIdx, const TargetRegisterClass *CurRC,
|
|
|
|
const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
|
|
|
|
const TargetRegisterClass *OpRC = getRegClassConstraint(OpIdx, TII, TRI);
|
|
|
|
const MachineOperand &MO = getOperand(OpIdx);
|
|
|
|
assert(MO.isReg() &&
|
|
|
|
"Cannot get register constraints for non-register operand");
|
|
|
|
assert(CurRC && "Invalid initial register class");
|
|
|
|
if (unsigned SubIdx = MO.getSubReg()) {
|
|
|
|
if (OpRC)
|
|
|
|
CurRC = TRI->getMatchingSuperRegClass(CurRC, OpRC, SubIdx);
|
|
|
|
else
|
|
|
|
CurRC = TRI->getSubClassWithSubReg(CurRC, SubIdx);
|
|
|
|
} else if (OpRC)
|
|
|
|
CurRC = TRI->getCommonSubClass(CurRC, OpRC);
|
|
|
|
return CurRC;
|
|
|
|
}
|
|
|
|
|
2013-01-10 02:28:16 +08:00
|
|
|
/// Return the number of instructions inside the MI bundle, not counting the
|
|
|
|
/// header instruction.
|
2011-12-14 10:11:42 +08:00
|
|
|
unsigned MachineInstr::getBundleSize() const {
|
2016-02-23 04:49:58 +08:00
|
|
|
MachineBasicBlock::const_instr_iterator I = getIterator();
|
2011-12-14 10:11:42 +08:00
|
|
|
unsigned Size = 0;
|
2016-02-19 06:09:30 +08:00
|
|
|
while (I->isBundledWithSucc()) {
|
|
|
|
++Size;
|
|
|
|
++I;
|
|
|
|
}
|
2011-12-14 10:11:42 +08:00
|
|
|
return Size;
|
|
|
|
}
|
|
|
|
|
2016-04-22 12:04:08 +08:00
|
|
|
/// Returns true if the MachineInstr has an implicit-use operand of exactly
|
|
|
|
/// the given register (not considering sub/super-registers).
|
|
|
|
bool MachineInstr::hasRegisterImplicitUseOperand(unsigned Reg) const {
|
|
|
|
for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
|
|
|
|
const MachineOperand &MO = getOperand(i);
|
|
|
|
if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.getReg() == Reg)
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2007-04-27 03:00:32 +08:00
|
|
|
/// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
|
2009-09-18 01:57:26 +08:00
|
|
|
/// the specific register or -1 if it is not found. It further tightens
|
2007-02-23 09:04:26 +08:00
|
|
|
/// the search criteria to a use that kills the register if isKill is true.
|
2016-10-11 17:09:21 +08:00
|
|
|
int MachineInstr::findRegisterUseOperandIdx(
|
|
|
|
unsigned Reg, bool isKill, const TargetRegisterInfo *TRI) const {
|
2006-12-06 16:27:42 +08:00
|
|
|
for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
|
2007-05-30 02:35:22 +08:00
|
|
|
const MachineOperand &MO = getOperand(i);
|
2008-10-03 23:45:36 +08:00
|
|
|
if (!MO.isReg() || !MO.isUse())
|
2008-03-05 08:59:57 +08:00
|
|
|
continue;
|
|
|
|
unsigned MOReg = MO.getReg();
|
|
|
|
if (!MOReg)
|
|
|
|
continue;
|
2016-10-11 17:09:21 +08:00
|
|
|
if (MOReg == Reg || (TRI && TargetRegisterInfo::isPhysicalRegister(MOReg) &&
|
|
|
|
TargetRegisterInfo::isPhysicalRegister(Reg) &&
|
|
|
|
TRI->isSubRegister(MOReg, Reg)))
|
2007-02-23 09:04:26 +08:00
|
|
|
if (!isKill || MO.isKill())
|
2007-03-27 06:37:45 +08:00
|
|
|
return i;
|
2007-02-20 05:49:54 +08:00
|
|
|
}
|
2007-03-27 06:37:45 +08:00
|
|
|
return -1;
|
2007-02-20 05:49:54 +08:00
|
|
|
}
|
2010-05-20 04:36:22 +08:00
|
|
|
|
2010-05-22 04:02:01 +08:00
|
|
|
/// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
|
|
|
|
/// indicating if this instruction reads or writes Reg. This also considers
|
|
|
|
/// partial defines.
|
|
|
|
std::pair<bool,bool>
|
|
|
|
MachineInstr::readsWritesVirtualRegister(unsigned Reg,
|
|
|
|
SmallVectorImpl<unsigned> *Ops) const {
|
|
|
|
bool PartDef = false; // Partial redefine.
|
|
|
|
bool FullDef = false; // Full define.
|
|
|
|
bool Use = false;
|
2010-05-20 04:36:22 +08:00
|
|
|
|
|
|
|
for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
|
|
|
|
const MachineOperand &MO = getOperand(i);
|
|
|
|
if (!MO.isReg() || MO.getReg() != Reg)
|
|
|
|
continue;
|
2010-05-22 04:02:01 +08:00
|
|
|
if (Ops)
|
|
|
|
Ops->push_back(i);
|
2010-05-20 04:36:22 +08:00
|
|
|
if (MO.isUse())
|
2010-05-22 04:02:01 +08:00
|
|
|
Use |= !MO.isUndef();
|
2011-08-19 08:30:17 +08:00
|
|
|
else if (MO.getSubReg() && !MO.isUndef())
|
|
|
|
// A partial <def,undef> doesn't count as reading the register.
|
2010-05-20 04:36:22 +08:00
|
|
|
PartDef = true;
|
|
|
|
else
|
|
|
|
FullDef = true;
|
|
|
|
}
|
2010-05-22 04:02:01 +08:00
|
|
|
// A partial redefine uses Reg unless there is also a full define.
|
|
|
|
return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef);
|
2010-05-20 04:36:22 +08:00
|
|
|
}
|
|
|
|
|
2008-03-05 08:59:57 +08:00
|
|
|
/// findRegisterDefOperandIdx() - Returns the operand index that is a def of
|
2008-05-06 08:20:10 +08:00
|
|
|
/// the specified register or -1 if it is not found. If isDead is true, defs
|
|
|
|
/// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
|
|
|
|
/// also checks if there is a def of a super-register.
|
2010-05-22 04:53:24 +08:00
|
|
|
int
|
|
|
|
MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead, bool Overlap,
|
|
|
|
const TargetRegisterInfo *TRI) const {
|
|
|
|
bool isPhys = TargetRegisterInfo::isPhysicalRegister(Reg);
|
2007-02-20 05:49:54 +08:00
|
|
|
for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
|
2008-03-05 08:59:57 +08:00
|
|
|
const MachineOperand &MO = getOperand(i);
|
2012-02-15 07:49:37 +08:00
|
|
|
// Accept regmask operands when Overlap is set.
|
|
|
|
// Ignore them when looking for a specific def operand (Overlap == false).
|
|
|
|
if (isPhys && Overlap && MO.isRegMask() && MO.clobbersPhysReg(Reg))
|
|
|
|
return i;
|
2008-10-03 23:45:36 +08:00
|
|
|
if (!MO.isReg() || !MO.isDef())
|
2008-03-05 08:59:57 +08:00
|
|
|
continue;
|
|
|
|
unsigned MOReg = MO.getReg();
|
2010-05-22 04:53:24 +08:00
|
|
|
bool Found = (MOReg == Reg);
|
|
|
|
if (!Found && TRI && isPhys &&
|
|
|
|
TargetRegisterInfo::isPhysicalRegister(MOReg)) {
|
|
|
|
if (Overlap)
|
|
|
|
Found = TRI->regsOverlap(MOReg, Reg);
|
|
|
|
else
|
|
|
|
Found = TRI->isSubRegister(MOReg, Reg);
|
|
|
|
}
|
|
|
|
if (Found && (!isDead || MO.isDead()))
|
|
|
|
return i;
|
2006-12-06 16:27:42 +08:00
|
|
|
}
|
2008-03-05 08:59:57 +08:00
|
|
|
return -1;
|
2006-12-06 16:27:42 +08:00
|
|
|
}
|
2007-05-15 09:26:09 +08:00
|
|
|
|
2007-05-30 02:35:22 +08:00
|
|
|
/// findFirstPredOperandIdx() - Find the index of the first operand in the
|
|
|
|
/// operand list that is used to represent the predicate. It returns -1 if
|
|
|
|
/// none is found.
|
|
|
|
int MachineInstr::findFirstPredOperandIdx() const {
|
2011-08-30 06:24:09 +08:00
|
|
|
// Don't call MCID.findFirstPredOperandIdx() because this variant
|
|
|
|
// is sometimes called on an instruction that's not yet complete, and
|
|
|
|
// so the number of operands is less than the MCID indicates. In
|
|
|
|
// particular, the PTX target does this.
|
2011-06-29 03:10:37 +08:00
|
|
|
const MCInstrDesc &MCID = getDesc();
|
|
|
|
if (MCID.isPredicable()) {
|
2007-05-15 09:26:09 +08:00
|
|
|
for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
|
2011-06-29 03:10:37 +08:00
|
|
|
if (MCID.OpInfo[i].isPredicate())
|
2007-05-30 02:35:22 +08:00
|
|
|
return i;
|
2007-05-15 09:26:09 +08:00
|
|
|
}
|
|
|
|
|
2007-05-30 02:35:22 +08:00
|
|
|
return -1;
|
2007-05-15 09:26:09 +08:00
|
|
|
}
|
2011-08-25 00:44:17 +08:00
|
|
|
|
2012-09-05 02:36:28 +08:00
|
|
|
// MachineOperand::TiedTo is 4 bits wide.
|
|
|
|
const unsigned TiedMax = 15;
|
|
|
|
|
|
|
|
/// tieOperands - Mark operands at DefIdx and UseIdx as tied to each other.
|
|
|
|
///
|
|
|
|
/// Use and def operands can be tied together, indicated by a non-zero TiedTo
|
|
|
|
/// field. TiedTo can have these values:
|
|
|
|
///
|
|
|
|
/// 0: Operand is not tied to anything.
|
|
|
|
/// 1 to TiedMax-1: Tied to getOperand(TiedTo-1).
|
|
|
|
/// TiedMax: Tied to an operand >= TiedMax-1.
|
|
|
|
///
|
|
|
|
/// The tied def must be one of the first TiedMax operands on a normal
|
|
|
|
/// instruction. INLINEASM instructions allow more tied defs.
|
|
|
|
///
|
2012-09-01 04:50:53 +08:00
|
|
|
void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) {
|
|
|
|
MachineOperand &DefMO = getOperand(DefIdx);
|
|
|
|
MachineOperand &UseMO = getOperand(UseIdx);
|
|
|
|
assert(DefMO.isDef() && "DefIdx must be a def operand");
|
|
|
|
assert(UseMO.isUse() && "UseIdx must be a use operand");
|
|
|
|
assert(!DefMO.isTied() && "Def is already tied to another use");
|
|
|
|
assert(!UseMO.isTied() && "Use is already tied to another def");
|
|
|
|
|
2012-09-05 02:36:28 +08:00
|
|
|
if (DefIdx < TiedMax)
|
|
|
|
UseMO.TiedTo = DefIdx + 1;
|
|
|
|
else {
|
|
|
|
// Inline asm can use the group descriptors to find tied operands, but on
|
|
|
|
// normal instruction, the tied def must be within the first TiedMax
|
|
|
|
// operands.
|
|
|
|
assert(isInlineAsm() && "DefIdx out of range");
|
|
|
|
UseMO.TiedTo = TiedMax;
|
|
|
|
}
|
|
|
|
|
|
|
|
// UseIdx can be out of range, we'll search for it in findTiedOperandIdx().
|
|
|
|
DefMO.TiedTo = std::min(UseIdx + 1, TiedMax);
|
2012-09-01 04:50:53 +08:00
|
|
|
}
|
|
|
|
|
2012-08-29 08:37:58 +08:00
|
|
|
/// Given the index of a tied register operand, find the operand it is tied to.
|
|
|
|
/// Defs are tied to uses and vice versa. Returns the index of the tied operand
|
|
|
|
/// which must exist.
|
|
|
|
unsigned MachineInstr::findTiedOperandIdx(unsigned OpIdx) const {
|
2012-09-05 02:36:28 +08:00
|
|
|
const MachineOperand &MO = getOperand(OpIdx);
|
|
|
|
assert(MO.isTied() && "Operand isn't tied");
|
|
|
|
|
|
|
|
// Normally TiedTo is in range.
|
|
|
|
if (MO.TiedTo < TiedMax)
|
|
|
|
return MO.TiedTo - 1;
|
|
|
|
|
|
|
|
// Uses on normal instructions can be out of range.
|
|
|
|
if (!isInlineAsm()) {
|
|
|
|
// Normal tied defs must be in the 0..TiedMax-1 range.
|
|
|
|
if (MO.isUse())
|
|
|
|
return TiedMax - 1;
|
|
|
|
// MO is a def. Search for the tied use.
|
|
|
|
for (unsigned i = TiedMax - 1, e = getNumOperands(); i != e; ++i) {
|
|
|
|
const MachineOperand &UseMO = getOperand(i);
|
|
|
|
if (UseMO.isReg() && UseMO.isUse() && UseMO.TiedTo == OpIdx + 1)
|
|
|
|
return i;
|
2012-08-29 08:37:58 +08:00
|
|
|
}
|
2012-09-05 02:36:28 +08:00
|
|
|
llvm_unreachable("Can't find tied use");
|
2012-08-29 08:37:58 +08:00
|
|
|
}
|
|
|
|
|
2012-09-05 02:36:28 +08:00
|
|
|
// Now deal with inline asm by parsing the operand group descriptor flags.
|
|
|
|
// Find the beginning of each operand group.
|
|
|
|
SmallVector<unsigned, 8> GroupIdx;
|
|
|
|
unsigned OpIdxGroup = ~0u;
|
|
|
|
unsigned NumOps;
|
|
|
|
for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
|
|
|
|
i += NumOps) {
|
|
|
|
const MachineOperand &FlagMO = getOperand(i);
|
|
|
|
assert(FlagMO.isImm() && "Invalid tied operand on inline asm");
|
|
|
|
unsigned CurGroup = GroupIdx.size();
|
|
|
|
GroupIdx.push_back(i);
|
|
|
|
NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
|
|
|
|
// OpIdx belongs to this operand group.
|
|
|
|
if (OpIdx > i && OpIdx < i + NumOps)
|
|
|
|
OpIdxGroup = CurGroup;
|
|
|
|
unsigned TiedGroup;
|
|
|
|
if (!InlineAsm::isUseOperandTiedToDef(FlagMO.getImm(), TiedGroup))
|
|
|
|
continue;
|
|
|
|
// Operands in this group are tied to operands in TiedGroup which must be
|
|
|
|
// earlier. Find the number of operands between the two groups.
|
|
|
|
unsigned Delta = i - GroupIdx[TiedGroup];
|
|
|
|
|
|
|
|
// OpIdx is a use tied to TiedGroup.
|
|
|
|
if (OpIdxGroup == CurGroup)
|
|
|
|
return OpIdx - Delta;
|
|
|
|
|
|
|
|
// OpIdx is a def tied to this use group.
|
|
|
|
if (OpIdxGroup == TiedGroup)
|
|
|
|
return OpIdx + Delta;
|
|
|
|
}
|
|
|
|
llvm_unreachable("Invalid tied operand on inline asm");
|
2012-08-29 08:37:58 +08:00
|
|
|
}
|
|
|
|
|
2010-05-14 04:34:42 +08:00
|
|
|
/// clearKillInfo - Clears kill flags on all operands.
|
|
|
|
///
|
|
|
|
void MachineInstr::clearKillInfo() {
|
2015-02-22 01:08:08 +08:00
|
|
|
for (MachineOperand &MO : operands()) {
|
2010-05-14 04:34:42 +08:00
|
|
|
if (MO.isReg() && MO.isUse())
|
|
|
|
MO.setIsKill(false);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2010-06-03 06:47:25 +08:00
|
|
|
void MachineInstr::substituteRegister(unsigned FromReg,
|
|
|
|
unsigned ToReg,
|
|
|
|
unsigned SubIdx,
|
|
|
|
const TargetRegisterInfo &RegInfo) {
|
|
|
|
if (TargetRegisterInfo::isPhysicalRegister(ToReg)) {
|
|
|
|
if (SubIdx)
|
|
|
|
ToReg = RegInfo.getSubReg(ToReg, SubIdx);
|
2015-02-22 01:08:08 +08:00
|
|
|
for (MachineOperand &MO : operands()) {
|
2010-06-03 06:47:25 +08:00
|
|
|
if (!MO.isReg() || MO.getReg() != FromReg)
|
|
|
|
continue;
|
|
|
|
MO.substPhysReg(ToReg, RegInfo);
|
|
|
|
}
|
|
|
|
} else {
|
2015-02-22 01:08:08 +08:00
|
|
|
for (MachineOperand &MO : operands()) {
|
2010-06-03 06:47:25 +08:00
|
|
|
if (!MO.isReg() || MO.getReg() != FromReg)
|
|
|
|
continue;
|
|
|
|
MO.substVirtReg(ToReg, SubIdx, RegInfo);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2008-07-03 17:09:37 +08:00
|
|
|
/// isSafeToMove - Return true if it is safe to move this instruction. If
|
|
|
|
/// SawStore is set to true, it means that there is a store (or call) between
|
|
|
|
/// the instruction's location and its intended destination.
|
2015-05-20 05:22:20 +08:00
|
|
|
bool MachineInstr::isSafeToMove(AliasAnalysis *AA, bool &SawStore) const {
|
2008-03-13 08:44:09 +08:00
|
|
|
// Ignore stuff that we obviously can't move.
|
2012-08-30 04:48:45 +08:00
|
|
|
//
|
|
|
|
// Treat volatile loads as stores. This is not strictly necessary for
|
2012-09-05 02:44:43 +08:00
|
|
|
// volatiles, but it is required for atomic loads. It is not allowed to move
|
2012-08-30 04:48:45 +08:00
|
|
|
// a load across an atomic load with Ordering > Monotonic.
|
|
|
|
if (mayStore() || isCall() ||
|
2012-08-30 05:19:21 +08:00
|
|
|
(mayLoad() && hasOrderedMemoryRef())) {
|
2008-03-13 08:44:09 +08:00
|
|
|
SawStore = true;
|
|
|
|
return false;
|
|
|
|
}
|
2011-01-08 05:08:26 +08:00
|
|
|
|
2014-03-07 14:08:31 +08:00
|
|
|
if (isPosition() || isDebugValue() || isTerminator() ||
|
|
|
|
hasUnmodeledSideEffects())
|
2008-03-13 08:44:09 +08:00
|
|
|
return false;
|
|
|
|
|
|
|
|
// See if this instruction does a load. If so, we have to guarantee that the
|
|
|
|
// loaded value doesn't change between the load and the its intended
|
|
|
|
// destination. The check for isInvariantLoad gives the targe the chance to
|
|
|
|
// classify the load as always returning a constant, e.g. a constant pool
|
|
|
|
// load.
|
2016-09-10 09:03:20 +08:00
|
|
|
if (mayLoad() && !isDereferenceableInvariantLoad(AA))
|
2008-03-13 08:44:09 +08:00
|
|
|
// Otherwise, this is a real load. If there is a store between the load and
|
2012-08-30 04:48:45 +08:00
|
|
|
// end of block, we can't move it.
|
|
|
|
return !SawStore;
|
2008-09-24 08:06:15 +08:00
|
|
|
|
2008-03-13 08:44:09 +08:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2017-03-10 07:33:36 +08:00
|
|
|
bool MachineInstr::mayAlias(AliasAnalysis *AA, MachineInstr &Other,
|
|
|
|
bool UseTBAA) {
|
2017-10-11 07:50:49 +08:00
|
|
|
const MachineFunction *MF = getMF();
|
2017-03-10 07:33:36 +08:00
|
|
|
const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
|
2017-08-30 22:57:12 +08:00
|
|
|
const MachineFrameInfo &MFI = MF->getFrameInfo();
|
2017-03-10 07:33:36 +08:00
|
|
|
|
|
|
|
// If neither instruction stores to memory, they can't alias in any
|
|
|
|
// meaningful way, even if they read from the same address.
|
|
|
|
if (!mayStore() && !Other.mayStore())
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// Let the target decide if memory accesses cannot possibly overlap.
|
|
|
|
if (TII->areMemAccessesTriviallyDisjoint(*this, Other, AA))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// FIXME: Need to handle multiple memory operands to support all targets.
|
|
|
|
if (!hasOneMemOperand() || !Other.hasOneMemOperand())
|
|
|
|
return true;
|
|
|
|
|
|
|
|
MachineMemOperand *MMOa = *memoperands_begin();
|
|
|
|
MachineMemOperand *MMOb = *Other.memoperands_begin();
|
|
|
|
|
|
|
|
// The following interface to AA is fashioned after DAGCombiner::isAlias
|
|
|
|
// and operates with MachineMemOperand offset with some important
|
|
|
|
// assumptions:
|
|
|
|
// - LLVM fundamentally assumes flat address spaces.
|
|
|
|
// - MachineOperand offset can *only* result from legalization and
|
|
|
|
// cannot affect queries other than the trivial case of overlap
|
|
|
|
// checking.
|
|
|
|
// - These offsets never wrap and never step outside
|
|
|
|
// of allocated objects.
|
|
|
|
// - There should never be any negative offsets here.
|
|
|
|
//
|
|
|
|
// FIXME: Modify API to hide this math from "user"
|
2017-08-30 22:57:12 +08:00
|
|
|
// Even before we go to AA we can reason locally about some
|
2017-03-10 07:33:36 +08:00
|
|
|
// memory objects. It can save compile time, and possibly catch some
|
|
|
|
// corner cases not currently covered.
|
|
|
|
|
2017-08-30 22:57:12 +08:00
|
|
|
int64_t OffsetA = MMOa->getOffset();
|
|
|
|
int64_t OffsetB = MMOb->getOffset();
|
|
|
|
|
|
|
|
int64_t MinOffset = std::min(OffsetA, OffsetB);
|
|
|
|
int64_t WidthA = MMOa->getSize();
|
|
|
|
int64_t WidthB = MMOb->getSize();
|
|
|
|
const Value *ValA = MMOa->getValue();
|
|
|
|
const Value *ValB = MMOb->getValue();
|
|
|
|
bool SameVal = (ValA && ValB && (ValA == ValB));
|
|
|
|
if (!SameVal) {
|
|
|
|
const PseudoSourceValue *PSVa = MMOa->getPseudoValue();
|
|
|
|
const PseudoSourceValue *PSVb = MMOb->getPseudoValue();
|
|
|
|
if (PSVa && ValB && !PSVa->mayAlias(&MFI))
|
|
|
|
return false;
|
|
|
|
if (PSVb && ValA && !PSVb->mayAlias(&MFI))
|
|
|
|
return false;
|
|
|
|
if (PSVa && PSVb && (PSVa == PSVb))
|
|
|
|
SameVal = true;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (SameVal) {
|
|
|
|
int64_t MaxOffset = std::max(OffsetA, OffsetB);
|
|
|
|
int64_t LowWidth = (MinOffset == OffsetA) ? WidthA : WidthB;
|
|
|
|
return (MinOffset + LowWidth > MaxOffset);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!AA)
|
|
|
|
return true;
|
|
|
|
|
|
|
|
if (!ValA || !ValB)
|
|
|
|
return true;
|
|
|
|
|
|
|
|
assert((OffsetA >= 0) && "Negative MachineMemOperand offset");
|
|
|
|
assert((OffsetB >= 0) && "Negative MachineMemOperand offset");
|
2017-03-10 07:33:36 +08:00
|
|
|
|
2017-08-30 22:57:12 +08:00
|
|
|
int64_t Overlapa = WidthA + OffsetA - MinOffset;
|
|
|
|
int64_t Overlapb = WidthB + OffsetB - MinOffset;
|
2017-03-10 07:33:36 +08:00
|
|
|
|
2017-08-30 22:57:12 +08:00
|
|
|
AliasResult AAResult = AA->alias(
|
|
|
|
MemoryLocation(ValA, Overlapa,
|
|
|
|
UseTBAA ? MMOa->getAAInfo() : AAMDNodes()),
|
|
|
|
MemoryLocation(ValB, Overlapb,
|
|
|
|
UseTBAA ? MMOb->getAAInfo() : AAMDNodes()));
|
2017-03-10 07:33:36 +08:00
|
|
|
|
|
|
|
return (AAResult != NoAlias);
|
|
|
|
}
|
|
|
|
|
2012-08-30 05:19:21 +08:00
|
|
|
/// hasOrderedMemoryRef - Return true if this instruction may have an ordered
|
|
|
|
/// or volatile memory reference, or if the information describing the memory
|
|
|
|
/// reference is not available. Return false if it is known to have no ordered
|
|
|
|
/// memory references.
|
|
|
|
bool MachineInstr::hasOrderedMemoryRef() const {
|
2008-09-24 08:06:15 +08:00
|
|
|
// An instruction known never to access memory won't have a volatile access.
|
2011-12-07 15:15:52 +08:00
|
|
|
if (!mayStore() &&
|
|
|
|
!mayLoad() &&
|
|
|
|
!isCall() &&
|
2011-01-08 07:50:32 +08:00
|
|
|
!hasUnmodeledSideEffects())
|
2008-09-24 08:06:15 +08:00
|
|
|
return false;
|
|
|
|
|
|
|
|
// Otherwise, if the instruction has no memory reference information,
|
|
|
|
// conservatively assume it wasn't preserved.
|
|
|
|
if (memoperands_empty())
|
|
|
|
return true;
|
2011-08-25 00:44:17 +08:00
|
|
|
|
2016-07-14 06:35:19 +08:00
|
|
|
// Check if any of our memory operands are ordered.
|
2017-05-31 09:10:10 +08:00
|
|
|
return llvm::any_of(memoperands(), [](const MachineMemOperand *MMO) {
|
2016-07-14 06:35:19 +08:00
|
|
|
return !MMO->isUnordered();
|
|
|
|
});
|
2008-09-24 08:06:15 +08:00
|
|
|
}
|
|
|
|
|
2016-09-10 09:03:20 +08:00
|
|
|
/// isDereferenceableInvariantLoad - Return true if this instruction will never
|
|
|
|
/// trap and is loading from a location whose value is invariant across a run of
|
|
|
|
/// this function.
|
|
|
|
bool MachineInstr::isDereferenceableInvariantLoad(AliasAnalysis *AA) const {
|
2009-10-08 01:38:06 +08:00
|
|
|
// If the instruction doesn't load at all, it isn't an invariant load.
|
2011-12-07 15:15:52 +08:00
|
|
|
if (!mayLoad())
|
2009-10-08 01:38:06 +08:00
|
|
|
return false;
|
|
|
|
|
|
|
|
// If the instruction has lost its memoperands, conservatively assume that
|
|
|
|
// it may not be an invariant load.
|
|
|
|
if (memoperands_empty())
|
|
|
|
return false;
|
|
|
|
|
2016-07-29 02:40:00 +08:00
|
|
|
const MachineFrameInfo &MFI = getParent()->getParent()->getFrameInfo();
|
2009-10-08 01:38:06 +08:00
|
|
|
|
2016-07-14 06:35:19 +08:00
|
|
|
for (MachineMemOperand *MMO : memoperands()) {
|
|
|
|
if (MMO->isVolatile()) return false;
|
|
|
|
if (MMO->isStore()) return false;
|
[CodeGen] Split out the notions of MI invariance and MI dereferenceability.
Summary:
An IR load can be invariant, dereferenceable, neither, or both. But
currently, MI's notion of invariance is IR-invariant &&
IR-dereferenceable.
This patch splits up the notions of invariance and dereferenceability at
the MI level. It's NFC, so adds some probably-unnecessary
"is-dereferenceable" checks, which we can remove later if desired.
Reviewers: chandlerc, tstellarAMD
Subscribers: jholewinski, arsenm, nemanjai, llvm-commits
Differential Revision: https://reviews.llvm.org/D23371
llvm-svn: 281151
2016-09-11 09:38:58 +08:00
|
|
|
if (MMO->isInvariant() && MMO->isDereferenceable())
|
|
|
|
continue;
|
2014-04-15 15:22:52 +08:00
|
|
|
|
|
|
|
// A load from a constant PseudoSourceValue is invariant.
|
2016-07-14 06:35:19 +08:00
|
|
|
if (const PseudoSourceValue *PSV = MMO->getPseudoValue())
|
2016-07-29 02:40:00 +08:00
|
|
|
if (PSV->isConstant(&MFI))
|
2014-04-15 15:22:52 +08:00
|
|
|
continue;
|
|
|
|
|
2016-07-14 06:35:19 +08:00
|
|
|
if (const Value *V = MMO->getValue()) {
|
2009-10-08 01:38:06 +08:00
|
|
|
// If we have an AliasAnalysis, ask it whether the memory is constant.
|
2015-06-17 15:18:54 +08:00
|
|
|
if (AA &&
|
|
|
|
AA->pointsToConstantMemory(
|
2016-07-14 06:35:19 +08:00
|
|
|
MemoryLocation(V, MMO->getSize(), MMO->getAAInfo())))
|
2009-10-08 01:38:06 +08:00
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Otherwise assume conservatively.
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Everything checks out.
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2009-12-03 10:31:43 +08:00
|
|
|
/// isConstantValuePHI - If the specified instruction is a PHI that always
|
|
|
|
/// merges together the same virtual register, return the register, otherwise
|
|
|
|
/// return 0.
|
|
|
|
unsigned MachineInstr::isConstantValuePHI() const {
|
2010-02-10 03:54:29 +08:00
|
|
|
if (!isPHI())
|
2009-12-03 10:31:43 +08:00
|
|
|
return 0;
|
2009-12-08 07:10:34 +08:00
|
|
|
assert(getNumOperands() >= 3 &&
|
|
|
|
"It's illegal to have a PHI without source operands");
|
2009-12-03 10:31:43 +08:00
|
|
|
|
|
|
|
unsigned Reg = getOperand(1).getReg();
|
|
|
|
for (unsigned i = 3, e = getNumOperands(); i < e; i += 2)
|
|
|
|
if (getOperand(i).getReg() != Reg)
|
|
|
|
return 0;
|
|
|
|
return Reg;
|
|
|
|
}
|
|
|
|
|
2011-01-08 07:50:32 +08:00
|
|
|
bool MachineInstr::hasUnmodeledSideEffects() const {
|
2011-12-07 15:15:52 +08:00
|
|
|
if (hasProperty(MCID::UnmodeledSideEffects))
|
2011-01-08 07:50:32 +08:00
|
|
|
return true;
|
|
|
|
if (isInlineAsm()) {
|
|
|
|
unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
|
|
|
|
if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2015-08-12 18:14:58 +08:00
|
|
|
bool MachineInstr::isLoadFoldBarrier() const {
|
|
|
|
return mayStore() || isCall() || hasUnmodeledSideEffects();
|
|
|
|
}
|
|
|
|
|
2010-04-09 04:02:37 +08:00
|
|
|
/// allDefsAreDead - Return true if all the defs of this instruction are dead.
|
|
|
|
///
|
|
|
|
bool MachineInstr::allDefsAreDead() const {
|
2015-02-22 01:08:08 +08:00
|
|
|
for (const MachineOperand &MO : operands()) {
|
2010-04-09 04:02:37 +08:00
|
|
|
if (!MO.isReg() || MO.isUse())
|
|
|
|
continue;
|
|
|
|
if (!MO.isDead())
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2010-10-23 05:49:09 +08:00
|
|
|
/// copyImplicitOps - Copy implicit register operands from specified
|
|
|
|
/// instruction to this instruction.
|
2012-12-21 06:54:02 +08:00
|
|
|
void MachineInstr::copyImplicitOps(MachineFunction &MF,
|
2016-02-28 04:01:33 +08:00
|
|
|
const MachineInstr &MI) {
|
|
|
|
for (unsigned i = MI.getDesc().getNumOperands(), e = MI.getNumOperands();
|
2010-10-23 05:49:09 +08:00
|
|
|
i != e; ++i) {
|
2016-02-28 04:01:33 +08:00
|
|
|
const MachineOperand &MO = MI.getOperand(i);
|
2014-03-17 09:22:54 +08:00
|
|
|
if ((MO.isReg() && MO.isImplicit()) || MO.isRegMask())
|
2012-12-21 06:54:02 +08:00
|
|
|
addOperand(MF, MO);
|
2010-10-23 05:49:09 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-10-13 00:16:06 +08:00
|
|
|
#ifdef LLVM_ENABLE_DUMP
|
2017-01-30 02:20:42 +08:00
|
|
|
LLVM_DUMP_METHOD void MachineInstr::dump() const {
|
2016-12-21 09:41:12 +08:00
|
|
|
dbgs() << " ";
|
2017-01-30 02:20:42 +08:00
|
|
|
print(dbgs());
|
2008-10-10 09:43:55 +08:00
|
|
|
}
|
2017-01-28 10:02:38 +08:00
|
|
|
#endif
|
2008-10-10 09:43:55 +08:00
|
|
|
|
2017-02-24 03:17:31 +08:00
|
|
|
void MachineInstr::print(raw_ostream &OS, bool SkipOpers, bool SkipDebugLoc,
|
2016-12-21 09:41:12 +08:00
|
|
|
const TargetInstrInfo *TII) const {
|
2015-06-27 07:18:44 +08:00
|
|
|
const Module *M = nullptr;
|
|
|
|
if (const MachineBasicBlock *MBB = getParent())
|
|
|
|
if (const MachineFunction *MF = MBB->getParent())
|
|
|
|
M = MF->getFunction()->getParent();
|
|
|
|
|
|
|
|
ModuleSlotTracker MST(M);
|
2017-02-24 03:17:31 +08:00
|
|
|
print(OS, MST, SkipOpers, SkipDebugLoc, TII);
|
2015-06-27 06:06:47 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST,
|
2017-02-24 03:17:31 +08:00
|
|
|
bool SkipOpers, bool SkipDebugLoc,
|
|
|
|
const TargetInstrInfo *TII) const {
|
2015-02-27 08:11:34 +08:00
|
|
|
// We can be a bit tidier if we know the MachineFunction.
|
2014-04-14 08:51:57 +08:00
|
|
|
const MachineFunction *MF = nullptr;
|
2015-02-27 08:11:34 +08:00
|
|
|
const TargetRegisterInfo *TRI = nullptr;
|
2014-04-14 08:51:57 +08:00
|
|
|
const MachineRegisterInfo *MRI = nullptr;
|
2016-07-30 04:32:59 +08:00
|
|
|
const TargetIntrinsicInfo *IntrinsicInfo = nullptr;
|
|
|
|
|
Print "..." instead of all the uninteresting register clobbers on call
instructions. This makes CodeGen dumps significantly less noisy.
Example before:
BL <ga:@bar>, %R0<imp-def>, %R1<imp-def,dead>, %R2<imp-def,dead>, %R3<imp-def,dead>, %R12<imp-def,dead>, %LR<imp-def,dead>, %D0<imp-def,dead>, %D1<imp-def,dead>, %D2<imp-def,dead>, %D3<imp-def,dead>, %D4<imp-def,dead>, %D5<imp-def,dead>, %D6<imp-def,dead>, %D7<imp-def,dead>, %D16<imp-def,dead>, %D17<imp-def,dead>, %D18<imp-def,dead>, %D19<imp-def,dead>, %D20<imp-def,dead>, %D21<imp-def,dead>, %D22<imp-def,dead>, %D23<imp-def,dead>, %D24<imp-def,dead>, %D25<imp-def,dead>, %D26<imp-def,dead>, %D27<imp-def,dead>, %D28<imp-def,dead>, %D29<imp-def,dead>, %D30<imp-def,dead>, %D31<imp-def,dead>, %CPSR<imp-def,dead>, %FPSCR<imp-def,dead>
Same example after:
BL <ga:@bar>, %R0<imp-def>, %R1<imp-def,dead>, %LR<imp-def,dead>, %CPSR<imp-def,dead>, ...
llvm-svn: 86583
2009-11-10 03:38:45 +08:00
|
|
|
if (const MachineBasicBlock *MBB = getParent()) {
|
|
|
|
MF = MBB->getParent();
|
2015-02-27 08:11:34 +08:00
|
|
|
if (MF) {
|
2010-07-29 02:35:46 +08:00
|
|
|
MRI = &MF->getRegInfo();
|
2015-02-27 08:11:34 +08:00
|
|
|
TRI = MF->getSubtarget().getRegisterInfo();
|
2016-12-21 09:41:12 +08:00
|
|
|
if (!TII)
|
|
|
|
TII = MF->getSubtarget().getInstrInfo();
|
2016-07-30 04:32:59 +08:00
|
|
|
IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
|
2015-02-27 08:11:34 +08:00
|
|
|
}
|
Print "..." instead of all the uninteresting register clobbers on call
instructions. This makes CodeGen dumps significantly less noisy.
Example before:
BL <ga:@bar>, %R0<imp-def>, %R1<imp-def,dead>, %R2<imp-def,dead>, %R3<imp-def,dead>, %R12<imp-def,dead>, %LR<imp-def,dead>, %D0<imp-def,dead>, %D1<imp-def,dead>, %D2<imp-def,dead>, %D3<imp-def,dead>, %D4<imp-def,dead>, %D5<imp-def,dead>, %D6<imp-def,dead>, %D7<imp-def,dead>, %D16<imp-def,dead>, %D17<imp-def,dead>, %D18<imp-def,dead>, %D19<imp-def,dead>, %D20<imp-def,dead>, %D21<imp-def,dead>, %D22<imp-def,dead>, %D23<imp-def,dead>, %D24<imp-def,dead>, %D25<imp-def,dead>, %D26<imp-def,dead>, %D27<imp-def,dead>, %D28<imp-def,dead>, %D29<imp-def,dead>, %D30<imp-def,dead>, %D31<imp-def,dead>, %CPSR<imp-def,dead>, %FPSCR<imp-def,dead>
Same example after:
BL <ga:@bar>, %R0<imp-def>, %R1<imp-def,dead>, %LR<imp-def,dead>, %CPSR<imp-def,dead>, ...
llvm-svn: 86583
2009-11-10 03:38:45 +08:00
|
|
|
}
|
2009-11-01 04:19:03 +08:00
|
|
|
|
2010-07-29 02:35:46 +08:00
|
|
|
// Save a list of virtual registers.
|
|
|
|
SmallVector<unsigned, 8> VirtRegs;
|
|
|
|
|
2009-11-01 04:19:03 +08:00
|
|
|
// Print explicitly defined operands on the left of an assignment syntax.
|
Print "..." instead of all the uninteresting register clobbers on call
instructions. This makes CodeGen dumps significantly less noisy.
Example before:
BL <ga:@bar>, %R0<imp-def>, %R1<imp-def,dead>, %R2<imp-def,dead>, %R3<imp-def,dead>, %R12<imp-def,dead>, %LR<imp-def,dead>, %D0<imp-def,dead>, %D1<imp-def,dead>, %D2<imp-def,dead>, %D3<imp-def,dead>, %D4<imp-def,dead>, %D5<imp-def,dead>, %D6<imp-def,dead>, %D7<imp-def,dead>, %D16<imp-def,dead>, %D17<imp-def,dead>, %D18<imp-def,dead>, %D19<imp-def,dead>, %D20<imp-def,dead>, %D21<imp-def,dead>, %D22<imp-def,dead>, %D23<imp-def,dead>, %D24<imp-def,dead>, %D25<imp-def,dead>, %D26<imp-def,dead>, %D27<imp-def,dead>, %D28<imp-def,dead>, %D29<imp-def,dead>, %D30<imp-def,dead>, %D31<imp-def,dead>, %CPSR<imp-def,dead>, %FPSCR<imp-def,dead>
Same example after:
BL <ga:@bar>, %R0<imp-def>, %R1<imp-def,dead>, %LR<imp-def,dead>, %CPSR<imp-def,dead>, ...
llvm-svn: 86583
2009-11-10 03:38:45 +08:00
|
|
|
unsigned StartOp = 0, e = getNumOperands();
|
2009-11-01 04:19:03 +08:00
|
|
|
for (; StartOp < e && getOperand(StartOp).isReg() &&
|
|
|
|
getOperand(StartOp).isDef() &&
|
|
|
|
!getOperand(StartOp).isImplicit();
|
|
|
|
++StartOp) {
|
|
|
|
if (StartOp != 0) OS << ", ";
|
2016-07-30 04:32:59 +08:00
|
|
|
getOperand(StartOp).print(OS, MST, TRI, IntrinsicInfo);
|
2010-07-29 02:35:46 +08:00
|
|
|
unsigned Reg = getOperand(StartOp).getReg();
|
2016-02-11 07:43:48 +08:00
|
|
|
if (TargetRegisterInfo::isVirtualRegister(Reg)) {
|
2010-07-29 02:35:46 +08:00
|
|
|
VirtRegs.push_back(Reg);
|
2016-09-09 19:46:34 +08:00
|
|
|
LLT Ty = MRI ? MRI->getType(Reg) : LLT{};
|
|
|
|
if (Ty.isValid())
|
|
|
|
OS << '(' << Ty << ')';
|
2016-02-11 07:43:48 +08:00
|
|
|
}
|
2002-10-30 09:55:38 +08:00
|
|
|
}
|
2004-06-25 08:13:11 +08:00
|
|
|
|
2009-11-01 04:19:03 +08:00
|
|
|
if (StartOp != 0)
|
|
|
|
OS << " = ";
|
|
|
|
|
|
|
|
// Print the opcode name.
|
2015-02-27 08:11:34 +08:00
|
|
|
if (TII)
|
|
|
|
OS << TII->getName(getOpcode());
|
2012-02-10 21:18:44 +08:00
|
|
|
else
|
|
|
|
OS << "UNKNOWN";
|
2005-04-22 06:36:52 +08:00
|
|
|
|
2013-01-25 15:45:25 +08:00
|
|
|
if (SkipOpers)
|
|
|
|
return;
|
|
|
|
|
2009-11-01 04:19:03 +08:00
|
|
|
// Print the rest of the operands.
|
Print "..." instead of all the uninteresting register clobbers on call
instructions. This makes CodeGen dumps significantly less noisy.
Example before:
BL <ga:@bar>, %R0<imp-def>, %R1<imp-def,dead>, %R2<imp-def,dead>, %R3<imp-def,dead>, %R12<imp-def,dead>, %LR<imp-def,dead>, %D0<imp-def,dead>, %D1<imp-def,dead>, %D2<imp-def,dead>, %D3<imp-def,dead>, %D4<imp-def,dead>, %D5<imp-def,dead>, %D6<imp-def,dead>, %D7<imp-def,dead>, %D16<imp-def,dead>, %D17<imp-def,dead>, %D18<imp-def,dead>, %D19<imp-def,dead>, %D20<imp-def,dead>, %D21<imp-def,dead>, %D22<imp-def,dead>, %D23<imp-def,dead>, %D24<imp-def,dead>, %D25<imp-def,dead>, %D26<imp-def,dead>, %D27<imp-def,dead>, %D28<imp-def,dead>, %D29<imp-def,dead>, %D30<imp-def,dead>, %D31<imp-def,dead>, %CPSR<imp-def,dead>, %FPSCR<imp-def,dead>
Same example after:
BL <ga:@bar>, %R0<imp-def>, %R1<imp-def,dead>, %LR<imp-def,dead>, %CPSR<imp-def,dead>, ...
llvm-svn: 86583
2009-11-10 03:38:45 +08:00
|
|
|
bool FirstOp = true;
|
Decode and pretty print inline asm operand descriptors.
The INLINEASM MachineInstrs have an immediate operand describing each
original inline asm operand. Decode the bits in MachineInstr::print() so
it is easier to read:
INLINEASM <es:rorq $1,$0>, $0:[regdef], %vreg0<def>, %vreg1<def>, $1:[imm], 1, $2:[reguse] [tiedto:$0], %vreg2, %vreg3, $3:[regdef-ec], %EFLAGS<earlyclobber,imp-def>
llvm-svn: 133901
2011-06-27 12:08:29 +08:00
|
|
|
unsigned AsmDescOp = ~0u;
|
|
|
|
unsigned AsmOpCount = 0;
|
2011-01-08 07:50:32 +08:00
|
|
|
|
2011-09-29 08:40:51 +08:00
|
|
|
if (isInlineAsm() && e >= InlineAsm::MIOp_FirstOperand) {
|
2011-01-08 07:50:32 +08:00
|
|
|
// Print asm string.
|
|
|
|
OS << " ";
|
2015-06-27 06:06:47 +08:00
|
|
|
getOperand(InlineAsm::MIOp_AsmString).print(OS, MST, TRI);
|
2011-01-08 07:50:32 +08:00
|
|
|
|
2013-01-12 02:12:39 +08:00
|
|
|
// Print HasSideEffects, MayLoad, MayStore, IsAlignStack
|
2011-01-08 07:50:32 +08:00
|
|
|
unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
|
|
|
|
if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
|
|
|
|
OS << " [sideeffect]";
|
2013-01-12 02:12:39 +08:00
|
|
|
if (ExtraInfo & InlineAsm::Extra_MayLoad)
|
|
|
|
OS << " [mayload]";
|
|
|
|
if (ExtraInfo & InlineAsm::Extra_MayStore)
|
|
|
|
OS << " [maystore]";
|
2016-06-23 02:51:08 +08:00
|
|
|
if (ExtraInfo & InlineAsm::Extra_IsConvergent)
|
|
|
|
OS << " [isconvergent]";
|
2011-01-08 07:50:32 +08:00
|
|
|
if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
|
|
|
|
OS << " [alignstack]";
|
2012-09-06 06:17:43 +08:00
|
|
|
if (getInlineAsmDialect() == InlineAsm::AD_ATT)
|
2012-09-06 05:00:58 +08:00
|
|
|
OS << " [attdialect]";
|
2012-09-06 06:17:43 +08:00
|
|
|
if (getInlineAsmDialect() == InlineAsm::AD_Intel)
|
2012-09-06 05:00:58 +08:00
|
|
|
OS << " [inteldialect]";
|
2011-01-08 07:50:32 +08:00
|
|
|
|
Decode and pretty print inline asm operand descriptors.
The INLINEASM MachineInstrs have an immediate operand describing each
original inline asm operand. Decode the bits in MachineInstr::print() so
it is easier to read:
INLINEASM <es:rorq $1,$0>, $0:[regdef], %vreg0<def>, %vreg1<def>, $1:[imm], 1, $2:[reguse] [tiedto:$0], %vreg2, %vreg3, $3:[regdef-ec], %EFLAGS<earlyclobber,imp-def>
llvm-svn: 133901
2011-06-27 12:08:29 +08:00
|
|
|
StartOp = AsmDescOp = InlineAsm::MIOp_FirstOperand;
|
2011-01-08 07:50:32 +08:00
|
|
|
FirstOp = false;
|
|
|
|
}
|
|
|
|
|
2002-10-30 09:55:38 +08:00
|
|
|
for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
|
Print "..." instead of all the uninteresting register clobbers on call
instructions. This makes CodeGen dumps significantly less noisy.
Example before:
BL <ga:@bar>, %R0<imp-def>, %R1<imp-def,dead>, %R2<imp-def,dead>, %R3<imp-def,dead>, %R12<imp-def,dead>, %LR<imp-def,dead>, %D0<imp-def,dead>, %D1<imp-def,dead>, %D2<imp-def,dead>, %D3<imp-def,dead>, %D4<imp-def,dead>, %D5<imp-def,dead>, %D6<imp-def,dead>, %D7<imp-def,dead>, %D16<imp-def,dead>, %D17<imp-def,dead>, %D18<imp-def,dead>, %D19<imp-def,dead>, %D20<imp-def,dead>, %D21<imp-def,dead>, %D22<imp-def,dead>, %D23<imp-def,dead>, %D24<imp-def,dead>, %D25<imp-def,dead>, %D26<imp-def,dead>, %D27<imp-def,dead>, %D28<imp-def,dead>, %D29<imp-def,dead>, %D30<imp-def,dead>, %D31<imp-def,dead>, %CPSR<imp-def,dead>, %FPSCR<imp-def,dead>
Same example after:
BL <ga:@bar>, %R0<imp-def>, %R1<imp-def,dead>, %LR<imp-def,dead>, %CPSR<imp-def,dead>, ...
llvm-svn: 86583
2009-11-10 03:38:45 +08:00
|
|
|
const MachineOperand &MO = getOperand(i);
|
|
|
|
|
2011-01-10 10:58:51 +08:00
|
|
|
if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg()))
|
2010-07-29 02:35:46 +08:00
|
|
|
VirtRegs.push_back(MO.getReg());
|
|
|
|
|
Print "..." instead of all the uninteresting register clobbers on call
instructions. This makes CodeGen dumps significantly less noisy.
Example before:
BL <ga:@bar>, %R0<imp-def>, %R1<imp-def,dead>, %R2<imp-def,dead>, %R3<imp-def,dead>, %R12<imp-def,dead>, %LR<imp-def,dead>, %D0<imp-def,dead>, %D1<imp-def,dead>, %D2<imp-def,dead>, %D3<imp-def,dead>, %D4<imp-def,dead>, %D5<imp-def,dead>, %D6<imp-def,dead>, %D7<imp-def,dead>, %D16<imp-def,dead>, %D17<imp-def,dead>, %D18<imp-def,dead>, %D19<imp-def,dead>, %D20<imp-def,dead>, %D21<imp-def,dead>, %D22<imp-def,dead>, %D23<imp-def,dead>, %D24<imp-def,dead>, %D25<imp-def,dead>, %D26<imp-def,dead>, %D27<imp-def,dead>, %D28<imp-def,dead>, %D29<imp-def,dead>, %D30<imp-def,dead>, %D31<imp-def,dead>, %CPSR<imp-def,dead>, %FPSCR<imp-def,dead>
Same example after:
BL <ga:@bar>, %R0<imp-def>, %R1<imp-def,dead>, %LR<imp-def,dead>, %CPSR<imp-def,dead>, ...
llvm-svn: 86583
2009-11-10 03:38:45 +08:00
|
|
|
if (FirstOp) FirstOp = false; else OS << ",";
|
2002-10-30 09:55:38 +08:00
|
|
|
OS << " ";
|
2010-01-20 06:08:34 +08:00
|
|
|
if (i < getDesc().NumOperands) {
|
2011-06-29 03:10:37 +08:00
|
|
|
const MCOperandInfo &MCOI = getDesc().OpInfo[i];
|
|
|
|
if (MCOI.isPredicate())
|
2010-01-20 06:08:34 +08:00
|
|
|
OS << "pred:";
|
2011-06-29 03:10:37 +08:00
|
|
|
if (MCOI.isOptionalDef())
|
2010-01-20 06:08:34 +08:00
|
|
|
OS << "opt:";
|
|
|
|
}
|
2010-04-29 04:03:13 +08:00
|
|
|
if (isDebugValue() && MO.isMetadata()) {
|
|
|
|
// Pretty print DBG_VALUE instructions.
|
2015-04-30 00:38:44 +08:00
|
|
|
auto *DIV = dyn_cast<DILocalVariable>(MO.getMetadata());
|
2015-04-14 10:22:36 +08:00
|
|
|
if (DIV && !DIV->getName().empty())
|
|
|
|
OS << "!\"" << DIV->getName() << '\"';
|
2010-04-29 04:03:13 +08:00
|
|
|
else
|
2015-06-27 06:06:47 +08:00
|
|
|
MO.print(OS, MST, TRI);
|
2017-01-10 05:38:10 +08:00
|
|
|
} else if (TRI && (isInsertSubreg() || isRegSequence() ||
|
|
|
|
(isSubregToReg() && i == 3)) && MO.isImm()) {
|
2015-02-27 08:11:34 +08:00
|
|
|
OS << TRI->getSubRegIndexName(MO.getImm());
|
Decode and pretty print inline asm operand descriptors.
The INLINEASM MachineInstrs have an immediate operand describing each
original inline asm operand. Decode the bits in MachineInstr::print() so
it is easier to read:
INLINEASM <es:rorq $1,$0>, $0:[regdef], %vreg0<def>, %vreg1<def>, $1:[imm], 1, $2:[reguse] [tiedto:$0], %vreg2, %vreg3, $3:[regdef-ec], %EFLAGS<earlyclobber,imp-def>
llvm-svn: 133901
2011-06-27 12:08:29 +08:00
|
|
|
} else if (i == AsmDescOp && MO.isImm()) {
|
|
|
|
// Pretty print the inline asm operand descriptor.
|
|
|
|
OS << '$' << AsmOpCount++;
|
|
|
|
unsigned Flag = MO.getImm();
|
|
|
|
switch (InlineAsm::getKind(Flag)) {
|
2011-10-13 07:37:29 +08:00
|
|
|
case InlineAsm::Kind_RegUse: OS << ":[reguse"; break;
|
|
|
|
case InlineAsm::Kind_RegDef: OS << ":[regdef"; break;
|
|
|
|
case InlineAsm::Kind_RegDefEarlyClobber: OS << ":[regdef-ec"; break;
|
|
|
|
case InlineAsm::Kind_Clobber: OS << ":[clobber"; break;
|
|
|
|
case InlineAsm::Kind_Imm: OS << ":[imm"; break;
|
|
|
|
case InlineAsm::Kind_Mem: OS << ":[mem"; break;
|
|
|
|
default: OS << ":[??" << InlineAsm::getKind(Flag); break;
|
Decode and pretty print inline asm operand descriptors.
The INLINEASM MachineInstrs have an immediate operand describing each
original inline asm operand. Decode the bits in MachineInstr::print() so
it is easier to read:
INLINEASM <es:rorq $1,$0>, $0:[regdef], %vreg0<def>, %vreg1<def>, $1:[imm], 1, $2:[reguse] [tiedto:$0], %vreg2, %vreg3, $3:[regdef-ec], %EFLAGS<earlyclobber,imp-def>
llvm-svn: 133901
2011-06-27 12:08:29 +08:00
|
|
|
}
|
|
|
|
|
2011-10-13 07:37:29 +08:00
|
|
|
unsigned RCID = 0;
|
2016-07-18 21:17:31 +08:00
|
|
|
if (!InlineAsm::isImmKind(Flag) && !InlineAsm::isMemKind(Flag) &&
|
|
|
|
InlineAsm::hasRegClassConstraint(Flag, RCID)) {
|
2015-02-27 08:11:34 +08:00
|
|
|
if (TRI) {
|
|
|
|
OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID));
|
2014-11-17 13:50:14 +08:00
|
|
|
} else
|
2011-10-13 07:37:29 +08:00
|
|
|
OS << ":RC" << RCID;
|
2011-10-13 08:54:59 +08:00
|
|
|
}
|
2011-10-13 07:37:29 +08:00
|
|
|
|
2016-07-18 21:17:31 +08:00
|
|
|
if (InlineAsm::isMemKind(Flag)) {
|
|
|
|
unsigned MCID = InlineAsm::getMemoryConstraintID(Flag);
|
|
|
|
switch (MCID) {
|
|
|
|
case InlineAsm::Constraint_es: OS << ":es"; break;
|
|
|
|
case InlineAsm::Constraint_i: OS << ":i"; break;
|
|
|
|
case InlineAsm::Constraint_m: OS << ":m"; break;
|
|
|
|
case InlineAsm::Constraint_o: OS << ":o"; break;
|
|
|
|
case InlineAsm::Constraint_v: OS << ":v"; break;
|
|
|
|
case InlineAsm::Constraint_Q: OS << ":Q"; break;
|
|
|
|
case InlineAsm::Constraint_R: OS << ":R"; break;
|
|
|
|
case InlineAsm::Constraint_S: OS << ":S"; break;
|
|
|
|
case InlineAsm::Constraint_T: OS << ":T"; break;
|
|
|
|
case InlineAsm::Constraint_Um: OS << ":Um"; break;
|
|
|
|
case InlineAsm::Constraint_Un: OS << ":Un"; break;
|
|
|
|
case InlineAsm::Constraint_Uq: OS << ":Uq"; break;
|
|
|
|
case InlineAsm::Constraint_Us: OS << ":Us"; break;
|
|
|
|
case InlineAsm::Constraint_Ut: OS << ":Ut"; break;
|
|
|
|
case InlineAsm::Constraint_Uv: OS << ":Uv"; break;
|
|
|
|
case InlineAsm::Constraint_Uy: OS << ":Uy"; break;
|
|
|
|
case InlineAsm::Constraint_X: OS << ":X"; break;
|
|
|
|
case InlineAsm::Constraint_Z: OS << ":Z"; break;
|
|
|
|
case InlineAsm::Constraint_ZC: OS << ":ZC"; break;
|
|
|
|
case InlineAsm::Constraint_Zy: OS << ":Zy"; break;
|
|
|
|
default: OS << ":?"; break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
Decode and pretty print inline asm operand descriptors.
The INLINEASM MachineInstrs have an immediate operand describing each
original inline asm operand. Decode the bits in MachineInstr::print() so
it is easier to read:
INLINEASM <es:rorq $1,$0>, $0:[regdef], %vreg0<def>, %vreg1<def>, $1:[imm], 1, $2:[reguse] [tiedto:$0], %vreg2, %vreg3, $3:[regdef-ec], %EFLAGS<earlyclobber,imp-def>
llvm-svn: 133901
2011-06-27 12:08:29 +08:00
|
|
|
unsigned TiedTo = 0;
|
|
|
|
if (InlineAsm::isUseOperandTiedToDef(Flag, TiedTo))
|
2011-10-13 07:37:29 +08:00
|
|
|
OS << " tiedto:$" << TiedTo;
|
|
|
|
|
|
|
|
OS << ']';
|
Decode and pretty print inline asm operand descriptors.
The INLINEASM MachineInstrs have an immediate operand describing each
original inline asm operand. Decode the bits in MachineInstr::print() so
it is easier to read:
INLINEASM <es:rorq $1,$0>, $0:[regdef], %vreg0<def>, %vreg1<def>, $1:[imm], 1, $2:[reguse] [tiedto:$0], %vreg2, %vreg3, $3:[regdef-ec], %EFLAGS<earlyclobber,imp-def>
llvm-svn: 133901
2011-06-27 12:08:29 +08:00
|
|
|
|
|
|
|
// Compute the index of the next operand descriptor.
|
|
|
|
AsmDescOp += 1 + InlineAsm::getNumOperandRegisters(Flag);
|
2010-04-29 04:03:13 +08:00
|
|
|
} else
|
2015-06-27 06:06:47 +08:00
|
|
|
MO.print(OS, MST, TRI);
|
Print "..." instead of all the uninteresting register clobbers on call
instructions. This makes CodeGen dumps significantly less noisy.
Example before:
BL <ga:@bar>, %R0<imp-def>, %R1<imp-def,dead>, %R2<imp-def,dead>, %R3<imp-def,dead>, %R12<imp-def,dead>, %LR<imp-def,dead>, %D0<imp-def,dead>, %D1<imp-def,dead>, %D2<imp-def,dead>, %D3<imp-def,dead>, %D4<imp-def,dead>, %D5<imp-def,dead>, %D6<imp-def,dead>, %D7<imp-def,dead>, %D16<imp-def,dead>, %D17<imp-def,dead>, %D18<imp-def,dead>, %D19<imp-def,dead>, %D20<imp-def,dead>, %D21<imp-def,dead>, %D22<imp-def,dead>, %D23<imp-def,dead>, %D24<imp-def,dead>, %D25<imp-def,dead>, %D26<imp-def,dead>, %D27<imp-def,dead>, %D28<imp-def,dead>, %D29<imp-def,dead>, %D30<imp-def,dead>, %D31<imp-def,dead>, %CPSR<imp-def,dead>, %FPSCR<imp-def,dead>
Same example after:
BL <ga:@bar>, %R0<imp-def>, %R1<imp-def,dead>, %LR<imp-def,dead>, %CPSR<imp-def,dead>, ...
llvm-svn: 86583
2009-11-10 03:38:45 +08:00
|
|
|
}
|
|
|
|
|
2009-11-01 04:19:03 +08:00
|
|
|
bool HaveSemi = false;
|
2015-09-16 19:18:25 +08:00
|
|
|
const unsigned PrintableFlags = FrameSetup | FrameDestroy;
|
2013-01-10 02:35:09 +08:00
|
|
|
if (Flags & PrintableFlags) {
|
2016-01-02 21:40:36 +08:00
|
|
|
if (!HaveSemi) {
|
|
|
|
OS << ";";
|
|
|
|
HaveSemi = true;
|
|
|
|
}
|
2011-03-06 02:43:04 +08:00
|
|
|
OS << " flags: ";
|
|
|
|
|
|
|
|
if (Flags & FrameSetup)
|
|
|
|
OS << "FrameSetup";
|
2015-09-16 19:18:25 +08:00
|
|
|
|
|
|
|
if (Flags & FrameDestroy)
|
|
|
|
OS << "FrameDestroy";
|
2011-03-06 02:43:04 +08:00
|
|
|
}
|
|
|
|
|
2008-07-08 07:14:23 +08:00
|
|
|
if (!memoperands_empty()) {
|
2016-01-02 21:40:36 +08:00
|
|
|
if (!HaveSemi) {
|
|
|
|
OS << ";";
|
|
|
|
HaveSemi = true;
|
|
|
|
}
|
2009-11-01 04:19:03 +08:00
|
|
|
|
|
|
|
OS << " mem:";
|
2009-09-26 04:36:54 +08:00
|
|
|
for (mmo_iterator i = memoperands_begin(), e = memoperands_end();
|
|
|
|
i != e; ++i) {
|
2015-06-27 06:06:47 +08:00
|
|
|
(*i)->print(OS, MST);
|
2014-03-02 20:27:27 +08:00
|
|
|
if (std::next(i) != e)
|
2009-09-23 09:33:16 +08:00
|
|
|
OS << " ";
|
2008-02-07 06:27:42 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2010-07-29 02:35:46 +08:00
|
|
|
// Print the regclass of any virtual registers encountered.
|
|
|
|
if (MRI && !VirtRegs.empty()) {
|
2016-01-02 21:40:36 +08:00
|
|
|
if (!HaveSemi) {
|
|
|
|
OS << ";";
|
|
|
|
HaveSemi = true;
|
|
|
|
}
|
2010-07-29 02:35:46 +08:00
|
|
|
for (unsigned i = 0; i != VirtRegs.size(); ++i) {
|
2016-04-08 07:18:11 +08:00
|
|
|
const RegClassOrRegBank &RC = MRI->getRegClassOrRegBank(VirtRegs[i]);
|
2016-02-11 08:19:17 +08:00
|
|
|
if (!RC)
|
|
|
|
continue;
|
2016-04-08 07:18:11 +08:00
|
|
|
// Generic virtual registers do not have register classes.
|
|
|
|
if (RC.is<const RegisterBank *>())
|
|
|
|
OS << " " << RC.get<const RegisterBank *>()->getName();
|
|
|
|
else
|
|
|
|
OS << " "
|
|
|
|
<< TRI->getRegClassName(RC.get<const TargetRegisterClass *>());
|
|
|
|
OS << ':' << PrintReg(VirtRegs[i]);
|
2010-07-29 02:35:46 +08:00
|
|
|
for (unsigned j = i+1; j != VirtRegs.size();) {
|
2016-04-08 07:18:11 +08:00
|
|
|
if (MRI->getRegClassOrRegBank(VirtRegs[j]) != RC) {
|
2010-07-29 02:35:46 +08:00
|
|
|
++j;
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
if (VirtRegs[i] != VirtRegs[j])
|
2011-01-09 11:05:53 +08:00
|
|
|
OS << "," << PrintReg(VirtRegs[j]);
|
2010-07-29 02:35:46 +08:00
|
|
|
VirtRegs.erase(VirtRegs.begin()+j);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-03-06 02:43:04 +08:00
|
|
|
// Print debug location information.
|
2015-04-04 00:23:04 +08:00
|
|
|
if (isDebugValue() && getOperand(e - 2).isMetadata()) {
|
2016-01-02 21:40:36 +08:00
|
|
|
if (!HaveSemi)
|
|
|
|
OS << ";";
|
2015-04-30 00:38:44 +08:00
|
|
|
auto *DV = cast<DILocalVariable>(getOperand(e - 2).getMetadata());
|
2015-04-14 10:22:36 +08:00
|
|
|
OS << " line no:" << DV->getLine();
|
2015-04-16 06:29:27 +08:00
|
|
|
if (auto *InlinedAt = debugLoc->getInlinedAt()) {
|
2015-03-31 03:14:47 +08:00
|
|
|
DebugLoc InlinedAtDL(InlinedAt);
|
|
|
|
if (InlinedAtDL && MF) {
|
2011-08-05 04:44:26 +08:00
|
|
|
OS << " inlined @[ ";
|
2015-09-22 19:15:07 +08:00
|
|
|
InlinedAtDL.print(OS);
|
2011-08-05 04:44:26 +08:00
|
|
|
OS << " ]";
|
|
|
|
}
|
|
|
|
}
|
Move the complex address expression out of DIVariable and into an extra
argument of the llvm.dbg.declare/llvm.dbg.value intrinsics.
Previously, DIVariable was a variable-length field that has an optional
reference to a Metadata array consisting of a variable number of
complex address expressions. In the case of OpPiece expressions this is
wasting a lot of storage in IR, because when an aggregate type is, e.g.,
SROA'd into all of its n individual members, the IR will contain n copies
of the DIVariable, all alike, only differing in the complex address
reference at the end.
By making the complex address into an extra argument of the
dbg.value/dbg.declare intrinsics, all of the pieces can reference the
same variable and the complex address expressions can be uniqued across
the CU, too.
Down the road, this will allow us to move other flags, such as
"indirection" out of the DIVariable, too.
The new intrinsics look like this:
declare void @llvm.dbg.declare(metadata %storage, metadata %var, metadata %expr)
declare void @llvm.dbg.value(metadata %storage, i64 %offset, metadata %var, metadata %expr)
This patch adds a new LLVM-local tag to DIExpressions, so we can detect
and pretty-print DIExpression metadata nodes.
What this patch doesn't do:
This patch does not touch the "Indirect" field in DIVariable; but moving
that into the expression would be a natural next step.
http://reviews.llvm.org/D4919
rdar://problem/17994491
Thanks to dblaikie and dexonsmith for reviewing this patch!
Note: I accidentally committed a bogus older version of this patch previously.
llvm-svn: 218787
2014-10-02 02:55:02 +08:00
|
|
|
if (isIndirectDebugValue())
|
|
|
|
OS << " indirect";
|
2017-02-24 05:05:29 +08:00
|
|
|
} else if (SkipDebugLoc) {
|
|
|
|
return;
|
|
|
|
} else if (debugLoc && MF) {
|
2016-01-02 21:40:36 +08:00
|
|
|
if (!HaveSemi)
|
|
|
|
OS << ";";
|
2009-11-24 05:29:08 +08:00
|
|
|
OS << " dbg:";
|
2015-02-27 07:32:17 +08:00
|
|
|
debugLoc.print(OS);
|
2009-02-20 05:44:55 +08:00
|
|
|
}
|
|
|
|
|
2011-03-06 02:43:04 +08:00
|
|
|
OS << '\n';
|
2002-10-30 08:48:05 +08:00
|
|
|
}
|
|
|
|
|
2008-01-24 09:10:07 +08:00
|
|
|
bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
|
2008-02-11 02:45:23 +08:00
|
|
|
const TargetRegisterInfo *RegInfo,
|
2008-01-24 09:10:07 +08:00
|
|
|
bool AddIfNotFound) {
|
2008-04-16 17:41:59 +08:00
|
|
|
bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
|
2012-06-02 07:28:30 +08:00
|
|
|
bool hasAliases = isPhysReg &&
|
|
|
|
MCRegAliasIterator(IncomingReg, RegInfo, false).isValid();
|
2008-09-03 23:56:16 +08:00
|
|
|
bool Found = false;
|
2008-04-16 17:41:59 +08:00
|
|
|
SmallVector<unsigned,4> DeadOps;
|
2008-03-04 06:14:33 +08:00
|
|
|
for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
|
|
|
|
MachineOperand &MO = getOperand(i);
|
2009-08-05 04:09:25 +08:00
|
|
|
if (!MO.isReg() || !MO.isUse() || MO.isUndef())
|
2008-04-16 17:41:59 +08:00
|
|
|
continue;
|
2016-05-11 01:57:27 +08:00
|
|
|
|
|
|
|
// DEBUG_VALUE nodes do not contribute to code generation and should
|
|
|
|
// always be ignored. Failure to do so may result in trying to modify
|
|
|
|
// KILL flags on DEBUG_VALUE nodes.
|
|
|
|
if (MO.isDebug())
|
|
|
|
continue;
|
|
|
|
|
2008-04-16 17:41:59 +08:00
|
|
|
unsigned Reg = MO.getReg();
|
|
|
|
if (!Reg)
|
|
|
|
continue;
|
2008-03-04 06:14:33 +08:00
|
|
|
|
2008-04-16 17:41:59 +08:00
|
|
|
if (Reg == IncomingReg) {
|
2008-09-03 23:56:16 +08:00
|
|
|
if (!Found) {
|
|
|
|
if (MO.isKill())
|
|
|
|
// The register is already marked kill.
|
|
|
|
return true;
|
2009-08-03 03:13:03 +08:00
|
|
|
if (isPhysReg && isRegTiedToDefOperand(i))
|
|
|
|
// Two-address uses of physregs must not be marked kill.
|
|
|
|
return true;
|
2008-09-03 23:56:16 +08:00
|
|
|
MO.setIsKill();
|
|
|
|
Found = true;
|
|
|
|
}
|
|
|
|
} else if (hasAliases && MO.isKill() &&
|
|
|
|
TargetRegisterInfo::isPhysicalRegister(Reg)) {
|
2008-04-16 17:41:59 +08:00
|
|
|
// A super-register kill already exists.
|
|
|
|
if (RegInfo->isSuperRegister(IncomingReg, Reg))
|
2008-07-03 09:18:51 +08:00
|
|
|
return true;
|
|
|
|
if (RegInfo->isSubRegister(IncomingReg, Reg))
|
2008-04-16 17:41:59 +08:00
|
|
|
DeadOps.push_back(i);
|
2008-01-24 09:10:07 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2008-04-16 17:41:59 +08:00
|
|
|
// Trim unneeded kill operands.
|
|
|
|
while (!DeadOps.empty()) {
|
|
|
|
unsigned OpIdx = DeadOps.back();
|
|
|
|
if (getOperand(OpIdx).isImplicit())
|
|
|
|
RemoveOperand(OpIdx);
|
|
|
|
else
|
|
|
|
getOperand(OpIdx).setIsKill(false);
|
|
|
|
DeadOps.pop_back();
|
|
|
|
}
|
|
|
|
|
2008-03-04 06:14:33 +08:00
|
|
|
// If not found, this means an alias of one of the operands is killed. Add a
|
2008-01-24 09:10:07 +08:00
|
|
|
// new implicit operand if required.
|
2008-09-03 23:56:16 +08:00
|
|
|
if (!Found && AddIfNotFound) {
|
2008-03-04 06:14:33 +08:00
|
|
|
addOperand(MachineOperand::CreateReg(IncomingReg,
|
|
|
|
false /*IsDef*/,
|
|
|
|
true /*IsImp*/,
|
|
|
|
true /*IsKill*/));
|
2008-01-24 09:10:07 +08:00
|
|
|
return true;
|
|
|
|
}
|
2008-09-03 23:56:16 +08:00
|
|
|
return Found;
|
2008-01-24 09:10:07 +08:00
|
|
|
}
|
|
|
|
|
2012-01-27 01:52:15 +08:00
|
|
|
void MachineInstr::clearRegisterKills(unsigned Reg,
|
|
|
|
const TargetRegisterInfo *RegInfo) {
|
|
|
|
if (!TargetRegisterInfo::isPhysicalRegister(Reg))
|
2014-04-14 08:51:57 +08:00
|
|
|
RegInfo = nullptr;
|
2015-02-22 01:08:08 +08:00
|
|
|
for (MachineOperand &MO : operands()) {
|
2012-01-27 01:52:15 +08:00
|
|
|
if (!MO.isReg() || !MO.isUse() || !MO.isKill())
|
|
|
|
continue;
|
|
|
|
unsigned OpReg = MO.getReg();
|
2016-02-25 03:21:48 +08:00
|
|
|
if ((RegInfo && RegInfo->regsOverlap(Reg, OpReg)) || Reg == OpReg)
|
2012-01-27 01:52:15 +08:00
|
|
|
MO.setIsKill(false);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-10-11 05:28:38 +08:00
|
|
|
bool MachineInstr::addRegisterDead(unsigned Reg,
|
2008-02-11 02:45:23 +08:00
|
|
|
const TargetRegisterInfo *RegInfo,
|
2008-01-24 09:10:07 +08:00
|
|
|
bool AddIfNotFound) {
|
2013-10-11 05:28:38 +08:00
|
|
|
bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(Reg);
|
2012-06-02 07:28:30 +08:00
|
|
|
bool hasAliases = isPhysReg &&
|
2013-10-11 05:28:38 +08:00
|
|
|
MCRegAliasIterator(Reg, RegInfo, false).isValid();
|
2008-09-03 23:56:16 +08:00
|
|
|
bool Found = false;
|
2008-04-16 17:41:59 +08:00
|
|
|
SmallVector<unsigned,4> DeadOps;
|
2008-01-24 09:10:07 +08:00
|
|
|
for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
|
|
|
|
MachineOperand &MO = getOperand(i);
|
2008-10-03 23:45:36 +08:00
|
|
|
if (!MO.isReg() || !MO.isDef())
|
2008-04-16 17:41:59 +08:00
|
|
|
continue;
|
2013-10-11 05:28:38 +08:00
|
|
|
unsigned MOReg = MO.getReg();
|
|
|
|
if (!MOReg)
|
2008-09-03 23:56:16 +08:00
|
|
|
continue;
|
|
|
|
|
2013-10-11 05:28:38 +08:00
|
|
|
if (MOReg == Reg) {
|
2011-04-06 00:53:50 +08:00
|
|
|
MO.setIsDead();
|
|
|
|
Found = true;
|
2008-09-03 23:56:16 +08:00
|
|
|
} else if (hasAliases && MO.isDead() &&
|
2013-10-11 05:28:38 +08:00
|
|
|
TargetRegisterInfo::isPhysicalRegister(MOReg)) {
|
2008-04-16 17:41:59 +08:00
|
|
|
// There exists a super-register that's marked dead.
|
2013-10-11 05:28:38 +08:00
|
|
|
if (RegInfo->isSuperRegister(Reg, MOReg))
|
2008-07-03 09:18:51 +08:00
|
|
|
return true;
|
2013-10-11 05:28:38 +08:00
|
|
|
if (RegInfo->isSubRegister(Reg, MOReg))
|
2008-04-16 17:41:59 +08:00
|
|
|
DeadOps.push_back(i);
|
2008-01-24 09:10:07 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2008-04-16 17:41:59 +08:00
|
|
|
// Trim unneeded dead operands.
|
|
|
|
while (!DeadOps.empty()) {
|
|
|
|
unsigned OpIdx = DeadOps.back();
|
|
|
|
if (getOperand(OpIdx).isImplicit())
|
|
|
|
RemoveOperand(OpIdx);
|
|
|
|
else
|
|
|
|
getOperand(OpIdx).setIsDead(false);
|
|
|
|
DeadOps.pop_back();
|
|
|
|
}
|
|
|
|
|
2008-09-03 23:56:16 +08:00
|
|
|
// If not found, this means an alias of one of the operands is dead. Add a
|
|
|
|
// new implicit operand if required.
|
2009-06-25 01:54:48 +08:00
|
|
|
if (Found || !AddIfNotFound)
|
|
|
|
return Found;
|
2011-08-25 00:44:17 +08:00
|
|
|
|
2013-10-11 05:28:38 +08:00
|
|
|
addOperand(MachineOperand::CreateReg(Reg,
|
2009-06-25 01:54:48 +08:00
|
|
|
true /*IsDef*/,
|
|
|
|
true /*IsImp*/,
|
|
|
|
false /*IsKill*/,
|
|
|
|
true /*IsDead*/));
|
|
|
|
return true;
|
2008-01-24 09:10:07 +08:00
|
|
|
}
|
2010-01-06 08:29:28 +08:00
|
|
|
|
2015-02-05 03:35:16 +08:00
|
|
|
void MachineInstr::clearRegisterDeads(unsigned Reg) {
|
|
|
|
for (MachineOperand &MO : operands()) {
|
|
|
|
if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg)
|
|
|
|
continue;
|
|
|
|
MO.setIsDead(false);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-11-11 08:41:58 +08:00
|
|
|
void MachineInstr::setRegisterDefReadUndef(unsigned Reg, bool IsUndef) {
|
2015-01-22 06:55:13 +08:00
|
|
|
for (MachineOperand &MO : operands()) {
|
|
|
|
if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg || MO.getSubReg() == 0)
|
|
|
|
continue;
|
2015-11-11 08:41:58 +08:00
|
|
|
MO.setIsUndef(IsUndef);
|
2015-01-22 06:55:13 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-10-11 05:28:38 +08:00
|
|
|
void MachineInstr::addRegisterDefined(unsigned Reg,
|
2010-01-06 08:29:28 +08:00
|
|
|
const TargetRegisterInfo *RegInfo) {
|
2013-10-11 05:28:38 +08:00
|
|
|
if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
|
|
|
|
MachineOperand *MO = findRegisterDefOperand(Reg, false, RegInfo);
|
2010-05-22 00:32:16 +08:00
|
|
|
if (MO)
|
|
|
|
return;
|
|
|
|
} else {
|
2015-02-22 01:08:08 +08:00
|
|
|
for (const MachineOperand &MO : operands()) {
|
2013-10-11 05:28:38 +08:00
|
|
|
if (MO.isReg() && MO.getReg() == Reg && MO.isDef() &&
|
2010-05-22 00:32:16 +08:00
|
|
|
MO.getSubReg() == 0)
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
}
|
2013-10-11 05:28:38 +08:00
|
|
|
addOperand(MachineOperand::CreateReg(Reg,
|
2010-05-22 00:32:16 +08:00
|
|
|
true /*IsDef*/,
|
|
|
|
true /*IsImp*/));
|
2010-01-06 08:29:28 +08:00
|
|
|
}
|
2010-03-04 07:37:30 +08:00
|
|
|
|
2012-02-04 04:43:39 +08:00
|
|
|
void MachineInstr::setPhysRegsDeadExcept(ArrayRef<unsigned> UsedRegs,
|
2010-06-19 07:28:01 +08:00
|
|
|
const TargetRegisterInfo &TRI) {
|
2012-02-04 05:23:14 +08:00
|
|
|
bool HasRegMask = false;
|
2015-02-22 01:08:08 +08:00
|
|
|
for (MachineOperand &MO : operands()) {
|
2012-02-04 05:23:14 +08:00
|
|
|
if (MO.isRegMask()) {
|
|
|
|
HasRegMask = true;
|
|
|
|
continue;
|
|
|
|
}
|
2010-06-19 07:28:01 +08:00
|
|
|
if (!MO.isReg() || !MO.isDef()) continue;
|
|
|
|
unsigned Reg = MO.getReg();
|
2012-02-04 04:43:35 +08:00
|
|
|
if (!TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
|
2010-06-19 07:28:01 +08:00
|
|
|
// If there are no uses, including partial uses, the def is dead.
|
2017-05-31 09:10:10 +08:00
|
|
|
if (llvm::none_of(UsedRegs,
|
|
|
|
[&](unsigned Use) { return TRI.regsOverlap(Use, Reg); }))
|
2015-02-22 01:08:08 +08:00
|
|
|
MO.setIsDead();
|
2010-06-19 07:28:01 +08:00
|
|
|
}
|
2012-02-04 05:23:14 +08:00
|
|
|
|
|
|
|
// This is a call with a register mask operand.
|
|
|
|
// Mask clobbers are always dead, so add defs for the non-dead defines.
|
|
|
|
if (HasRegMask)
|
|
|
|
for (ArrayRef<unsigned>::iterator I = UsedRegs.begin(), E = UsedRegs.end();
|
|
|
|
I != E; ++I)
|
|
|
|
addRegisterDefined(*I, &TRI);
|
2010-06-19 07:28:01 +08:00
|
|
|
}
|
|
|
|
|
2010-03-04 07:37:30 +08:00
|
|
|
unsigned
|
|
|
|
MachineInstrExpressionTrait::getHashValue(const MachineInstr* const &MI) {
|
2012-03-07 17:39:46 +08:00
|
|
|
// Build up a buffer of hash code components.
|
|
|
|
SmallVector<size_t, 8> HashComponents;
|
|
|
|
HashComponents.reserve(MI->getNumOperands() + 1);
|
|
|
|
HashComponents.push_back(MI->getOpcode());
|
2015-02-22 01:08:08 +08:00
|
|
|
for (const MachineOperand &MO : MI->operands()) {
|
2012-07-05 19:06:22 +08:00
|
|
|
if (MO.isReg() && MO.isDef() &&
|
|
|
|
TargetRegisterInfo::isVirtualRegister(MO.getReg()))
|
|
|
|
continue; // Skip virtual register defs.
|
|
|
|
|
|
|
|
HashComponents.push_back(hash_value(MO));
|
2012-03-07 17:39:46 +08:00
|
|
|
}
|
|
|
|
return hash_combine_range(HashComponents.begin(), HashComponents.end());
|
2010-03-04 07:37:30 +08:00
|
|
|
}
|
2011-07-02 11:53:34 +08:00
|
|
|
|
|
|
|
void MachineInstr::emitError(StringRef Msg) const {
|
|
|
|
// Find the source location cookie.
|
|
|
|
unsigned LocCookie = 0;
|
2014-04-14 08:51:57 +08:00
|
|
|
const MDNode *LocMD = nullptr;
|
2011-07-02 11:53:34 +08:00
|
|
|
for (unsigned i = getNumOperands(); i != 0; --i) {
|
|
|
|
if (getOperand(i-1).isMetadata() &&
|
|
|
|
(LocMD = getOperand(i-1).getMetadata()) &&
|
|
|
|
LocMD->getNumOperands() != 0) {
|
IR: Split Metadata from Value
Split `Metadata` away from the `Value` class hierarchy, as part of
PR21532. Assembly and bitcode changes are in the wings, but this is the
bulk of the change for the IR C++ API.
I have a follow-up patch prepared for `clang`. If this breaks other
sub-projects, I apologize in advance :(. Help me compile it on Darwin
I'll try to fix it. FWIW, the errors should be easy to fix, so it may
be simpler to just fix it yourself.
This breaks the build for all metadata-related code that's out-of-tree.
Rest assured the transition is mechanical and the compiler should catch
almost all of the problems.
Here's a quick guide for updating your code:
- `Metadata` is the root of a class hierarchy with three main classes:
`MDNode`, `MDString`, and `ValueAsMetadata`. It is distinct from
the `Value` class hierarchy. It is typeless -- i.e., instances do
*not* have a `Type`.
- `MDNode`'s operands are all `Metadata *` (instead of `Value *`).
- `TrackingVH<MDNode>` and `WeakVH` referring to metadata can be
replaced with `TrackingMDNodeRef` and `TrackingMDRef`, respectively.
If you're referring solely to resolved `MDNode`s -- post graph
construction -- just use `MDNode*`.
- `MDNode` (and the rest of `Metadata`) have only limited support for
`replaceAllUsesWith()`.
As long as an `MDNode` is pointing at a forward declaration -- the
result of `MDNode::getTemporary()` -- it maintains a side map of its
uses and can RAUW itself. Once the forward declarations are fully
resolved RAUW support is dropped on the ground. This means that
uniquing collisions on changing operands cause nodes to become
"distinct". (This already happened fairly commonly, whenever an
operand went to null.)
If you're constructing complex (non self-reference) `MDNode` cycles,
you need to call `MDNode::resolveCycles()` on each node (or on a
top-level node that somehow references all of the nodes). Also,
don't do that. Metadata cycles (and the RAUW machinery needed to
construct them) are expensive.
- An `MDNode` can only refer to a `Constant` through a bridge called
`ConstantAsMetadata` (one of the subclasses of `ValueAsMetadata`).
As a side effect, accessing an operand of an `MDNode` that is known
to be, e.g., `ConstantInt`, takes three steps: first, cast from
`Metadata` to `ConstantAsMetadata`; second, extract the `Constant`;
third, cast down to `ConstantInt`.
The eventual goal is to introduce `MDInt`/`MDFloat`/etc. and have
metadata schema owners transition away from using `Constant`s when
the type isn't important (and they don't care about referring to
`GlobalValue`s).
In the meantime, I've added transitional API to the `mdconst`
namespace that matches semantics with the old code, in order to
avoid adding the error-prone three-step equivalent to every call
site. If your old code was:
MDNode *N = foo();
bar(isa <ConstantInt>(N->getOperand(0)));
baz(cast <ConstantInt>(N->getOperand(1)));
bak(cast_or_null <ConstantInt>(N->getOperand(2)));
bat(dyn_cast <ConstantInt>(N->getOperand(3)));
bay(dyn_cast_or_null<ConstantInt>(N->getOperand(4)));
you can trivially match its semantics with:
MDNode *N = foo();
bar(mdconst::hasa <ConstantInt>(N->getOperand(0)));
baz(mdconst::extract <ConstantInt>(N->getOperand(1)));
bak(mdconst::extract_or_null <ConstantInt>(N->getOperand(2)));
bat(mdconst::dyn_extract <ConstantInt>(N->getOperand(3)));
bay(mdconst::dyn_extract_or_null<ConstantInt>(N->getOperand(4)));
and when you transition your metadata schema to `MDInt`:
MDNode *N = foo();
bar(isa <MDInt>(N->getOperand(0)));
baz(cast <MDInt>(N->getOperand(1)));
bak(cast_or_null <MDInt>(N->getOperand(2)));
bat(dyn_cast <MDInt>(N->getOperand(3)));
bay(dyn_cast_or_null<MDInt>(N->getOperand(4)));
- A `CallInst` -- specifically, intrinsic instructions -- can refer to
metadata through a bridge called `MetadataAsValue`. This is a
subclass of `Value` where `getType()->isMetadataTy()`.
`MetadataAsValue` is the *only* class that can legally refer to a
`LocalAsMetadata`, which is a bridged form of non-`Constant` values
like `Argument` and `Instruction`. It can also refer to any other
`Metadata` subclass.
(I'll break all your testcases in a follow-up commit, when I propagate
this change to assembly.)
llvm-svn: 223802
2014-12-10 02:38:53 +08:00
|
|
|
if (const ConstantInt *CI =
|
|
|
|
mdconst::dyn_extract<ConstantInt>(LocMD->getOperand(0))) {
|
2011-07-02 11:53:34 +08:00
|
|
|
LocCookie = CI->getZExtValue();
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (const MachineBasicBlock *MBB = getParent())
|
|
|
|
if (const MachineFunction *MF = MBB->getParent())
|
|
|
|
return MF->getMMI().getModule()->getContext().emitError(LocCookie, Msg);
|
|
|
|
report_fatal_error(Msg);
|
|
|
|
}
|
2016-04-15 02:29:59 +08:00
|
|
|
|
2016-06-12 23:39:02 +08:00
|
|
|
MachineInstrBuilder llvm::BuildMI(MachineFunction &MF, const DebugLoc &DL,
|
2016-04-15 02:29:59 +08:00
|
|
|
const MCInstrDesc &MCID, bool IsIndirect,
|
2017-07-29 07:00:45 +08:00
|
|
|
unsigned Reg, const MDNode *Variable,
|
|
|
|
const MDNode *Expr) {
|
2016-04-15 02:29:59 +08:00
|
|
|
assert(isa<DILocalVariable>(Variable) && "not a variable");
|
|
|
|
assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
|
|
|
|
assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
|
|
|
|
"Expected inlined-at fields to agree");
|
|
|
|
if (IsIndirect)
|
|
|
|
return BuildMI(MF, DL, MCID)
|
|
|
|
.addReg(Reg, RegState::Debug)
|
2017-07-29 07:00:45 +08:00
|
|
|
.addImm(0U)
|
2016-04-15 02:29:59 +08:00
|
|
|
.addMetadata(Variable)
|
|
|
|
.addMetadata(Expr);
|
2017-07-29 07:00:45 +08:00
|
|
|
else
|
2016-04-15 02:29:59 +08:00
|
|
|
return BuildMI(MF, DL, MCID)
|
|
|
|
.addReg(Reg, RegState::Debug)
|
|
|
|
.addReg(0U, RegState::Debug)
|
|
|
|
.addMetadata(Variable)
|
|
|
|
.addMetadata(Expr);
|
|
|
|
}
|
|
|
|
|
|
|
|
MachineInstrBuilder llvm::BuildMI(MachineBasicBlock &BB,
|
2016-06-12 23:39:02 +08:00
|
|
|
MachineBasicBlock::iterator I,
|
|
|
|
const DebugLoc &DL, const MCInstrDesc &MCID,
|
|
|
|
bool IsIndirect, unsigned Reg,
|
2017-07-29 07:00:45 +08:00
|
|
|
const MDNode *Variable, const MDNode *Expr) {
|
2016-04-15 02:29:59 +08:00
|
|
|
assert(isa<DILocalVariable>(Variable) && "not a variable");
|
|
|
|
assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
|
|
|
|
MachineFunction &MF = *BB.getParent();
|
2017-07-29 07:00:45 +08:00
|
|
|
MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, Reg, Variable, Expr);
|
2016-04-15 02:29:59 +08:00
|
|
|
BB.insert(I, MI);
|
|
|
|
return MachineInstrBuilder(MF, MI);
|
|
|
|
}
|
2017-04-18 09:21:53 +08:00
|
|
|
|
2017-09-16 05:49:56 +08:00
|
|
|
/// Compute the new DIExpression to use with a DBG_VALUE for a spill slot.
|
|
|
|
/// This prepends DW_OP_deref when spilling an indirect DBG_VALUE.
|
|
|
|
static const DIExpression *computeExprForSpill(const MachineInstr &MI) {
|
|
|
|
assert(MI.getOperand(0).isReg() && "can't spill non-register");
|
|
|
|
assert(MI.getDebugVariable()->isValidLocationForIntrinsic(MI.getDebugLoc()) &&
|
|
|
|
"Expected inlined-at fields to agree");
|
|
|
|
|
|
|
|
const DIExpression *Expr = MI.getDebugExpression();
|
|
|
|
if (MI.isIndirectDebugValue()) {
|
|
|
|
assert(MI.getOperand(1).getImm() == 0 && "DBG_VALUE with nonzero offset");
|
|
|
|
Expr = DIExpression::prepend(Expr, DIExpression::WithDeref);
|
|
|
|
}
|
|
|
|
return Expr;
|
|
|
|
}
|
|
|
|
|
2017-04-18 09:21:53 +08:00
|
|
|
MachineInstr *llvm::buildDbgValueForSpill(MachineBasicBlock &BB,
|
|
|
|
MachineBasicBlock::iterator I,
|
|
|
|
const MachineInstr &Orig,
|
|
|
|
int FrameIndex) {
|
2017-09-16 05:49:56 +08:00
|
|
|
const DIExpression *Expr = computeExprForSpill(Orig);
|
|
|
|
return BuildMI(BB, I, Orig.getDebugLoc(), Orig.getDesc())
|
2017-04-18 09:21:53 +08:00
|
|
|
.addFrameIndex(FrameIndex)
|
2017-07-29 07:00:45 +08:00
|
|
|
.addImm(0U)
|
2017-09-16 05:49:56 +08:00
|
|
|
.addMetadata(Orig.getDebugVariable())
|
2017-04-18 09:21:53 +08:00
|
|
|
.addMetadata(Expr);
|
|
|
|
}
|
2017-09-16 05:49:56 +08:00
|
|
|
|
|
|
|
void llvm::updateDbgValueForSpill(MachineInstr &Orig, int FrameIndex) {
|
|
|
|
const DIExpression *Expr = computeExprForSpill(Orig);
|
|
|
|
Orig.getOperand(0).ChangeToFrameIndex(FrameIndex);
|
|
|
|
Orig.getOperand(1).ChangeToImmediate(0U);
|
|
|
|
Orig.getOperand(3).setMetadata(Expr);
|
|
|
|
}
|