llvm-project/llvm/test/CodeGen/PowerPC/vec_shift.ll

; RUN: llc -verify-machineinstrs < %s  -march=ppc32 -mcpu=g5
; PR3628

define void @update(<4 x i32> %val, <4 x i32>* %dst) nounwind {
entry:
	%shl = shl <4 x i32> %val, < i32 4, i32 3, i32 2, i32 1 >
	%shr = ashr <4 x i32> %shl, < i32 1, i32 2, i32 3, i32 4 >
	store <4 x i32> %shr, <4 x i32>* %dst
	ret void
}
Adding -verify-machineinstrs option to PowerPC tests Currently we have a number of tests that fail with -verify-machineinstrs. To detect this cases earlier we add the option to the testcases with the exception of tests that will currently fail with this option. PR 27456 keeps track of this failures. No code review, as discussed with Hal Finkel. llvm-svn: 277624 2016-08-04 02:17:35 +08:00			`; RUN: llc -verify-machineinstrs < %s -march=ppc32 -mcpu=g5`
PR3628: Add patterns to match SHL/SRL/SRA to the corresponding Altivec instructions. llvm-svn: 73009 2009-06-07 09:07:55 +08:00			`; PR3628`

			`define void @update(<4 x i32> %val, <4 x i32>* %dst) nounwind {`
			`entry:`
			`%shl = shl <4 x i32> %val, < i32 4, i32 3, i32 2, i32 1 >`
			`%shr = ashr <4 x i32> %shl, < i32 1, i32 2, i32 3, i32 4 >`
			`store <4 x i32> %shr, <4 x i32>* %dst`
			`ret void`
			`}`