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llvm-project/llvm/test/CodeGen/ARM/mul_const.ll

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Eliminate more uses of llvm-as and llvm-dis. llvm-svn: 81293
2009-09-09 08:09:15 +08:00
; RUN: llc < %s -march=arm | FileCheck %s
Fix ARM isle code that optimize multiply by constants which are power-of-2 +/- 1. llvm-svn: 76520
2009-07-21 08:31:12 +08:00
Some cheap DAG combine goodness for multiplication with a particular constant. This can be extended later on to handle more "complex" constants. llvm-svn: 103881
2010-05-16 02:16:59 +08:00
define i32 @t9(i32 %v) nounwind readnone {
Fix ARM isle code that optimize multiply by constants which are power-of-2 +/- 1. llvm-svn: 76520
2009-07-21 08:31:12 +08:00
entry:
Some cheap DAG combine goodness for multiplication with a particular constant. This can be extended later on to handle more "complex" constants. llvm-svn: 103881
2010-05-16 02:16:59 +08:00
; CHECK: t9:
Fix ARM isle code that optimize multiply by constants which are power-of-2 +/- 1. llvm-svn: 76520
2009-07-21 08:31:12 +08:00
; CHECK: add r0, r0, r0, lsl #3
%0 = mul i32 %v, 9
ret i32 %0
}
Some cheap DAG combine goodness for multiplication with a particular constant. This can be extended later on to handle more "complex" constants. llvm-svn: 103881
2010-05-16 02:16:59 +08:00
define i32 @t7(i32 %v) nounwind readnone {
Fix ARM isle code that optimize multiply by constants which are power-of-2 +/- 1. llvm-svn: 76520
2009-07-21 08:31:12 +08:00
entry:
Some cheap DAG combine goodness for multiplication with a particular constant. This can be extended later on to handle more "complex" constants. llvm-svn: 103881
2010-05-16 02:16:59 +08:00
; CHECK: t7:
Fix ARM isle code that optimize multiply by constants which are power-of-2 +/- 1. llvm-svn: 76520
2009-07-21 08:31:12 +08:00
; CHECK: rsb r0, r0, r0, lsl #3
%0 = mul i32 %v, 7
ret i32 %0
}
Some cheap DAG combine goodness for multiplication with a particular constant. This can be extended later on to handle more "complex" constants. llvm-svn: 103881
2010-05-16 02:16:59 +08:00
define i32 @t5(i32 %v) nounwind readnone {
entry:
; CHECK: t5:
; CHECK: add r0, r0, r0, lsl #2
%0 = mul i32 %v, 5
ret i32 %0
}
define i32 @t3(i32 %v) nounwind readnone {
entry:
; CHECK: t3:
; CHECK: add r0, r0, r0, lsl #1
%0 = mul i32 %v, 3
ret i32 %0
}
define i32 @t12288(i32 %v) nounwind readnone {
entry:
; CHECK: t12288:
; CHECK: add r0, r0, r0, lsl #1
; CHECK: mov r0, r0, lsl #12
%0 = mul i32 %v, 12288
ret i32 %0
}