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llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum.mir

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AMDGPU/GlobalISel: Selection for fminnum/fmaxnum v2f16 case doesn't work yet because the VOP3P complex patterns haven't been ported yet. llvm-svn: 366585
2019-07-19 22:42:40 +08:00
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
AMDGPU/GlobalISel: Initial selection of MUBUF addr64 load/store Fixes the main reason for compile failures on SI, but doesn't really try to use the addressing modes yet.
2020-01-23 05:56:48 +08:00
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX7 %s
AMDGPU/GlobalISel: Selection for fminnum/fmaxnum v2f16 case doesn't work yet because the VOP3P complex patterns haven't been ported yet. llvm-svn: 366585
2019-07-19 22:42:40 +08:00
# FIXME: Ideally this would fail to select with ieee mode enabled.
---
name: fmaxnum_f32_f64_ieee_mode_on
legalized: true
regBankSelected: true
machineFunctionInfo:
mode:
ieee: true
body: |
bb.0:
liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr3_vgpr4, $sgpr10_sgpr11, $vgpr10_vgpr11, $vgpr12_vgpr13
; GFX7-LABEL: name: fmaxnum_f32_f64_ieee_mode_on
AMDGPU: Relax 32-bit SGPR register class Mostly use SReg_32 instead of SReg_32_XM0 for arbitrary values. This will allow the register coalescer to do a better job eliminating copies to m0. For GlobalISel, as a terrible hack, use SGPR_32 for things that should use SCC until booleans are solved. llvm-svn: 375267
2019-10-19 02:26:37 +08:00
; GFX7: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
AMDGPU/GlobalISel: Selection for fminnum/fmaxnum v2f16 case doesn't work yet because the VOP3P complex patterns haven't been ported yet. llvm-svn: 366585
2019-07-19 22:42:40 +08:00
; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX7: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX7: [[COPY3:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4
AMDGPU/GlobalISel: Don't use XEXEC class for SGPRs We don't use the xexec register classes for arbitrary values anymore. Avoids a test variance beween GlobalISel and SelectionDAG>
2020-01-13 06:10:18 +08:00
; GFX7: [[COPY4:%[0-9]+]]:sreg_64 = COPY $sgpr10_sgpr11
AMDGPU/GlobalISel: Selection for fminnum/fmaxnum v2f16 case doesn't work yet because the VOP3P complex patterns haven't been ported yet. llvm-svn: 366585
2019-07-19 22:42:40 +08:00
; GFX7: [[COPY5:%[0-9]+]]:vreg_64 = COPY $vgpr10_vgpr11
; GFX7: [[COPY6:%[0-9]+]]:vreg_64 = COPY $vgpr12_vgpr13
GlobalISel: Infer nofpexcept flag during selection for non-strict ops Match SelectionDAG's behavior of adding nofpexcept to out instructions that may raise fp exceptions that are selected from instructions that do not.
2020-06-01 02:19:46 +08:00
; GFX7: %7:vgpr_32 = nofpexcept V_MAX_F32_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX7: %8:vgpr_32 = nofpexcept V_MAX_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; GFX7: %9:vgpr_32 = nofpexcept V_MAX_F32_e64 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec
; GFX7: FLAT_STORE_DWORD [[COPY3]], %7, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
; GFX7: FLAT_STORE_DWORD [[COPY3]], %8, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
; GFX7: FLAT_STORE_DWORD [[COPY3]], %9, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
; GFX7: %10:vreg_64 = nofpexcept V_MAX_F64 0, [[COPY4]], 0, [[COPY5]], 0, 0, implicit $mode, implicit $exec
; GFX7: %11:vreg_64 = nofpexcept V_MAX_F64 0, [[COPY5]], 0, [[COPY4]], 0, 0, implicit $mode, implicit $exec
; GFX7: %12:vreg_64 = nofpexcept V_MAX_F64 0, [[COPY5]], 0, [[COPY6]], 0, 0, implicit $mode, implicit $exec
; GFX7: S_ENDPGM 0, implicit %10, implicit %11, implicit %12
AMDGPU/GlobalISel: Selection for fminnum/fmaxnum v2f16 case doesn't work yet because the VOP3P complex patterns haven't been ported yet. llvm-svn: 366585
2019-07-19 22:42:40 +08:00
%0:sgpr(s32) = COPY $sgpr0
%1:vgpr(s32) = COPY $vgpr0
%2:vgpr(s32) = COPY $vgpr1
%3:vgpr(p1) = COPY $vgpr3_vgpr4
%10:sgpr(s64) = COPY $sgpr10_sgpr11
%11:vgpr(s64) = COPY $vgpr10_vgpr11
%12:vgpr(s64) = COPY $vgpr12_vgpr13
; maxnum vs
%4:vgpr(s32) = G_FMAXNUM %1, %0
; maxnum sv
%5:vgpr(s32) = G_FMAXNUM %0, %1
; maxnum vv
%6:vgpr(s32) = G_FMAXNUM %1, %2
G_STORE %4, %3 :: (store 4, addrspace 1)
G_STORE %5, %3 :: (store 4, addrspace 1)
G_STORE %6, %3 :: (store 4, addrspace 1)
; 64-bit
; maxnum vs
%14:vgpr(s64) = G_FMAXNUM %10, %11
; maxnum sv
%15:vgpr(s64) = G_FMAXNUM %11, %10
; maxnum vv
%16:vgpr(s64) = G_FMAXNUM %11, %12
S_ENDPGM 0, implicit %14, implicit %15, implicit %16
...
---
name: fmaxnum_f32_f64_ieee_mode_off
legalized: true
regBankSelected: true
machineFunctionInfo:
mode:
ieee: false
body: |
bb.0:
liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr3_vgpr4, $sgpr10_sgpr11, $vgpr10_vgpr11, $vgpr12_vgpr13
; GFX7-LABEL: name: fmaxnum_f32_f64_ieee_mode_off
AMDGPU: Relax 32-bit SGPR register class Mostly use SReg_32 instead of SReg_32_XM0 for arbitrary values. This will allow the register coalescer to do a better job eliminating copies to m0. For GlobalISel, as a terrible hack, use SGPR_32 for things that should use SCC until booleans are solved. llvm-svn: 375267
2019-10-19 02:26:37 +08:00
; GFX7: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
AMDGPU/GlobalISel: Selection for fminnum/fmaxnum v2f16 case doesn't work yet because the VOP3P complex patterns haven't been ported yet. llvm-svn: 366585
2019-07-19 22:42:40 +08:00
; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX7: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX7: [[COPY3:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4
AMDGPU/GlobalISel: Don't use XEXEC class for SGPRs We don't use the xexec register classes for arbitrary values anymore. Avoids a test variance beween GlobalISel and SelectionDAG>
2020-01-13 06:10:18 +08:00
; GFX7: [[COPY4:%[0-9]+]]:sreg_64 = COPY $sgpr10_sgpr11
AMDGPU/GlobalISel: Selection for fminnum/fmaxnum v2f16 case doesn't work yet because the VOP3P complex patterns haven't been ported yet. llvm-svn: 366585
2019-07-19 22:42:40 +08:00
; GFX7: [[COPY5:%[0-9]+]]:vreg_64 = COPY $vgpr10_vgpr11
; GFX7: [[COPY6:%[0-9]+]]:vreg_64 = COPY $vgpr12_vgpr13
GlobalISel: Infer nofpexcept flag during selection for non-strict ops Match SelectionDAG's behavior of adding nofpexcept to out instructions that may raise fp exceptions that are selected from instructions that do not.
2020-06-01 02:19:46 +08:00
; GFX7: %7:vgpr_32 = nofpexcept V_MAX_F32_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX7: %8:vgpr_32 = nofpexcept V_MAX_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; GFX7: %9:vgpr_32 = nofpexcept V_MAX_F32_e64 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec
; GFX7: FLAT_STORE_DWORD [[COPY3]], %7, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
; GFX7: FLAT_STORE_DWORD [[COPY3]], %8, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
; GFX7: FLAT_STORE_DWORD [[COPY3]], %9, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
; GFX7: %10:vreg_64 = nofpexcept V_MAX_F64 0, [[COPY4]], 0, [[COPY5]], 0, 0, implicit $mode, implicit $exec
; GFX7: %11:vreg_64 = nofpexcept V_MAX_F64 0, [[COPY5]], 0, [[COPY4]], 0, 0, implicit $mode, implicit $exec
; GFX7: %12:vreg_64 = nofpexcept V_MAX_F64 0, [[COPY5]], 0, [[COPY6]], 0, 0, implicit $mode, implicit $exec
; GFX7: S_ENDPGM 0, implicit %10, implicit %11, implicit %12
AMDGPU/GlobalISel: Selection for fminnum/fmaxnum v2f16 case doesn't work yet because the VOP3P complex patterns haven't been ported yet. llvm-svn: 366585
2019-07-19 22:42:40 +08:00
%0:sgpr(s32) = COPY $sgpr0
%1:vgpr(s32) = COPY $vgpr0
%2:vgpr(s32) = COPY $vgpr1
%3:vgpr(p1) = COPY $vgpr3_vgpr4
%10:sgpr(s64) = COPY $sgpr10_sgpr11
%11:vgpr(s64) = COPY $vgpr10_vgpr11
%12:vgpr(s64) = COPY $vgpr12_vgpr13
; maxnum vs
%4:vgpr(s32) = G_FMAXNUM %1, %0
; maxnum sv
%5:vgpr(s32) = G_FMAXNUM %0, %1
; maxnum vv
%6:vgpr(s32) = G_FMAXNUM %1, %2
G_STORE %4, %3 :: (store 4, addrspace 1)
G_STORE %5, %3 :: (store 4, addrspace 1)
G_STORE %6, %3 :: (store 4, addrspace 1)
; 64-bit
; maxnum vs
%14:vgpr(s64) = G_FMAXNUM %10, %11
; maxnum sv
%15:vgpr(s64) = G_FMAXNUM %11, %10
; maxnum vv
%16:vgpr(s64) = G_FMAXNUM %11, %12
S_ENDPGM 0, implicit %14, implicit %15, implicit %16
...