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llvm-project/llvm/docs/AMDGPU/gfx7_vdata1_fd235e.rst

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[AMDGPU][MC][DOC] Updated AMD GPU assembler description Stage 2: added detailed description of operands See bug 36572: https://bugs.llvm.org/show_bug.cgi?id=36572 llvm-svn: 349368
2018-12-18 01:38:11 +08:00
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[AMDGPU][GFX7][DOC][NFC] Update assembler syntax description Summary of changes: - Updated MUBUF lds syntax (see https://reviews.llvm.org/D124485). - Enabled literals with src0 of v_madak_f32, v_madmk_f32 (see https://reviews.llvm.org/D111067). - Corrected LGKM_CNT description. - Minor bug fixing.
2022-06-06 20:50:10 +08:00
.. _amdgpu_synid_gfx7_vdata1_fd235e:
[AMDGPU][MC][DOC] Updated AMD GPU assembler description Stage 2: added detailed description of operands See bug 36572: https://bugs.llvm.org/show_bug.cgi?id=36572 llvm-svn: 349368
2018-12-18 01:38:11 +08:00
[AMDGPU][MC][NFC][DOC] Updated AMD GPU assembler syntax description. Summary of changes: - Added f16 omod modifier (bug 51386). - Corrected names of data types (bug 48638). - Enabled a16 with most GFX10 MIMG opcodes (see https://reviews.llvm.org/D102231). - Corrected description of integer operands (bug 51130). - Corrected description of 8-bit DS offsets (bug 51536). - Improved PERMLANE op_sel description. - Corrected *SAD* opcode types.
2021-08-27 22:16:22 +08:00
vdata1
======
[AMDGPU][MC][DOC] Updated AMD GPU assembler description Stage 2: added detailed description of operands See bug 36572: https://bugs.llvm.org/show_bug.cgi?id=36572 llvm-svn: 349368
2018-12-18 01:38:11 +08:00
Instruction input.
*Size:* 2 dwords.
*Operands:* :ref:`v<amdgpu_synid_v>`