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llvm-project/llvm/lib/Target/Mips/MicroMipsInstrFPU.td

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Support for microMIPS FPU instructions 1. llvm-svn: 197815
2013-12-20 23:44:08 +08:00
let isCodeGenOnly = 1, Predicates = [InMicroMips] in {
[mips][sched] Split IIFadd into II_ADD_[DS], II_SUB_[DS] No functional change since the InstrItinData's have been duplicated. llvm-svn: 199732
2014-01-21 20:38:07 +08:00
def FADD_S_MM : MMRel, ADDS_FT<"add.s", FGR32Opnd, II_ADD_S, 1, fadd>,
Support for microMIPS FPU instructions 1. llvm-svn: 197815
2013-12-20 23:44:08 +08:00
ADDS_FM_MM<0, 0x30>;
[mips][sched] Renamed II_FdivSingle and II_FdivDouble to II_DIV_S and II_DIV_D respectively No functional change llvm-svn: 199738
2014-01-21 21:22:08 +08:00
def FDIV_S_MM : MMRel, ADDS_FT<"div.s", FGR32Opnd, II_DIV_S, 0, fdiv>,
Support for microMIPS FPU instructions 1. llvm-svn: 197815
2013-12-20 23:44:08 +08:00
ADDS_FM_MM<0, 0xf0>;
[mips][sched] Split IIFmulSingle into II_MUL_S, II_MADD_S, II_MSUB_S, II_NMADD_S, and II_NMSUB_S No functional change since the InstrItinData's have been duplicated. llvm-svn: 199734
2014-01-21 20:51:44 +08:00
def FMUL_S_MM : MMRel, ADDS_FT<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>,
Support for microMIPS FPU instructions 1. llvm-svn: 197815
2013-12-20 23:44:08 +08:00
ADDS_FM_MM<0, 0xb0>;
[mips][sched] Split IIFadd into II_ADD_[DS], II_SUB_[DS] No functional change since the InstrItinData's have been duplicated. llvm-svn: 199732
2014-01-21 20:38:07 +08:00
def FSUB_S_MM : MMRel, ADDS_FT<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>,
Support for microMIPS FPU instructions 1. llvm-svn: 197815
2013-12-20 23:44:08 +08:00
ADDS_FM_MM<0, 0x70>;
[mips][sched] Split IIFadd into II_ADD_[DS], II_SUB_[DS] No functional change since the InstrItinData's have been duplicated. llvm-svn: 199732
2014-01-21 20:38:07 +08:00
def FADD_MM : MMRel, ADDS_FT<"add.d", AFGR64Opnd, II_ADD_D, 1, fadd>,
Support for microMIPS FPU instructions 1. llvm-svn: 197815
2013-12-20 23:44:08 +08:00
ADDS_FM_MM<1, 0x30>;
[mips][sched] Renamed II_FdivSingle and II_FdivDouble to II_DIV_S and II_DIV_D respectively No functional change llvm-svn: 199738
2014-01-21 21:22:08 +08:00
def FDIV_MM : MMRel, ADDS_FT<"div.d", AFGR64Opnd, II_DIV_D, 0, fdiv>,
Support for microMIPS FPU instructions 1. llvm-svn: 197815
2013-12-20 23:44:08 +08:00
ADDS_FM_MM<1, 0xf0>;
[mips][sched] Split IIFmulDouble into II_MUL_D, II_MADD_D, II_MSUB_D, II_NMADD_D, and II_NMSUB_S No functional change since the InstrItinData's have been duplicated. llvm-svn: 199737
2014-01-21 21:07:31 +08:00
def FMUL_MM : MMRel, ADDS_FT<"mul.d", AFGR64Opnd, II_MUL_D, 1, fmul>,
Support for microMIPS FPU instructions 1. llvm-svn: 197815
2013-12-20 23:44:08 +08:00
ADDS_FM_MM<1, 0xb0>;
[mips][sched] Split IIFadd into II_ADD_[DS], II_SUB_[DS] No functional change since the InstrItinData's have been duplicated. llvm-svn: 199732
2014-01-21 20:38:07 +08:00
def FSUB_MM : MMRel, ADDS_FT<"sub.d", AFGR64Opnd, II_SUB_D, 0, fsub>,
Support for microMIPS FPU instructions 1. llvm-svn: 197815
2013-12-20 23:44:08 +08:00
ADDS_FM_MM<1, 0x70>;
[mips][sched] Split IIFLoad into II_L[WD]C1, and II_L[WDU]XC1 No functional change since the InstrItinData's have been duplicated. llvm-svn: 199743
2014-01-21 21:59:56 +08:00
def LWC1_MM : MMRel, LW_FT<"lwc1", FGR32Opnd, II_LWC1, load>, LW_FM_MM<0x27>;
[mips][sched] Split IIFStore into II_S[WD]C1, and II_S[WDU]XC1 No functional change since the InstrItinData's have been duplicated. llvm-svn: 199747
2014-01-21 22:50:20 +08:00
def SWC1_MM : MMRel, SW_FT<"swc1", FGR32Opnd, II_SWC1, store>,
Support for microMIPS FPU instructions 1. llvm-svn: 197815
2013-12-20 23:44:08 +08:00
LW_FM_MM<0x26>;
[mips][sched] Split IIFLoad into II_L[WD]C1, and II_L[WDU]XC1 No functional change since the InstrItinData's have been duplicated. llvm-svn: 199743
2014-01-21 21:59:56 +08:00
def LDC1_MM : MMRel, LW_FT<"ldc1", AFGR64Opnd, II_LDC1, load>, LW_FM_MM<0x2f>;
[mips][sched] Split IIFStore into II_S[WD]C1, and II_S[WDU]XC1 No functional change since the InstrItinData's have been duplicated. llvm-svn: 199747
2014-01-21 22:50:20 +08:00
def SDC1_MM : MMRel, SW_FT<"sdc1", AFGR64Opnd, II_SDC1, store>,
Support for microMIPS FPU instructions 1. llvm-svn: 197815
2013-12-20 23:44:08 +08:00
LW_FM_MM<0x2e>;
[mips][sched] Split IIFLoad into II_L[WD]C1, and II_L[WDU]XC1 No functional change since the InstrItinData's have been duplicated. llvm-svn: 199743
2014-01-21 21:59:56 +08:00
def LWXC1_MM : MMRel, LWXC1_FT<"lwxc1", FGR32Opnd, II_LWXC1, load>,
[mips][mips64r6] [sl][duw]xc1 are not available on MIPS32r6/MIPS64r6 Summary: Folded mips64-fp-indexed-ls.ll into fp-indexed-ls.ll. To do so, the zext's in mips64-fp-indexed-ls.ll were changed to implicit sign extensions (performed by getelementptr). This does not affect the purpose of the test. Depends on D4004 Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4110 llvm-svn: 210784
2014-06-12 22:19:28 +08:00
LWXC1_FM_MM<0x48>, INSN_MIPS4_32R2_NOT_32R6_64R6;
[mips][sched] Split IIFStore into II_S[WD]C1, and II_S[WDU]XC1 No functional change since the InstrItinData's have been duplicated. llvm-svn: 199747
2014-01-21 22:50:20 +08:00
def SWXC1_MM : MMRel, SWXC1_FT<"swxc1", FGR32Opnd, II_SWXC1, store>,
[mips][mips64r6] [sl][duw]xc1 are not available on MIPS32r6/MIPS64r6 Summary: Folded mips64-fp-indexed-ls.ll into fp-indexed-ls.ll. To do so, the zext's in mips64-fp-indexed-ls.ll were changed to implicit sign extensions (performed by getelementptr). This does not affect the purpose of the test. Depends on D4004 Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4110 llvm-svn: 210784
2014-06-12 22:19:28 +08:00
SWXC1_FM_MM<0x88>, INSN_MIPS4_32R2_NOT_32R6_64R6;
[mips][sched] Split IIFLoad into II_L[WD]C1, and II_L[WDU]XC1 No functional change since the InstrItinData's have been duplicated. llvm-svn: 199743
2014-01-21 21:59:56 +08:00
def LUXC1_MM : MMRel, LWXC1_FT<"luxc1", AFGR64Opnd, II_LUXC1>,
[mips][mips64r6] [sl][duw]xc1 are not available on MIPS32r6/MIPS64r6 Summary: Folded mips64-fp-indexed-ls.ll into fp-indexed-ls.ll. To do so, the zext's in mips64-fp-indexed-ls.ll were changed to implicit sign extensions (performed by getelementptr). This does not affect the purpose of the test. Depends on D4004 Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4110 llvm-svn: 210784
2014-06-12 22:19:28 +08:00
LWXC1_FM_MM<0x148>, INSN_MIPS5_32R2_NOT_32R6_64R6;
[mips][sched] Split IIFStore into II_S[WD]C1, and II_S[WDU]XC1 No functional change since the InstrItinData's have been duplicated. llvm-svn: 199747
2014-01-21 22:50:20 +08:00
def SUXC1_MM : MMRel, SWXC1_FT<"suxc1", AFGR64Opnd, II_SUXC1>,
[mips][mips64r6] [sl][duw]xc1 are not available on MIPS32r6/MIPS64r6 Summary: Folded mips64-fp-indexed-ls.ll into fp-indexed-ls.ll. To do so, the zext's in mips64-fp-indexed-ls.ll were changed to implicit sign extensions (performed by getelementptr). This does not affect the purpose of the test. Depends on D4004 Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4110 llvm-svn: 210784
2014-06-12 22:19:28 +08:00
SWXC1_FM_MM<0x188>, INSN_MIPS5_32R2_NOT_32R6_64R6;
Support for microMIPS FPU instructions 1. llvm-svn: 197815
2013-12-20 23:44:08 +08:00
[mips][sched] Split IIFcmp into II_C_CC_[SD] No functional change since the InstrItinData's have been duplicated. llvm-svn: 199728
2014-01-21 19:42:48 +08:00
def FCMP_S32_MM : MMRel, CEQS_FT<"s", FGR32, II_C_CC_S, MipsFPCmp>,
Support for microMIPS FPU instructions 1. llvm-svn: 197815
2013-12-20 23:44:08 +08:00
CEQS_FM_MM<0>;
[mips][sched] Split IIFcmp into II_C_CC_[SD] No functional change since the InstrItinData's have been duplicated. llvm-svn: 199728
2014-01-21 19:42:48 +08:00
def FCMP_D32_MM : MMRel, CEQS_FT<"d", AFGR64, II_C_CC_D, MipsFPCmp>,
Support for microMIPS FPU instructions 1. llvm-svn: 197815
2013-12-20 23:44:08 +08:00
CEQS_FM_MM<1>;
def BC1F_MM : MMRel, BC1F_FT<"bc1f", brtarget_mm, IIBranch, MIPS_BRANCH_F>,
[mips][mips64r6] bc1[tf] are not available on MIPS32r6/MIPS64r6 Summary: Also tightened up the acceptable condition operand for these instructions on MIPS-I to MIPS-III. Support for $fcc[1-7] was added in MIPS-IV. Prior to that only $fcc0 is acceptable. We currently don't optimize (BEQZ (NOT $a), $target) and similar. It's probably best to do this in InstCombine. Depends on D4111 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4112 llvm-svn: 210787
2014-06-12 23:00:17 +08:00
BC1F_FM_MM<0x1c>, ISA_MIPS1_NOT_32R6_64R6;
Support for microMIPS FPU instructions 1. llvm-svn: 197815
2013-12-20 23:44:08 +08:00
def BC1T_MM : MMRel, BC1F_FT<"bc1t", brtarget_mm, IIBranch, MIPS_BRANCH_T>,
[mips][mips64r6] bc1[tf] are not available on MIPS32r6/MIPS64r6 Summary: Also tightened up the acceptable condition operand for these instructions on MIPS-I to MIPS-III. Support for $fcc[1-7] was added in MIPS-IV. Prior to that only $fcc0 is acceptable. We currently don't optimize (BEQZ (NOT $a), $target) and similar. It's probably best to do this in InstCombine. Depends on D4111 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4112 llvm-svn: 210787
2014-06-12 23:00:17 +08:00
BC1F_FM_MM<0x1d>, ISA_MIPS1_NOT_32R6_64R6;
Support for microMIPS FPU instructions 1. llvm-svn: 197815
2013-12-20 23:44:08 +08:00
[mips][sched] Split IIFcvt into II_(ROUND|TRUNC|CEIL|FLOOR|CVT), II_ABS, II_NEG No functional change since the InstrItinData's have been duplicated. llvm-svn: 199722
2014-01-21 18:56:23 +08:00
def CEIL_W_S_MM : MMRel, ABSS_FT<"ceil.w.s", FGR32Opnd, FGR32Opnd, II_CEIL>,
Support for microMIPS FPU instructions 1. llvm-svn: 197815
2013-12-20 23:44:08 +08:00
ROUND_W_FM_MM<0, 0x6c>;
[mips][sched] Split IIFcvt into II_(ROUND|TRUNC|CEIL|FLOOR|CVT), II_ABS, II_NEG No functional change since the InstrItinData's have been duplicated. llvm-svn: 199722
2014-01-21 18:56:23 +08:00
def CVT_W_S_MM : MMRel, ABSS_FT<"cvt.w.s", FGR32Opnd, FGR32Opnd, II_CVT>,
Support for microMIPS FPU instructions 1. llvm-svn: 197815
2013-12-20 23:44:08 +08:00
ROUND_W_FM_MM<0, 0x24>;
[mips][sched] Split IIFcvt into II_(ROUND|TRUNC|CEIL|FLOOR|CVT), II_ABS, II_NEG No functional change since the InstrItinData's have been duplicated. llvm-svn: 199722
2014-01-21 18:56:23 +08:00
def FLOOR_W_S_MM : MMRel, ABSS_FT<"floor.w.s", FGR32Opnd, FGR32Opnd, II_FLOOR>,
Support for microMIPS FPU instructions 1. llvm-svn: 197815
2013-12-20 23:44:08 +08:00
ROUND_W_FM_MM<0, 0x2c>;
[mips][sched] Split IIFcvt into II_(ROUND|TRUNC|CEIL|FLOOR|CVT), II_ABS, II_NEG No functional change since the InstrItinData's have been duplicated. llvm-svn: 199722
2014-01-21 18:56:23 +08:00
def ROUND_W_S_MM : MMRel, ABSS_FT<"round.w.s", FGR32Opnd, FGR32Opnd, II_ROUND>,
Support for microMIPS FPU instructions 1. llvm-svn: 197815
2013-12-20 23:44:08 +08:00
ROUND_W_FM_MM<0, 0xec>;
[mips][sched] Split IIFcvt into II_(ROUND|TRUNC|CEIL|FLOOR|CVT), II_ABS, II_NEG No functional change since the InstrItinData's have been duplicated. llvm-svn: 199722
2014-01-21 18:56:23 +08:00
def TRUNC_W_S_MM : MMRel, ABSS_FT<"trunc.w.s", FGR32Opnd, FGR32Opnd, II_TRUNC>,
Support for microMIPS FPU instructions 1. llvm-svn: 197815
2013-12-20 23:44:08 +08:00
ROUND_W_FM_MM<0, 0xac>;
[mips][sched] Renamed II_FsqrtSingle and II_FsqrtDouble to II_SQRT_S and II_SQRT_D respectively No functional change llvm-svn: 199741
2014-01-21 21:36:45 +08:00
def FSQRT_S_MM : MMRel, ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd, II_SQRT_S,
Support for microMIPS FPU instructions 1. llvm-svn: 197815
2013-12-20 23:44:08 +08:00
fsqrt>, ROUND_W_FM_MM<0, 0x28>;
[mips][sched] Split IIFcvt into II_(ROUND|TRUNC|CEIL|FLOOR|CVT), II_ABS, II_NEG No functional change since the InstrItinData's have been duplicated. llvm-svn: 199722
2014-01-21 18:56:23 +08:00
def CEIL_W_MM : MMRel, ABSS_FT<"ceil.w.d", FGR32Opnd, AFGR64Opnd, II_CEIL>,
Support for microMIPS FPU instructions 1. llvm-svn: 197815
2013-12-20 23:44:08 +08:00
ROUND_W_FM_MM<1, 0x6c>;
[mips][sched] Split IIFcvt into II_(ROUND|TRUNC|CEIL|FLOOR|CVT), II_ABS, II_NEG No functional change since the InstrItinData's have been duplicated. llvm-svn: 199722
2014-01-21 18:56:23 +08:00
def CVT_W_MM : MMRel, ABSS_FT<"cvt.w.d", FGR32Opnd, AFGR64Opnd, II_CVT>,
Support for microMIPS FPU instructions 1. llvm-svn: 197815
2013-12-20 23:44:08 +08:00
ROUND_W_FM_MM<1, 0x24>;
[mips][sched] Split IIFcvt into II_(ROUND|TRUNC|CEIL|FLOOR|CVT), II_ABS, II_NEG No functional change since the InstrItinData's have been duplicated. llvm-svn: 199722
2014-01-21 18:56:23 +08:00
def FLOOR_W_MM : MMRel, ABSS_FT<"floor.w.d", FGR32Opnd, AFGR64Opnd, II_FLOOR>,
Support for microMIPS FPU instructions 1. llvm-svn: 197815
2013-12-20 23:44:08 +08:00
ROUND_W_FM_MM<1, 0x2c>;
[mips][sched] Split IIFcvt into II_(ROUND|TRUNC|CEIL|FLOOR|CVT), II_ABS, II_NEG No functional change since the InstrItinData's have been duplicated. llvm-svn: 199722
2014-01-21 18:56:23 +08:00
def ROUND_W_MM : MMRel, ABSS_FT<"round.w.d", FGR32Opnd, AFGR64Opnd, II_ROUND>,
Support for microMIPS FPU instructions 1. llvm-svn: 197815
2013-12-20 23:44:08 +08:00
ROUND_W_FM_MM<1, 0xec>;
[mips][sched] Split IIFcvt into II_(ROUND|TRUNC|CEIL|FLOOR|CVT), II_ABS, II_NEG No functional change since the InstrItinData's have been duplicated. llvm-svn: 199722
2014-01-21 18:56:23 +08:00
def TRUNC_W_MM : MMRel, ABSS_FT<"trunc.w.d", FGR32Opnd, AFGR64Opnd, II_TRUNC>,
Support for microMIPS FPU instructions 1. llvm-svn: 197815
2013-12-20 23:44:08 +08:00
ROUND_W_FM_MM<1, 0xac>;
[mips][sched] Renamed II_FsqrtSingle and II_FsqrtDouble to II_SQRT_S and II_SQRT_D respectively No functional change llvm-svn: 199741
2014-01-21 21:36:45 +08:00
def FSQRT_MM : MMRel, ABSS_FT<"sqrt.d", AFGR64Opnd, AFGR64Opnd, II_SQRT_D,
fsqrt>, ROUND_W_FM_MM<1, 0x28>;
Support for microMIPS FPU instructions 1. llvm-svn: 197815
2013-12-20 23:44:08 +08:00
[mips][sched] Split IIFcvt into II_(ROUND|TRUNC|CEIL|FLOOR|CVT), II_ABS, II_NEG No functional change since the InstrItinData's have been duplicated. llvm-svn: 199722
2014-01-21 18:56:23 +08:00
def CVT_L_S_MM : MMRel, ABSS_FT<"cvt.l.s", FGR64Opnd, FGR32Opnd, II_CVT>,
[mips] Marked up instructions added in MIPS32r2 and tested that IAS for -mcpu=mips(2|32) does not accept them Summary: This required a new instruction group representing the 32-bit subset of MIPS-3 that was available in MIPS32R2. To limit the number of tests required, only one 32-bit and one 64-bit ISA prior to MIPS32/MIPS64 are tested. rdhwr has been deliberately left without an ISA annotation for now. This is because the assembler and CodeGen disagree on when the instruction is available. Strictly speaking, it is only available in MIPS32r2 and MIPS64r2. However, it is emulated by a kernel trap on earlier ISA's and is necessary for TLS so CodeGen should emit it on older ISA's too. Depends on D3696 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3697 llvm-svn: 208690
2014-05-13 19:45:36 +08:00
ROUND_W_FM_MM<0, 0x4>, INSN_MIPS3_32R2;
[mips][sched] Split IIFcvt into II_(ROUND|TRUNC|CEIL|FLOOR|CVT), II_ABS, II_NEG No functional change since the InstrItinData's have been duplicated. llvm-svn: 199722
2014-01-21 18:56:23 +08:00
def CVT_L_D64_MM : MMRel, ABSS_FT<"cvt.l.d", FGR64Opnd, FGR64Opnd, II_CVT>,
[mips] Marked up instructions added in MIPS32r2 and tested that IAS for -mcpu=mips(2|32) does not accept them Summary: This required a new instruction group representing the 32-bit subset of MIPS-3 that was available in MIPS32R2. To limit the number of tests required, only one 32-bit and one 64-bit ISA prior to MIPS32/MIPS64 are tested. rdhwr has been deliberately left without an ISA annotation for now. This is because the assembler and CodeGen disagree on when the instruction is available. Strictly speaking, it is only available in MIPS32r2 and MIPS64r2. However, it is emulated by a kernel trap on earlier ISA's and is necessary for TLS so CodeGen should emit it on older ISA's too. Depends on D3696 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3697 llvm-svn: 208690
2014-05-13 19:45:36 +08:00
ROUND_W_FM_MM<1, 0x4>, INSN_MIPS3_32R2;
Support for microMIPS FPU instructions 1. llvm-svn: 197815
2013-12-20 23:44:08 +08:00
[mips][sched] Split IIFcvt into II_(ROUND|TRUNC|CEIL|FLOOR|CVT), II_ABS, II_NEG No functional change since the InstrItinData's have been duplicated. llvm-svn: 199722
2014-01-21 18:56:23 +08:00
def FABS_S_MM : MMRel, ABSS_FT<"abs.s", FGR32Opnd, FGR32Opnd, II_ABS, fabs>,
Support for microMIPS FPU instructions 1. llvm-svn: 197815
2013-12-20 23:44:08 +08:00
ABS_FM_MM<0, 0xd>;
[mips][sched] Split IIFmove into II_C[FT]C1, II_MOV[FNTZ]_[SD], II_MOV_[SD] No functional change since the InstrItinData's have been duplicated. llvm-svn: 199727
2014-01-21 19:28:03 +08:00
def FMOV_S_MM : MMRel, ABSS_FT<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>,
Support for microMIPS FPU instructions 1. llvm-svn: 197815
2013-12-20 23:44:08 +08:00
ABS_FM_MM<0, 0x1>;
[mips][sched] Split IIFcvt into II_(ROUND|TRUNC|CEIL|FLOOR|CVT), II_ABS, II_NEG No functional change since the InstrItinData's have been duplicated. llvm-svn: 199722
2014-01-21 18:56:23 +08:00
def FNEG_S_MM : MMRel, ABSS_FT<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>,
Support for microMIPS FPU instructions 1. llvm-svn: 197815
2013-12-20 23:44:08 +08:00
ABS_FM_MM<0, 0x2d>;
[mips][sched] Split IIFcvt into II_(ROUND|TRUNC|CEIL|FLOOR|CVT), II_ABS, II_NEG No functional change since the InstrItinData's have been duplicated. llvm-svn: 199722
2014-01-21 18:56:23 +08:00
def CVT_D_S_MM : MMRel, ABSS_FT<"cvt.d.s", AFGR64Opnd, FGR32Opnd, II_CVT>,
Support for microMIPS FPU instructions 1. llvm-svn: 197815
2013-12-20 23:44:08 +08:00
ABS_FM_MM<0, 0x4d>;
[mips][sched] Split IIFcvt into II_(ROUND|TRUNC|CEIL|FLOOR|CVT), II_ABS, II_NEG No functional change since the InstrItinData's have been duplicated. llvm-svn: 199722
2014-01-21 18:56:23 +08:00
def CVT_D32_W_MM : MMRel, ABSS_FT<"cvt.d.w", AFGR64Opnd, FGR32Opnd, II_CVT>,
Support for microMIPS FPU instructions 1. llvm-svn: 197815
2013-12-20 23:44:08 +08:00
ABS_FM_MM<1, 0x4d>;
[mips][sched] Split IIFcvt into II_(ROUND|TRUNC|CEIL|FLOOR|CVT), II_ABS, II_NEG No functional change since the InstrItinData's have been duplicated. llvm-svn: 199722
2014-01-21 18:56:23 +08:00
def CVT_S_D32_MM : MMRel, ABSS_FT<"cvt.s.d", FGR32Opnd, AFGR64Opnd, II_CVT>,
Support for microMIPS FPU instructions 1. llvm-svn: 197815
2013-12-20 23:44:08 +08:00
ABS_FM_MM<0, 0x6d>;
[mips][sched] Split IIFcvt into II_(ROUND|TRUNC|CEIL|FLOOR|CVT), II_ABS, II_NEG No functional change since the InstrItinData's have been duplicated. llvm-svn: 199722
2014-01-21 18:56:23 +08:00
def CVT_S_W_MM : MMRel, ABSS_FT<"cvt.s.w", FGR32Opnd, FGR32Opnd, II_CVT>,
Support for microMIPS FPU instructions 1. llvm-svn: 197815
2013-12-20 23:44:08 +08:00
ABS_FM_MM<1, 0x6d>;
[mips][sched] Split IIFcvt into II_(ROUND|TRUNC|CEIL|FLOOR|CVT), II_ABS, II_NEG No functional change since the InstrItinData's have been duplicated. llvm-svn: 199722
2014-01-21 18:56:23 +08:00
def FABS_MM : MMRel, ABSS_FT<"abs.d", AFGR64Opnd, AFGR64Opnd, II_ABS, fabs>,
Support for microMIPS FPU instructions 1. llvm-svn: 197815
2013-12-20 23:44:08 +08:00
ABS_FM_MM<1, 0xd>;
[mips][sched] Split IIFcvt into II_(ROUND|TRUNC|CEIL|FLOOR|CVT), II_ABS, II_NEG No functional change since the InstrItinData's have been duplicated. llvm-svn: 199722
2014-01-21 18:56:23 +08:00
def FNEG_MM : MMRel, ABSS_FT<"neg.d", AFGR64Opnd, AFGR64Opnd, II_NEG, fneg>,
Support for microMIPS FPU instructions 1. llvm-svn: 197815
2013-12-20 23:44:08 +08:00
ABS_FM_MM<1, 0x2d>;
[mips][sched] Split IIFmove into II_C[FT]C1, II_MOV[FNTZ]_[SD], II_MOV_[SD] No functional change since the InstrItinData's have been duplicated. llvm-svn: 199727
2014-01-21 19:28:03 +08:00
def FMOV_D32_MM : MMRel, ABSS_FT<"mov.d", AFGR64Opnd, AFGR64Opnd, II_MOV_D>,
[mips] Split Instruction.Predicates into smaller lists and re-join them with !listconcat Summary: The overall idea is to chop the Predicates list into subsets that are usually overridden independently. This allows subclasses to partially override the predicates of their superclasses without having to re-add all the existing predicates. This patch starts the process by moving HasStdEnc into a new EncodingPredicates list and almost everything else into AdditionalPredicates. It has revealed a couple likely bugs where 'let Predicates' has removed the HasStdEnc predicate. No functional change (confirmed by diffing tablegen-erated files). Depends on D3549, D3506 Reviewers: vmedic Differential Revision: http://reviews.llvm.org/D3550 llvm-svn: 208184
2014-05-07 18:27:09 +08:00
ABS_FM_MM<1, 0x1>, AdditionalRequires<[NotFP64bit]>;
Support for microMIPS FPU instructions 2. llvm-svn: 198009
2013-12-25 18:09:27 +08:00
[mips][sched] Split IIFmove into II_C[FT]C1, II_MOV[FNTZ]_[SD], II_MOV_[SD] No functional change since the InstrItinData's have been duplicated. llvm-svn: 199727
2014-01-21 19:28:03 +08:00
def MOVZ_I_S_MM : MMRel, CMov_I_F_FT<"movz.s", GPR32Opnd, FGR32Opnd,
II_MOVZ_S>, CMov_I_F_FM_MM<0x78, 0>;
def MOVN_I_S_MM : MMRel, CMov_I_F_FT<"movn.s", GPR32Opnd, FGR32Opnd,
II_MOVN_S>, CMov_I_F_FM_MM<0x38, 0>;
Support for microMIPS FPU instructions 2. llvm-svn: 198009
2013-12-25 18:09:27 +08:00
def MOVZ_I_D32_MM : MMRel, CMov_I_F_FT<"movz.d", GPR32Opnd, AFGR64Opnd,
[mips][sched] Split IIFmove into II_C[FT]C1, II_MOV[FNTZ]_[SD], II_MOV_[SD] No functional change since the InstrItinData's have been duplicated. llvm-svn: 199727
2014-01-21 19:28:03 +08:00
II_MOVZ_D>, CMov_I_F_FM_MM<0x78, 1>;
Support for microMIPS FPU instructions 2. llvm-svn: 198009
2013-12-25 18:09:27 +08:00
def MOVN_I_D32_MM : MMRel, CMov_I_F_FT<"movn.d", GPR32Opnd, AFGR64Opnd,
[mips][sched] Split IIFmove into II_C[FT]C1, II_MOV[FNTZ]_[SD], II_MOV_[SD] No functional change since the InstrItinData's have been duplicated. llvm-svn: 199727
2014-01-21 19:28:03 +08:00
II_MOVN_D>, CMov_I_F_FM_MM<0x38, 1>;
Support for microMIPS FPU instructions 2. llvm-svn: 198009
2013-12-25 18:09:27 +08:00
[mips][sched] Split IIFmove into II_C[FT]C1, II_MOV[FNTZ]_[SD], II_MOV_[SD] No functional change since the InstrItinData's have been duplicated. llvm-svn: 199727
2014-01-21 19:28:03 +08:00
def MOVT_S_MM : MMRel, CMov_F_F_FT<"movt.s", FGR32Opnd, II_MOVT_S,
MipsCMovFP_T>, CMov_F_F_FM_MM<0x60, 0>;
def MOVF_S_MM : MMRel, CMov_F_F_FT<"movf.s", FGR32Opnd, II_MOVF_S,
MipsCMovFP_F>, CMov_F_F_FM_MM<0x20, 0>;
def MOVT_D32_MM : MMRel, CMov_F_F_FT<"movt.d", AFGR64Opnd, II_MOVT_D,
MipsCMovFP_T>, CMov_F_F_FM_MM<0x60, 1>;
def MOVF_D32_MM : MMRel, CMov_F_F_FT<"movf.d", AFGR64Opnd, II_MOVF_D,
MipsCMovFP_F>, CMov_F_F_FM_MM<0x20, 1>;
Support for microMIPS FPU instructions 2. llvm-svn: 198009
2013-12-25 18:09:27 +08:00
[mips][sched] Split IIFmove into II_C[FT]C1, II_MOV[FNTZ]_[SD], II_MOV_[SD] No functional change since the InstrItinData's have been duplicated. llvm-svn: 199727
2014-01-21 19:28:03 +08:00
def CFC1_MM : MMRel, MFC1_FT<"cfc1", GPR32Opnd, CCROpnd, II_CFC1>,
Support for microMIPS FPU instructions 2. llvm-svn: 198009
2013-12-25 18:09:27 +08:00
MFC1_FM_MM<0x40>;
[mips][sched] Split IIFmove into II_C[FT]C1, II_MOV[FNTZ]_[SD], II_MOV_[SD] No functional change since the InstrItinData's have been duplicated. llvm-svn: 199727
2014-01-21 19:28:03 +08:00
def CTC1_MM : MMRel, MTC1_FT<"ctc1", CCROpnd, GPR32Opnd, II_CTC1>,
Support for microMIPS FPU instructions 2. llvm-svn: 198009
2013-12-25 18:09:27 +08:00
MFC1_FM_MM<0x60>;
def MFC1_MM : MMRel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd,
[mips][sched] Split IIFmoveC1 into II_M[FT]C1, II_M[FT]HC1, II_DM[FT]C1 No functional change since the InstrItinData's have been duplicated. llvm-svn: 199748
2014-01-21 23:03:52 +08:00
II_MFC1, bitconvert>, MFC1_FM_MM<0x80>;
Support for microMIPS FPU instructions 2. llvm-svn: 198009
2013-12-25 18:09:27 +08:00
def MTC1_MM : MMRel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd,
[mips][sched] Split IIFmoveC1 into II_M[FT]C1, II_M[FT]HC1, II_DM[FT]C1 No functional change since the InstrItinData's have been duplicated. llvm-svn: 199748
2014-01-21 23:03:52 +08:00
II_MTC1, bitconvert>, MFC1_FM_MM<0xa0>;
def MFHC1_MM : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, FGRH32Opnd, II_MFHC1>,
[mips] Marked up instructions added in MIPS32r2 and tested that IAS for -mcpu=mips(2|32) does not accept them Summary: This required a new instruction group representing the 32-bit subset of MIPS-3 that was available in MIPS32R2. To limit the number of tests required, only one 32-bit and one 64-bit ISA prior to MIPS32/MIPS64 are tested. rdhwr has been deliberately left without an ISA annotation for now. This is because the assembler and CodeGen disagree on when the instruction is available. Strictly speaking, it is only available in MIPS32r2 and MIPS64r2. However, it is emulated by a kernel trap on earlier ISA's and is necessary for TLS so CodeGen should emit it on older ISA's too. Depends on D3696 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3697 llvm-svn: 208690
2014-05-13 19:45:36 +08:00
MFC1_FM_MM<3>, ISA_MIPS32R2;
[mips][sched] Split IIFmoveC1 into II_M[FT]C1, II_M[FT]HC1, II_DM[FT]C1 No functional change since the InstrItinData's have been duplicated. llvm-svn: 199748
2014-01-21 23:03:52 +08:00
def MTHC1_MM : MMRel, MTC1_FT<"mthc1", FGRH32Opnd, GPR32Opnd, II_MTHC1>,
[mips] Marked up instructions added in MIPS32r2 and tested that IAS for -mcpu=mips(2|32) does not accept them Summary: This required a new instruction group representing the 32-bit subset of MIPS-3 that was available in MIPS32R2. To limit the number of tests required, only one 32-bit and one 64-bit ISA prior to MIPS32/MIPS64 are tested. rdhwr has been deliberately left without an ISA annotation for now. This is because the assembler and CodeGen disagree on when the instruction is available. Strictly speaking, it is only available in MIPS32r2 and MIPS64r2. However, it is emulated by a kernel trap on earlier ISA's and is necessary for TLS so CodeGen should emit it on older ISA's too. Depends on D3696 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3697 llvm-svn: 208690
2014-05-13 19:45:36 +08:00
MFC1_FM_MM<7>, ISA_MIPS32R2;
Support for microMIPS FPU instructions 2. llvm-svn: 198009
2013-12-25 18:09:27 +08:00
[mips][sched] Split IIFmulSingle into II_MUL_S, II_MADD_S, II_MSUB_S, II_NMADD_S, and II_NMSUB_S No functional change since the InstrItinData's have been duplicated. llvm-svn: 199734
2014-01-21 20:51:44 +08:00
def MADD_S_MM : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S, fadd>,
Support for microMIPS FPU instructions 2. llvm-svn: 198009
2013-12-25 18:09:27 +08:00
MADDS_FM_MM<0x1>;
[mips][sched] Split IIFmulSingle into II_MUL_S, II_MADD_S, II_MSUB_S, II_NMADD_S, and II_NMSUB_S No functional change since the InstrItinData's have been duplicated. llvm-svn: 199734
2014-01-21 20:51:44 +08:00
def MSUB_S_MM : MMRel, MADDS_FT<"msub.s", FGR32Opnd, II_MSUB_S, fsub>,
Support for microMIPS FPU instructions 2. llvm-svn: 198009
2013-12-25 18:09:27 +08:00
MADDS_FM_MM<0x21>;
[mips][sched] Split IIFmulSingle into II_MUL_S, II_MADD_S, II_MSUB_S, II_NMADD_S, and II_NMSUB_S No functional change since the InstrItinData's have been duplicated. llvm-svn: 199734
2014-01-21 20:51:44 +08:00
def NMADD_S_MM : MMRel, NMADDS_FT<"nmadd.s", FGR32Opnd, II_NMADD_S, fadd>,
Support for microMIPS FPU instructions 2. llvm-svn: 198009
2013-12-25 18:09:27 +08:00
MADDS_FM_MM<0x2>;
[mips][sched] Split IIFmulSingle into II_MUL_S, II_MADD_S, II_MSUB_S, II_NMADD_S, and II_NMSUB_S No functional change since the InstrItinData's have been duplicated. llvm-svn: 199734
2014-01-21 20:51:44 +08:00
def NMSUB_S_MM : MMRel, NMADDS_FT<"nmsub.s", FGR32Opnd, II_NMSUB_S, fsub>,
Support for microMIPS FPU instructions 2. llvm-svn: 198009
2013-12-25 18:09:27 +08:00
MADDS_FM_MM<0x22>;
[mips][sched] Split IIFmulDouble into II_MUL_D, II_MADD_D, II_MSUB_D, II_NMADD_D, and II_NMSUB_S No functional change since the InstrItinData's have been duplicated. llvm-svn: 199737
2014-01-21 21:07:31 +08:00
def MADD_D32_MM : MMRel, MADDS_FT<"madd.d", AFGR64Opnd, II_MADD_D, fadd>,
Support for microMIPS FPU instructions 2. llvm-svn: 198009
2013-12-25 18:09:27 +08:00
MADDS_FM_MM<0x9>;
[mips][sched] Split IIFmulDouble into II_MUL_D, II_MADD_D, II_MSUB_D, II_NMADD_D, and II_NMSUB_S No functional change since the InstrItinData's have been duplicated. llvm-svn: 199737
2014-01-21 21:07:31 +08:00
def MSUB_D32_MM : MMRel, MADDS_FT<"msub.d", AFGR64Opnd, II_MSUB_D, fsub>,
Support for microMIPS FPU instructions 2. llvm-svn: 198009
2013-12-25 18:09:27 +08:00
MADDS_FM_MM<0x29>;
[mips][sched] Split IIFmulDouble into II_MUL_D, II_MADD_D, II_MSUB_D, II_NMADD_D, and II_NMSUB_S No functional change since the InstrItinData's have been duplicated. llvm-svn: 199737
2014-01-21 21:07:31 +08:00
def NMADD_D32_MM : MMRel, NMADDS_FT<"nmadd.d", AFGR64Opnd, II_NMADD_D, fadd>,
MADDS_FM_MM<0xa>;
def NMSUB_D32_MM : MMRel, NMADDS_FT<"nmsub.d", AFGR64Opnd, II_NMSUB_D, fsub>,
MADDS_FM_MM<0x2a>;
Support for microMIPS FPU instructions 1. llvm-svn: 197815
2013-12-20 23:44:08 +08:00
}