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llvm-project/llvm/test/CodeGen/R600/fneg.ll

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R600: Expand vector FNEG llvm-svn: 186913
2013-07-23 09:47:46 +08:00
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
; CHECK: @fneg_v2
DAGCombiner: Pass the correct type to TargetLowering::isF(Abs|Neg)Free This commit also implements these functions for R600 and removes a test case that was relying on the buggy behavior. llvm-svn: 187007
2013-07-24 07:55:03 +08:00
; CHECK: -PV
; CHECK: -PV
R600: Expand vector FNEG llvm-svn: 186913
2013-07-23 09:47:46 +08:00
define void @fneg_v2(<2 x float> addrspace(1)* nocapture %out, <2 x float> %in) {
entry:
%0 = fsub <2 x float> <float -0.000000e+00, float -0.000000e+00>, %in
store <2 x float> %0, <2 x float> addrspace(1)* %out
ret void
}
R600/SI: Use S_LOAD_DWORD instructions for v8i32 and v16i32 llvm-svn: 193212
2013-10-23 08:44:12 +08:00
; R600-CHECK-LABEL: @fneg_v4
; R600-CHECK: -PV
; R600-CHECK: -T
; R600-CHECK: -PV
; R600-CHECK: -PV
; SI-CHECK-LABEL: @fneg_v4
R600/SI: Change formatting of printed registers. Print the range of registers used with a single letter prefix. This better matches what the shader compiler produces and is overall less obnoxious than concatenating all of the subregister names together. Instead of SGPR0, it will print s0. Instead of SGPR0_SGPR1, it will print s[0:1] and so on. There doesn't appear to be a straightforward way to get the actual register info in the InstPrinter, so this parses the generated name to print with the new syntax. The required test changes are pretty nasty, and register matching regexes are now worse. Since there isn't a way to add to a variable in FileCheck, some of the tests now don't check the exact number of registers used, but I don't think that will be a real problem. llvm-svn: 194443
2013-11-12 10:35:51 +08:00
; SI-CHECK: V_ADD_F32_e64 v{{[0-9]}}, s{{[0-9]}}, 0, 0, 0, 0, 1
; SI-CHECK: V_ADD_F32_e64 v{{[0-9]}}, s{{[0-9]}}, 0, 0, 0, 0, 1
; SI-CHECK: V_ADD_F32_e64 v{{[0-9]}}, s{{[0-9]}}, 0, 0, 0, 0, 1
; SI-CHECK: V_ADD_F32_e64 v{{[0-9]}}, s{{[0-9]}}, 0, 0, 0, 0, 1
R600: Expand vector FNEG llvm-svn: 186913
2013-07-23 09:47:46 +08:00
define void @fneg_v4(<4 x float> addrspace(1)* nocapture %out, <4 x float> %in) {
entry:
%0 = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %in
store <4 x float> %0, <4 x float> addrspace(1)* %out
ret void
}
DAGCombiner: Pass the correct type to TargetLowering::isF(Abs|Neg)Free This commit also implements these functions for R600 and removes a test case that was relying on the buggy behavior. llvm-svn: 187007
2013-07-24 07:55:03 +08:00
; DAGCombiner will transform:
; (fneg (f32 bitcast (i32 a))) => (f32 bitcast (xor (i32 a), 0x80000000))
; unless the target returns true for isNegFree()
; CHECK-NOT: XOR
; CHECK: -KC0[2].Z
define void @fneg_free(float addrspace(1)* %out, i32 %in) {
entry:
%0 = bitcast i32 %in to float
%1 = fsub float 0.0, %0
store float %1, float addrspace(1)* %out
ret void
}