2003-01-14 04:01:16 +08:00
|
|
|
//===-- PhiElimination.cpp - Eliminate PHI nodes by inserting copies ------===//
|
2005-04-22 06:36:52 +08:00
|
|
|
//
|
2003-10-21 03:43:21 +08:00
|
|
|
// The LLVM Compiler Infrastructure
|
|
|
|
//
|
2007-12-30 04:36:04 +08:00
|
|
|
// This file is distributed under the University of Illinois Open Source
|
|
|
|
// License. See LICENSE.TXT for details.
|
2005-04-22 06:36:52 +08:00
|
|
|
//
|
2003-10-21 03:43:21 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
2003-01-14 04:01:16 +08:00
|
|
|
//
|
|
|
|
// This pass eliminates machine instruction PHI nodes by inserting copy
|
|
|
|
// instructions. This destroys SSA information, but is the desired input for
|
|
|
|
// some register allocators.
|
|
|
|
//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
2012-12-04 00:50:05 +08:00
|
|
|
#include "llvm/CodeGen/Passes.h"
|
2010-12-06 03:51:05 +08:00
|
|
|
#include "PHIEliminationUtils.h"
|
2012-12-04 00:50:05 +08:00
|
|
|
#include "llvm/ADT/STLExtras.h"
|
|
|
|
#include "llvm/ADT/SmallPtrSet.h"
|
|
|
|
#include "llvm/ADT/Statistic.h"
|
2013-02-10 14:42:36 +08:00
|
|
|
#include "llvm/CodeGen/LiveIntervalAnalysis.h"
|
2005-05-06 07:45:17 +08:00
|
|
|
#include "llvm/CodeGen/LiveVariables.h"
|
2009-11-14 08:38:06 +08:00
|
|
|
#include "llvm/CodeGen/MachineDominators.h"
|
2003-01-14 04:01:16 +08:00
|
|
|
#include "llvm/CodeGen/MachineInstr.h"
|
2008-04-12 01:54:45 +08:00
|
|
|
#include "llvm/CodeGen/MachineInstrBuilder.h"
|
2010-08-17 09:20:36 +08:00
|
|
|
#include "llvm/CodeGen/MachineLoopInfo.h"
|
2007-12-31 12:13:23 +08:00
|
|
|
#include "llvm/CodeGen/MachineRegisterInfo.h"
|
2013-01-02 19:36:10 +08:00
|
|
|
#include "llvm/IR/Function.h"
|
2011-03-10 13:59:17 +08:00
|
|
|
#include "llvm/Support/CommandLine.h"
|
2006-08-27 20:54:02 +08:00
|
|
|
#include "llvm/Support/Compiler.h"
|
2009-11-11 06:01:05 +08:00
|
|
|
#include "llvm/Support/Debug.h"
|
2015-03-24 03:32:43 +08:00
|
|
|
#include "llvm/Support/raw_ostream.h"
|
2012-12-04 00:50:05 +08:00
|
|
|
#include "llvm/Target/TargetInstrInfo.h"
|
2014-08-05 05:25:23 +08:00
|
|
|
#include "llvm/Target/TargetSubtargetInfo.h"
|
2005-10-03 15:22:07 +08:00
|
|
|
#include <algorithm>
|
2004-02-24 02:38:20 +08:00
|
|
|
using namespace llvm;
|
2003-11-12 06:41:34 +08:00
|
|
|
|
2014-04-22 10:02:50 +08:00
|
|
|
#define DEBUG_TYPE "phielim"
|
|
|
|
|
2011-03-10 13:59:17 +08:00
|
|
|
static cl::opt<bool>
|
|
|
|
DisableEdgeSplitting("disable-phi-elim-edge-splitting", cl::init(false),
|
|
|
|
cl::Hidden, cl::desc("Disable critical edge splitting "
|
|
|
|
"during PHI elimination"));
|
|
|
|
|
2013-02-12 11:49:25 +08:00
|
|
|
static cl::opt<bool>
|
|
|
|
SplitAllCriticalEdges("phi-elim-split-all-critical-edges", cl::init(false),
|
|
|
|
cl::Hidden, cl::desc("Split all critical edges during "
|
|
|
|
"PHI elimination"));
|
|
|
|
|
2015-03-03 18:23:11 +08:00
|
|
|
static cl::opt<bool> NoPhiElimLiveOutEarlyExit(
|
|
|
|
"no-phi-elim-live-out-early-exit", cl::init(false), cl::Hidden,
|
|
|
|
cl::desc("Do not use an early exit if isLiveOutPastPHIs returns true."));
|
|
|
|
|
2010-12-06 05:39:42 +08:00
|
|
|
namespace {
|
|
|
|
class PHIElimination : public MachineFunctionPass {
|
|
|
|
MachineRegisterInfo *MRI; // Machine register information
|
2013-02-10 14:42:30 +08:00
|
|
|
LiveVariables *LV;
|
2013-02-10 14:42:36 +08:00
|
|
|
LiveIntervals *LIS;
|
2010-12-06 05:39:42 +08:00
|
|
|
|
|
|
|
public:
|
|
|
|
static char ID; // Pass identification, replacement for typeid
|
|
|
|
PHIElimination() : MachineFunctionPass(ID) {
|
|
|
|
initializePHIEliminationPass(*PassRegistry::getPassRegistry());
|
|
|
|
}
|
|
|
|
|
2014-03-07 17:26:03 +08:00
|
|
|
bool runOnMachineFunction(MachineFunction &Fn) override;
|
|
|
|
void getAnalysisUsage(AnalysisUsage &AU) const override;
|
2010-12-06 05:39:42 +08:00
|
|
|
|
|
|
|
private:
|
|
|
|
/// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions
|
|
|
|
/// in predecessor basic blocks.
|
|
|
|
///
|
|
|
|
bool EliminatePHINodes(MachineFunction &MF, MachineBasicBlock &MBB);
|
2013-02-10 14:42:32 +08:00
|
|
|
void LowerPHINode(MachineBasicBlock &MBB,
|
2013-07-02 03:42:46 +08:00
|
|
|
MachineBasicBlock::iterator LastPHIIt);
|
2010-12-06 05:39:42 +08:00
|
|
|
|
|
|
|
/// analyzePHINodes - Gather information about the PHI nodes in
|
|
|
|
/// here. In particular, we want to map the number of uses of a virtual
|
|
|
|
/// register which is used in a PHI node. We map that to the BB the
|
|
|
|
/// vreg is coming from. This is used later to determine when the vreg
|
|
|
|
/// is killed in the BB.
|
|
|
|
///
|
|
|
|
void analyzePHINodes(const MachineFunction& Fn);
|
|
|
|
|
|
|
|
/// Split critical edges where necessary for good coalescer performance.
|
|
|
|
bool SplitPHIEdges(MachineFunction &MF, MachineBasicBlock &MBB,
|
2013-02-10 14:42:30 +08:00
|
|
|
MachineLoopInfo *MLI);
|
2010-12-06 05:39:42 +08:00
|
|
|
|
2013-02-11 07:29:49 +08:00
|
|
|
// These functions are temporary abstractions around LiveVariables and
|
|
|
|
// LiveIntervals, so they can go away when LiveVariables does.
|
2015-06-11 15:45:05 +08:00
|
|
|
bool isLiveIn(unsigned Reg, const MachineBasicBlock *MBB);
|
|
|
|
bool isLiveOutPastPHIs(unsigned Reg, const MachineBasicBlock *MBB);
|
2013-02-11 07:29:49 +08:00
|
|
|
|
2010-12-06 05:39:42 +08:00
|
|
|
typedef std::pair<unsigned, unsigned> BBVRegPair;
|
|
|
|
typedef DenseMap<BBVRegPair, unsigned> VRegPHIUse;
|
|
|
|
|
|
|
|
VRegPHIUse VRegPHIUseCount;
|
|
|
|
|
|
|
|
// Defs of PHI sources which are implicit_def.
|
|
|
|
SmallPtrSet<MachineInstr*, 4> ImpDefs;
|
|
|
|
|
|
|
|
// Map reusable lowered PHI node -> incoming join register.
|
|
|
|
typedef DenseMap<MachineInstr*, unsigned,
|
|
|
|
MachineInstrExpressionTrait> LoweredPHIMap;
|
|
|
|
LoweredPHIMap LoweredPHIs;
|
|
|
|
};
|
2015-06-23 17:49:53 +08:00
|
|
|
}
|
2010-12-06 05:39:42 +08:00
|
|
|
|
2013-02-10 14:42:32 +08:00
|
|
|
STATISTIC(NumLowered, "Number of phis lowered");
|
2011-02-14 10:09:11 +08:00
|
|
|
STATISTIC(NumCriticalEdgesSplit, "Number of critical edges split");
|
2009-12-17 02:55:53 +08:00
|
|
|
STATISTIC(NumReused, "Number of reused lowered phis");
|
2009-11-11 06:01:05 +08:00
|
|
|
|
2009-07-22 07:47:33 +08:00
|
|
|
char PHIElimination::ID = 0;
|
2010-12-06 05:39:42 +08:00
|
|
|
char& llvm::PHIEliminationID = PHIElimination::ID;
|
2003-01-14 04:01:16 +08:00
|
|
|
|
2012-02-10 12:10:36 +08:00
|
|
|
INITIALIZE_PASS_BEGIN(PHIElimination, "phi-node-elimination",
|
|
|
|
"Eliminate PHI nodes for register allocation",
|
|
|
|
false, false)
|
|
|
|
INITIALIZE_PASS_DEPENDENCY(LiveVariables)
|
|
|
|
INITIALIZE_PASS_END(PHIElimination, "phi-node-elimination",
|
|
|
|
"Eliminate PHI nodes for register allocation", false, false)
|
|
|
|
|
2010-12-06 05:39:42 +08:00
|
|
|
void PHIElimination::getAnalysisUsage(AnalysisUsage &AU) const {
|
2009-08-01 07:37:33 +08:00
|
|
|
AU.addPreserved<LiveVariables>();
|
2013-02-20 14:46:28 +08:00
|
|
|
AU.addPreserved<SlotIndexes>();
|
2013-02-10 14:42:36 +08:00
|
|
|
AU.addPreserved<LiveIntervals>();
|
2009-11-14 08:38:06 +08:00
|
|
|
AU.addPreserved<MachineDominatorTree>();
|
2010-08-18 05:00:37 +08:00
|
|
|
AU.addPreserved<MachineLoopInfo>();
|
2009-08-01 07:37:33 +08:00
|
|
|
MachineFunctionPass::getAnalysisUsage(AU);
|
|
|
|
}
|
2009-07-22 07:47:33 +08:00
|
|
|
|
2010-12-06 05:39:42 +08:00
|
|
|
bool PHIElimination::runOnMachineFunction(MachineFunction &MF) {
|
2010-05-05 01:12:26 +08:00
|
|
|
MRI = &MF.getRegInfo();
|
2013-02-10 14:42:30 +08:00
|
|
|
LV = getAnalysisIfAvailable<LiveVariables>();
|
2013-02-10 14:42:36 +08:00
|
|
|
LIS = getAnalysisIfAvailable<LiveIntervals>();
|
2008-04-04 00:38:20 +08:00
|
|
|
|
|
|
|
bool Changed = false;
|
|
|
|
|
2011-07-30 06:51:22 +08:00
|
|
|
// This pass takes the function out of SSA form.
|
|
|
|
MRI->leaveSSA();
|
|
|
|
|
2013-02-10 14:42:36 +08:00
|
|
|
// Split critical edges to help the coalescer. This does not yet support
|
|
|
|
// updating LiveIntervals, so we disable it.
|
2013-02-11 17:24:47 +08:00
|
|
|
if (!DisableEdgeSplitting && (LV || LIS)) {
|
2013-02-10 14:42:30 +08:00
|
|
|
MachineLoopInfo *MLI = getAnalysisIfAvailable<MachineLoopInfo>();
|
2015-06-11 15:45:05 +08:00
|
|
|
for (auto &MBB : MF)
|
|
|
|
Changed |= SplitPHIEdges(MF, MBB, MLI);
|
2010-08-18 05:00:37 +08:00
|
|
|
}
|
2009-11-12 03:31:31 +08:00
|
|
|
|
|
|
|
// Populate VRegPHIUseCount
|
2010-05-05 01:12:26 +08:00
|
|
|
analyzePHINodes(MF);
|
2009-11-12 03:31:31 +08:00
|
|
|
|
2008-04-04 00:38:20 +08:00
|
|
|
// Eliminate PHI instructions by inserting copies into predecessor blocks.
|
2015-06-11 15:45:05 +08:00
|
|
|
for (auto &MBB : MF)
|
|
|
|
Changed |= EliminatePHINodes(MF, MBB);
|
2008-04-04 00:38:20 +08:00
|
|
|
|
|
|
|
// Remove dead IMPLICIT_DEF instructions.
|
2014-08-25 07:23:06 +08:00
|
|
|
for (MachineInstr *DefMI : ImpDefs) {
|
2008-04-04 00:38:20 +08:00
|
|
|
unsigned DefReg = DefMI->getOperand(0).getReg();
|
2013-02-10 14:42:36 +08:00
|
|
|
if (MRI->use_nodbg_empty(DefReg)) {
|
|
|
|
if (LIS)
|
|
|
|
LIS->RemoveMachineInstrFromMaps(DefMI);
|
2008-04-04 00:38:20 +08:00
|
|
|
DefMI->eraseFromParent();
|
2013-02-10 14:42:36 +08:00
|
|
|
}
|
2008-04-04 00:38:20 +08:00
|
|
|
}
|
|
|
|
|
2009-12-17 02:55:53 +08:00
|
|
|
// Clean up the lowered PHI instructions.
|
|
|
|
for (LoweredPHIMap::iterator I = LoweredPHIs.begin(), E = LoweredPHIs.end();
|
2013-02-10 14:42:36 +08:00
|
|
|
I != E; ++I) {
|
2013-02-12 13:48:56 +08:00
|
|
|
if (LIS)
|
|
|
|
LIS->RemoveMachineInstrFromMaps(I->first);
|
2010-05-05 01:12:26 +08:00
|
|
|
MF.DeleteMachineInstr(I->first);
|
2013-02-10 14:42:36 +08:00
|
|
|
}
|
2009-12-17 02:55:53 +08:00
|
|
|
|
2009-12-18 07:42:32 +08:00
|
|
|
LoweredPHIs.clear();
|
2008-04-04 00:38:20 +08:00
|
|
|
ImpDefs.clear();
|
|
|
|
VRegPHIUseCount.clear();
|
2010-05-05 01:12:26 +08:00
|
|
|
|
2008-04-04 00:38:20 +08:00
|
|
|
return Changed;
|
|
|
|
}
|
|
|
|
|
2003-01-14 04:01:16 +08:00
|
|
|
/// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions in
|
|
|
|
/// predecessor basic blocks.
|
|
|
|
///
|
2010-12-06 05:39:42 +08:00
|
|
|
bool PHIElimination::EliminatePHINodes(MachineFunction &MF,
|
2009-07-22 07:47:33 +08:00
|
|
|
MachineBasicBlock &MBB) {
|
2010-02-10 03:54:29 +08:00
|
|
|
if (MBB.empty() || !MBB.front().isPHI())
|
2005-10-03 12:47:08 +08:00
|
|
|
return false; // Quick exit for basic blocks without PHIs.
|
2003-01-14 04:01:16 +08:00
|
|
|
|
2004-05-11 02:47:18 +08:00
|
|
|
// Get an iterator to the first instruction after the last PHI node (this may
|
2005-10-03 12:47:08 +08:00
|
|
|
// also be the end of the basic block).
|
2013-07-02 03:42:46 +08:00
|
|
|
MachineBasicBlock::iterator LastPHIIt =
|
2014-03-02 20:27:27 +08:00
|
|
|
std::prev(MBB.SkipPHIsAndLabels(MBB.begin()));
|
2004-05-11 02:47:18 +08:00
|
|
|
|
2010-02-10 03:54:29 +08:00
|
|
|
while (MBB.front().isPHI())
|
2013-07-02 03:42:46 +08:00
|
|
|
LowerPHINode(MBB, LastPHIIt);
|
2006-09-28 15:10:24 +08:00
|
|
|
|
2005-10-03 12:47:08 +08:00
|
|
|
return true;
|
|
|
|
}
|
2005-04-22 06:36:52 +08:00
|
|
|
|
2012-06-25 11:36:12 +08:00
|
|
|
/// isImplicitlyDefined - Return true if all defs of VirtReg are implicit-defs.
|
|
|
|
/// This includes registers with no defs.
|
|
|
|
static bool isImplicitlyDefined(unsigned VirtReg,
|
|
|
|
const MachineRegisterInfo *MRI) {
|
2014-03-18 03:36:09 +08:00
|
|
|
for (MachineInstr &DI : MRI->def_instructions(VirtReg))
|
|
|
|
if (!DI.isImplicitDef())
|
2012-06-25 11:36:12 +08:00
|
|
|
return false;
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2008-06-19 09:21:26 +08:00
|
|
|
/// isSourceDefinedByImplicitDef - Return true if all sources of the phi node
|
|
|
|
/// are implicit_def's.
|
2008-05-13 06:15:05 +08:00
|
|
|
static bool isSourceDefinedByImplicitDef(const MachineInstr *MPhi,
|
2008-06-19 09:21:26 +08:00
|
|
|
const MachineRegisterInfo *MRI) {
|
2012-06-25 11:36:12 +08:00
|
|
|
for (unsigned i = 1; i != MPhi->getNumOperands(); i += 2)
|
|
|
|
if (!isImplicitlyDefined(MPhi->getOperand(i).getReg(), MRI))
|
2008-05-10 08:17:50 +08:00
|
|
|
return false;
|
|
|
|
return true;
|
2008-04-12 01:54:45 +08:00
|
|
|
}
|
|
|
|
|
2009-03-17 17:46:22 +08:00
|
|
|
|
2013-02-10 14:42:32 +08:00
|
|
|
/// LowerPHINode - Lower the PHI node at the top of the specified block,
|
2009-11-11 06:00:56 +08:00
|
|
|
///
|
2013-02-10 14:42:32 +08:00
|
|
|
void PHIElimination::LowerPHINode(MachineBasicBlock &MBB,
|
2013-07-02 03:42:46 +08:00
|
|
|
MachineBasicBlock::iterator LastPHIIt) {
|
2013-02-10 14:42:32 +08:00
|
|
|
++NumLowered;
|
2013-07-02 03:42:46 +08:00
|
|
|
|
2014-03-02 20:27:27 +08:00
|
|
|
MachineBasicBlock::iterator AfterPHIsIt = std::next(LastPHIIt);
|
2013-07-02 03:42:46 +08:00
|
|
|
|
2005-10-03 12:47:08 +08:00
|
|
|
// Unlink the PHI node from the basic block, but don't delete the PHI yet.
|
|
|
|
MachineInstr *MPhi = MBB.remove(MBB.begin());
|
|
|
|
|
2008-04-12 01:54:45 +08:00
|
|
|
unsigned NumSrcs = (MPhi->getNumOperands() - 1) / 2;
|
2005-10-03 12:47:08 +08:00
|
|
|
unsigned DestReg = MPhi->getOperand(0).getReg();
|
2010-08-19 00:09:47 +08:00
|
|
|
assert(MPhi->getOperand(0).getSubReg() == 0 && "Can't handle sub-reg PHIs");
|
2008-07-03 17:09:37 +08:00
|
|
|
bool isDead = MPhi->getOperand(0).isDead();
|
2005-10-03 12:47:08 +08:00
|
|
|
|
2006-09-28 15:10:24 +08:00
|
|
|
// Create a new register for the incoming PHI arguments.
|
2005-10-03 12:47:08 +08:00
|
|
|
MachineFunction &MF = *MBB.getParent();
|
2008-07-03 17:09:37 +08:00
|
|
|
unsigned IncomingReg = 0;
|
2009-12-17 02:55:53 +08:00
|
|
|
bool reusedIncoming = false; // Is IncomingReg reused from an earlier PHI?
|
2005-10-03 12:47:08 +08:00
|
|
|
|
2008-05-13 06:15:05 +08:00
|
|
|
// Insert a register to register copy at the top of the current block (but
|
2005-10-03 12:47:08 +08:00
|
|
|
// after any remaining phi nodes) which copies the new incoming register
|
|
|
|
// into the phi node destination.
|
2014-08-05 10:39:49 +08:00
|
|
|
const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
|
2008-05-10 08:17:50 +08:00
|
|
|
if (isSourceDefinedByImplicitDef(MPhi, MRI))
|
2008-07-03 17:09:37 +08:00
|
|
|
// If all sources of a PHI node are implicit_def, just emit an
|
|
|
|
// implicit_def instead of a copy.
|
2009-02-03 10:29:34 +08:00
|
|
|
BuildMI(MBB, AfterPHIsIt, MPhi->getDebugLoc(),
|
2010-02-10 03:54:29 +08:00
|
|
|
TII->get(TargetOpcode::IMPLICIT_DEF), DestReg);
|
2008-07-03 17:09:37 +08:00
|
|
|
else {
|
2009-12-17 02:55:53 +08:00
|
|
|
// Can we reuse an earlier PHI node? This only happens for critical edges,
|
|
|
|
// typically those created by tail duplication.
|
|
|
|
unsigned &entry = LoweredPHIs[MPhi];
|
|
|
|
if (entry) {
|
|
|
|
// An identical PHI node was already lowered. Reuse the incoming register.
|
|
|
|
IncomingReg = entry;
|
|
|
|
reusedIncoming = true;
|
|
|
|
++NumReused;
|
2011-01-09 11:05:53 +08:00
|
|
|
DEBUG(dbgs() << "Reusing " << PrintReg(IncomingReg) << " for " << *MPhi);
|
2009-12-17 02:55:53 +08:00
|
|
|
} else {
|
2010-07-11 03:08:25 +08:00
|
|
|
const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(DestReg);
|
2009-12-17 02:55:53 +08:00
|
|
|
entry = IncomingReg = MF.getRegInfo().createVirtualRegister(RC);
|
|
|
|
}
|
2010-07-11 03:08:25 +08:00
|
|
|
BuildMI(MBB, AfterPHIsIt, MPhi->getDebugLoc(),
|
|
|
|
TII->get(TargetOpcode::COPY), DestReg)
|
|
|
|
.addReg(IncomingReg);
|
2008-07-03 17:09:37 +08:00
|
|
|
}
|
2003-01-14 04:01:16 +08:00
|
|
|
|
2008-05-13 06:15:05 +08:00
|
|
|
// Update live variable information if there is any.
|
2005-10-03 12:47:08 +08:00
|
|
|
if (LV) {
|
2014-03-02 20:27:27 +08:00
|
|
|
MachineInstr *PHICopy = std::prev(AfterPHIsIt);
|
2005-04-22 06:36:52 +08:00
|
|
|
|
2008-07-03 17:09:37 +08:00
|
|
|
if (IncomingReg) {
|
2009-12-17 02:55:53 +08:00
|
|
|
LiveVariables::VarInfo &VI = LV->getVarInfo(IncomingReg);
|
|
|
|
|
2008-07-03 17:09:37 +08:00
|
|
|
// Increment use count of the newly created virtual register.
|
2010-02-24 06:43:58 +08:00
|
|
|
LV->setPHIJoin(IncomingReg);
|
2009-12-17 02:55:53 +08:00
|
|
|
|
|
|
|
// When we are reusing the incoming register, it may already have been
|
|
|
|
// killed in this block. The old kill will also have been inserted at
|
|
|
|
// AfterPHIsIt, so it appears before the current PHICopy.
|
|
|
|
if (reusedIncoming)
|
|
|
|
if (MachineInstr *OldKill = VI.findKill(&MBB)) {
|
2010-01-05 09:24:24 +08:00
|
|
|
DEBUG(dbgs() << "Remove old kill from " << *OldKill);
|
2009-12-17 02:55:53 +08:00
|
|
|
LV->removeVirtualRegisterKilled(IncomingReg, OldKill);
|
|
|
|
DEBUG(MBB.dump());
|
|
|
|
}
|
2008-07-03 17:09:37 +08:00
|
|
|
|
|
|
|
// Add information to LiveVariables to know that the incoming value is
|
|
|
|
// killed. Note that because the value is defined in several places (once
|
|
|
|
// each for each incoming block), the "def" block and instruction fields
|
|
|
|
// for the VarInfo is not filled in.
|
|
|
|
LV->addVirtualRegisterKilled(IncomingReg, PHICopy);
|
|
|
|
}
|
2003-01-14 04:01:16 +08:00
|
|
|
|
2008-05-13 06:15:05 +08:00
|
|
|
// Since we are going to be deleting the PHI node, if it is the last use of
|
|
|
|
// any registers, or if the value itself is dead, we need to move this
|
2005-10-03 12:47:08 +08:00
|
|
|
// information over to the new copy we just inserted.
|
|
|
|
LV->removeVirtualRegistersKilled(MPhi);
|
|
|
|
|
2005-10-03 15:22:07 +08:00
|
|
|
// If the result is dead, update LV.
|
2008-07-03 17:09:37 +08:00
|
|
|
if (isDead) {
|
2005-10-03 15:22:07 +08:00
|
|
|
LV->addVirtualRegisterDead(DestReg, PHICopy);
|
2008-07-03 17:09:37 +08:00
|
|
|
LV->removeVirtualRegisterDead(DestReg, MPhi);
|
2003-05-12 11:55:21 +08:00
|
|
|
}
|
2005-10-03 12:47:08 +08:00
|
|
|
}
|
|
|
|
|
2013-02-10 14:42:36 +08:00
|
|
|
// Update LiveIntervals for the new copy or implicit def.
|
|
|
|
if (LIS) {
|
2014-03-02 20:27:27 +08:00
|
|
|
MachineInstr *NewInstr = std::prev(AfterPHIsIt);
|
2013-02-20 14:46:32 +08:00
|
|
|
SlotIndex DestCopyIndex = LIS->InsertMachineInstrInMaps(NewInstr);
|
2013-02-10 14:42:36 +08:00
|
|
|
|
|
|
|
SlotIndex MBBStartIndex = LIS->getMBBStartIdx(&MBB);
|
|
|
|
if (IncomingReg) {
|
|
|
|
// Add the region from the beginning of MBB to the copy instruction to
|
|
|
|
// IncomingReg's live interval.
|
2013-08-15 07:50:16 +08:00
|
|
|
LiveInterval &IncomingLI = LIS->createEmptyInterval(IncomingReg);
|
2013-02-10 14:42:36 +08:00
|
|
|
VNInfo *IncomingVNI = IncomingLI.getVNInfoAt(MBBStartIndex);
|
|
|
|
if (!IncomingVNI)
|
|
|
|
IncomingVNI = IncomingLI.getNextValue(MBBStartIndex,
|
|
|
|
LIS->getVNInfoAllocator());
|
2013-10-11 05:28:43 +08:00
|
|
|
IncomingLI.addSegment(LiveInterval::Segment(MBBStartIndex,
|
|
|
|
DestCopyIndex.getRegSlot(),
|
|
|
|
IncomingVNI));
|
2013-02-10 14:42:36 +08:00
|
|
|
}
|
|
|
|
|
2013-02-21 16:51:55 +08:00
|
|
|
LiveInterval &DestLI = LIS->getInterval(DestReg);
|
2013-02-21 16:51:58 +08:00
|
|
|
assert(DestLI.begin() != DestLI.end() &&
|
|
|
|
"PHIs should have nonempty LiveIntervals.");
|
|
|
|
if (DestLI.endIndex().isDead()) {
|
2013-02-10 14:42:36 +08:00
|
|
|
// A dead PHI's live range begins and ends at the start of the MBB, but
|
|
|
|
// the lowered copy, which will still be dead, needs to begin and end at
|
|
|
|
// the copy instruction.
|
|
|
|
VNInfo *OrigDestVNI = DestLI.getVNInfoAt(MBBStartIndex);
|
|
|
|
assert(OrigDestVNI && "PHI destination should be live at block entry.");
|
2013-10-11 05:28:43 +08:00
|
|
|
DestLI.removeSegment(MBBStartIndex, MBBStartIndex.getDeadSlot());
|
2013-02-10 14:42:36 +08:00
|
|
|
DestLI.createDeadDef(DestCopyIndex.getRegSlot(),
|
|
|
|
LIS->getVNInfoAllocator());
|
|
|
|
DestLI.removeValNo(OrigDestVNI);
|
|
|
|
} else {
|
|
|
|
// Otherwise, remove the region from the beginning of MBB to the copy
|
|
|
|
// instruction from DestReg's live interval.
|
2013-10-11 05:28:43 +08:00
|
|
|
DestLI.removeSegment(MBBStartIndex, DestCopyIndex.getRegSlot());
|
2013-02-10 14:42:36 +08:00
|
|
|
VNInfo *DestVNI = DestLI.getVNInfoAt(DestCopyIndex.getRegSlot());
|
|
|
|
assert(DestVNI && "PHI destination should be live at its definition.");
|
|
|
|
DestVNI->def = DestCopyIndex.getRegSlot();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2008-05-13 06:15:05 +08:00
|
|
|
// Adjust the VRegPHIUseCount map to account for the removal of this PHI node.
|
2005-10-03 12:47:08 +08:00
|
|
|
for (unsigned i = 1; i != MPhi->getNumOperands(); i += 2)
|
2009-12-17 02:55:53 +08:00
|
|
|
--VRegPHIUseCount[BBVRegPair(MPhi->getOperand(i+1).getMBB()->getNumber(),
|
2007-12-31 07:10:15 +08:00
|
|
|
MPhi->getOperand(i).getReg())];
|
2005-10-03 12:47:08 +08:00
|
|
|
|
2008-05-13 06:15:05 +08:00
|
|
|
// Now loop over all of the incoming arguments, changing them to copy into the
|
|
|
|
// IncomingReg register in the corresponding predecessor basic block.
|
2008-04-04 00:38:20 +08:00
|
|
|
SmallPtrSet<MachineBasicBlock*, 8> MBBsInsertedInto;
|
2008-04-12 01:54:45 +08:00
|
|
|
for (int i = NumSrcs - 1; i >= 0; --i) {
|
|
|
|
unsigned SrcReg = MPhi->getOperand(i*2+1).getReg();
|
2010-08-19 00:09:47 +08:00
|
|
|
unsigned SrcSubReg = MPhi->getOperand(i*2+1).getSubReg();
|
2012-06-25 11:36:12 +08:00
|
|
|
bool SrcUndef = MPhi->getOperand(i*2+1).isUndef() ||
|
|
|
|
isImplicitlyDefined(SrcReg, MRI);
|
2008-02-11 02:45:23 +08:00
|
|
|
assert(TargetRegisterInfo::isVirtualRegister(SrcReg) &&
|
2005-10-03 15:22:07 +08:00
|
|
|
"Machine PHI Operands must all be virtual registers!");
|
2005-10-03 12:47:08 +08:00
|
|
|
|
2009-07-23 12:34:03 +08:00
|
|
|
// Get the MachineBasicBlock equivalent of the BasicBlock that is the source
|
|
|
|
// path the PHI.
|
|
|
|
MachineBasicBlock &opBlock = *MPhi->getOperand(i*2+2).getMBB();
|
|
|
|
|
2005-10-03 12:47:08 +08:00
|
|
|
// Check to make sure we haven't already emitted the copy for this block.
|
2008-05-13 06:15:05 +08:00
|
|
|
// This can happen because PHI nodes may have multiple entries for the same
|
|
|
|
// basic block.
|
2014-11-19 15:49:26 +08:00
|
|
|
if (!MBBsInsertedInto.insert(&opBlock).second)
|
2005-10-03 15:22:07 +08:00
|
|
|
continue; // If the copy has already been emitted, we're done.
|
2009-11-11 06:00:56 +08:00
|
|
|
|
2008-05-13 06:15:05 +08:00
|
|
|
// Find a safe location to insert the copy, this may be the first terminator
|
|
|
|
// in the block (or end()).
|
2009-11-14 05:56:15 +08:00
|
|
|
MachineBasicBlock::iterator InsertPos =
|
2010-12-06 03:51:05 +08:00
|
|
|
findPHICopyInsertPoint(&opBlock, &MBB, SrcReg);
|
2009-03-14 06:59:14 +08:00
|
|
|
|
2005-10-03 15:22:07 +08:00
|
|
|
// Insert the copy.
|
2014-04-14 08:51:57 +08:00
|
|
|
MachineInstr *NewSrcInstr = nullptr;
|
2012-06-25 11:36:12 +08:00
|
|
|
if (!reusedIncoming && IncomingReg) {
|
|
|
|
if (SrcUndef) {
|
|
|
|
// The source register is undefined, so there is no need for a real
|
|
|
|
// COPY, but we still need to ensure joint dominance by defs.
|
|
|
|
// Insert an IMPLICIT_DEF instruction.
|
2013-02-10 14:42:36 +08:00
|
|
|
NewSrcInstr = BuildMI(opBlock, InsertPos, MPhi->getDebugLoc(),
|
|
|
|
TII->get(TargetOpcode::IMPLICIT_DEF),
|
|
|
|
IncomingReg);
|
2012-06-25 11:36:12 +08:00
|
|
|
|
|
|
|
// Clean up the old implicit-def, if there even was one.
|
|
|
|
if (MachineInstr *DefMI = MRI->getVRegDef(SrcReg))
|
|
|
|
if (DefMI->isImplicitDef())
|
|
|
|
ImpDefs.insert(DefMI);
|
|
|
|
} else {
|
2013-02-10 14:42:36 +08:00
|
|
|
NewSrcInstr = BuildMI(opBlock, InsertPos, MPhi->getDebugLoc(),
|
|
|
|
TII->get(TargetOpcode::COPY), IncomingReg)
|
|
|
|
.addReg(SrcReg, 0, SrcSubReg);
|
2012-06-25 11:36:12 +08:00
|
|
|
}
|
|
|
|
}
|
2005-10-03 15:22:07 +08:00
|
|
|
|
2013-02-10 14:42:36 +08:00
|
|
|
// We only need to update the LiveVariables kill of SrcReg if this was the
|
|
|
|
// last PHI use of SrcReg to be lowered on this CFG edge and it is not live
|
|
|
|
// out of the predecessor. We can also ignore undef sources.
|
|
|
|
if (LV && !SrcUndef &&
|
|
|
|
!VRegPHIUseCount[BBVRegPair(opBlock.getNumber(), SrcReg)] &&
|
|
|
|
!LV->isLiveOut(SrcReg, opBlock)) {
|
|
|
|
// We want to be able to insert a kill of the register if this PHI (aka,
|
|
|
|
// the copy we just inserted) is the last use of the source value. Live
|
|
|
|
// variable analysis conservatively handles this by saying that the value
|
|
|
|
// is live until the end of the block the PHI entry lives in. If the value
|
|
|
|
// really is dead at the PHI copy, there will be no successor blocks which
|
|
|
|
// have the value live-in.
|
|
|
|
|
|
|
|
// Okay, if we now know that the value is not live out of the block, we
|
|
|
|
// can add a kill marker in this block saying that it kills the incoming
|
|
|
|
// value!
|
2005-10-03 15:22:07 +08:00
|
|
|
|
2006-01-04 15:12:21 +08:00
|
|
|
// In our final twist, we have to decide which instruction kills the
|
2012-07-05 03:52:05 +08:00
|
|
|
// register. In most cases this is the copy, however, terminator
|
|
|
|
// instructions at the end of the block may also use the value. In this
|
|
|
|
// case, we should mark the last such terminator as being the killing
|
|
|
|
// block, not the copy.
|
|
|
|
MachineBasicBlock::iterator KillInst = opBlock.end();
|
|
|
|
MachineBasicBlock::iterator FirstTerm = opBlock.getFirstTerminator();
|
|
|
|
for (MachineBasicBlock::iterator Term = FirstTerm;
|
|
|
|
Term != opBlock.end(); ++Term) {
|
|
|
|
if (Term->readsRegister(SrcReg))
|
|
|
|
KillInst = Term;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (KillInst == opBlock.end()) {
|
|
|
|
// No terminator uses the register.
|
|
|
|
|
|
|
|
if (reusedIncoming || !IncomingReg) {
|
|
|
|
// We may have to rewind a bit if we didn't insert a copy this time.
|
|
|
|
KillInst = FirstTerm;
|
|
|
|
while (KillInst != opBlock.begin()) {
|
|
|
|
--KillInst;
|
|
|
|
if (KillInst->isDebugValue())
|
|
|
|
continue;
|
|
|
|
if (KillInst->readsRegister(SrcReg))
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
// We just inserted this copy.
|
2014-03-02 20:27:27 +08:00
|
|
|
KillInst = std::prev(InsertPos);
|
2011-01-14 14:33:45 +08:00
|
|
|
}
|
2006-01-04 15:12:21 +08:00
|
|
|
}
|
2009-12-17 02:55:53 +08:00
|
|
|
assert(KillInst->readsRegister(SrcReg) && "Cannot find kill instruction");
|
2009-11-11 06:00:56 +08:00
|
|
|
|
2006-01-04 15:12:21 +08:00
|
|
|
// Finally, mark it killed.
|
|
|
|
LV->addVirtualRegisterKilled(SrcReg, KillInst);
|
2005-10-03 15:22:07 +08:00
|
|
|
|
|
|
|
// This vreg no longer lives all of the way through opBlock.
|
|
|
|
unsigned opBlockNum = opBlock.getNumber();
|
2009-11-11 06:00:56 +08:00
|
|
|
LV->getVarInfo(SrcReg).AliveBlocks.reset(opBlockNum);
|
2003-01-14 04:01:16 +08:00
|
|
|
}
|
2013-02-10 14:42:36 +08:00
|
|
|
|
|
|
|
if (LIS) {
|
|
|
|
if (NewSrcInstr) {
|
|
|
|
LIS->InsertMachineInstrInMaps(NewSrcInstr);
|
2013-10-11 05:28:43 +08:00
|
|
|
LIS->addSegmentToEndOfBlock(IncomingReg, NewSrcInstr);
|
2013-02-10 14:42:36 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
if (!SrcUndef &&
|
|
|
|
!VRegPHIUseCount[BBVRegPair(opBlock.getNumber(), SrcReg)]) {
|
|
|
|
LiveInterval &SrcLI = LIS->getInterval(SrcReg);
|
|
|
|
|
|
|
|
bool isLiveOut = false;
|
|
|
|
for (MachineBasicBlock::succ_iterator SI = opBlock.succ_begin(),
|
|
|
|
SE = opBlock.succ_end(); SI != SE; ++SI) {
|
2013-02-12 13:48:58 +08:00
|
|
|
SlotIndex startIdx = LIS->getMBBStartIdx(*SI);
|
|
|
|
VNInfo *VNI = SrcLI.getVNInfoAt(startIdx);
|
|
|
|
|
|
|
|
// Definitions by other PHIs are not truly live-in for our purposes.
|
|
|
|
if (VNI && VNI->def != startIdx) {
|
2013-02-10 14:42:36 +08:00
|
|
|
isLiveOut = true;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!isLiveOut) {
|
|
|
|
MachineBasicBlock::iterator KillInst = opBlock.end();
|
|
|
|
MachineBasicBlock::iterator FirstTerm = opBlock.getFirstTerminator();
|
|
|
|
for (MachineBasicBlock::iterator Term = FirstTerm;
|
|
|
|
Term != opBlock.end(); ++Term) {
|
|
|
|
if (Term->readsRegister(SrcReg))
|
|
|
|
KillInst = Term;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (KillInst == opBlock.end()) {
|
|
|
|
// No terminator uses the register.
|
|
|
|
|
|
|
|
if (reusedIncoming || !IncomingReg) {
|
|
|
|
// We may have to rewind a bit if we didn't just insert a copy.
|
|
|
|
KillInst = FirstTerm;
|
|
|
|
while (KillInst != opBlock.begin()) {
|
|
|
|
--KillInst;
|
|
|
|
if (KillInst->isDebugValue())
|
|
|
|
continue;
|
|
|
|
if (KillInst->readsRegister(SrcReg))
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
// We just inserted this copy.
|
2014-03-02 20:27:27 +08:00
|
|
|
KillInst = std::prev(InsertPos);
|
2013-02-10 14:42:36 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
assert(KillInst->readsRegister(SrcReg) &&
|
|
|
|
"Cannot find kill instruction");
|
|
|
|
|
|
|
|
SlotIndex LastUseIndex = LIS->getInstructionIndex(KillInst);
|
2013-10-11 05:28:43 +08:00
|
|
|
SrcLI.removeSegment(LastUseIndex.getRegSlot(),
|
|
|
|
LIS->getMBBEndIdx(&opBlock));
|
2013-02-10 14:42:36 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2003-01-14 04:01:16 +08:00
|
|
|
}
|
2009-11-11 06:00:56 +08:00
|
|
|
|
2009-12-17 02:55:53 +08:00
|
|
|
// Really delete the PHI instruction now, if it is not in the LoweredPHIs map.
|
2013-02-10 14:42:36 +08:00
|
|
|
if (reusedIncoming || !IncomingReg) {
|
|
|
|
if (LIS)
|
|
|
|
LIS->RemoveMachineInstrFromMaps(MPhi);
|
2009-12-17 02:55:53 +08:00
|
|
|
MF.DeleteMachineInstr(MPhi);
|
2013-02-10 14:42:36 +08:00
|
|
|
}
|
2003-01-14 04:01:16 +08:00
|
|
|
}
|
2006-09-28 15:10:24 +08:00
|
|
|
|
|
|
|
/// analyzePHINodes - Gather information about the PHI nodes in here. In
|
|
|
|
/// particular, we want to map the number of uses of a virtual register which is
|
|
|
|
/// used in a PHI node. We map that to the BB the vreg is coming from. This is
|
|
|
|
/// used later to determine when the vreg is killed in the BB.
|
|
|
|
///
|
2010-12-06 05:39:42 +08:00
|
|
|
void PHIElimination::analyzePHINodes(const MachineFunction& MF) {
|
2014-05-01 02:29:51 +08:00
|
|
|
for (const auto &MBB : MF)
|
2014-05-01 06:17:38 +08:00
|
|
|
for (const auto &BBI : MBB) {
|
|
|
|
if (!BBI.isPHI())
|
|
|
|
break;
|
|
|
|
for (unsigned i = 1, e = BBI.getNumOperands(); i != e; i += 2)
|
|
|
|
++VRegPHIUseCount[BBVRegPair(BBI.getOperand(i+1).getMBB()->getNumber(),
|
|
|
|
BBI.getOperand(i).getReg())];
|
|
|
|
}
|
2006-09-28 15:10:24 +08:00
|
|
|
}
|
2009-11-11 06:00:56 +08:00
|
|
|
|
2010-12-06 05:39:42 +08:00
|
|
|
bool PHIElimination::SplitPHIEdges(MachineFunction &MF,
|
2011-02-17 14:13:46 +08:00
|
|
|
MachineBasicBlock &MBB,
|
|
|
|
MachineLoopInfo *MLI) {
|
2015-08-28 07:27:47 +08:00
|
|
|
if (MBB.empty() || !MBB.front().isPHI() || MBB.isEHPad())
|
2009-11-12 03:31:31 +08:00
|
|
|
return false; // Quick exit for basic blocks without PHIs.
|
2009-11-19 02:01:35 +08:00
|
|
|
|
2014-04-14 08:51:57 +08:00
|
|
|
const MachineLoop *CurLoop = MLI ? MLI->getLoopFor(&MBB) : nullptr;
|
2012-07-21 04:49:53 +08:00
|
|
|
bool IsLoopHeader = CurLoop && &MBB == CurLoop->getHeader();
|
|
|
|
|
2010-08-17 09:20:36 +08:00
|
|
|
bool Changed = false;
|
2011-12-07 06:12:01 +08:00
|
|
|
for (MachineBasicBlock::iterator BBI = MBB.begin(), BBE = MBB.end();
|
2010-02-10 03:54:29 +08:00
|
|
|
BBI != BBE && BBI->isPHI(); ++BBI) {
|
2009-11-11 06:01:05 +08:00
|
|
|
for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) {
|
|
|
|
unsigned Reg = BBI->getOperand(i).getReg();
|
|
|
|
MachineBasicBlock *PreMBB = BBI->getOperand(i+1).getMBB();
|
2012-07-21 04:49:53 +08:00
|
|
|
// Is there a critical edge from PreMBB to MBB?
|
|
|
|
if (PreMBB->succ_size() == 1)
|
|
|
|
continue;
|
|
|
|
|
2010-08-18 01:43:50 +08:00
|
|
|
// Avoid splitting backedges of loops. It would introduce small
|
|
|
|
// out-of-line blocks into the loop which is very bad for code placement.
|
2013-02-12 11:49:25 +08:00
|
|
|
if (PreMBB == &MBB && !SplitAllCriticalEdges)
|
2012-07-21 04:49:53 +08:00
|
|
|
continue;
|
2014-04-14 08:51:57 +08:00
|
|
|
const MachineLoop *PreLoop = MLI ? MLI->getLoopFor(PreMBB) : nullptr;
|
2013-02-12 11:49:25 +08:00
|
|
|
if (IsLoopHeader && PreLoop == CurLoop && !SplitAllCriticalEdges)
|
2012-07-21 04:49:53 +08:00
|
|
|
continue;
|
|
|
|
|
|
|
|
// LV doesn't consider a phi use live-out, so isLiveOut only returns true
|
|
|
|
// when the source register is live-out for some other reason than a phi
|
|
|
|
// use. That means the copy we will insert in PreMBB won't be a kill, and
|
|
|
|
// there is a risk it may not be coalesced away.
|
|
|
|
//
|
|
|
|
// If the copy would be a kill, there is no need to split the edge.
|
2015-03-03 18:23:11 +08:00
|
|
|
bool ShouldSplit = isLiveOutPastPHIs(Reg, PreMBB);
|
|
|
|
if (!ShouldSplit && !NoPhiElimLiveOutEarlyExit)
|
2012-07-21 04:49:53 +08:00
|
|
|
continue;
|
2015-03-03 18:23:11 +08:00
|
|
|
if (ShouldSplit) {
|
|
|
|
DEBUG(dbgs() << PrintReg(Reg) << " live-out before critical edge BB#"
|
|
|
|
<< PreMBB->getNumber() << " -> BB#" << MBB.getNumber()
|
|
|
|
<< ": " << *BBI);
|
|
|
|
}
|
2012-07-21 04:49:53 +08:00
|
|
|
|
|
|
|
// If Reg is not live-in to MBB, it means it must be live-in to some
|
|
|
|
// other PreMBB successor, and we can avoid the interference by splitting
|
|
|
|
// the edge.
|
|
|
|
//
|
|
|
|
// If Reg *is* live-in to MBB, the interference is inevitable and a copy
|
|
|
|
// is likely to be left after coalescing. If we are looking at a loop
|
|
|
|
// exiting edge, split it so we won't insert code in the loop, otherwise
|
|
|
|
// don't bother.
|
2015-03-03 18:23:11 +08:00
|
|
|
ShouldSplit = ShouldSplit && !isLiveIn(Reg, &MBB);
|
2012-07-21 04:49:53 +08:00
|
|
|
|
|
|
|
// Check for a loop exiting edge.
|
|
|
|
if (!ShouldSplit && CurLoop != PreLoop) {
|
|
|
|
DEBUG({
|
|
|
|
dbgs() << "Split wouldn't help, maybe avoid loop copies?\n";
|
|
|
|
if (PreLoop) dbgs() << "PreLoop: " << *PreLoop;
|
|
|
|
if (CurLoop) dbgs() << "CurLoop: " << *CurLoop;
|
|
|
|
});
|
|
|
|
// This edge could be entering a loop, exiting a loop, or it could be
|
|
|
|
// both: Jumping directly form one loop to the header of a sibling
|
|
|
|
// loop.
|
|
|
|
// Split unless this edge is entering CurLoop from an outer loop.
|
|
|
|
ShouldSplit = PreLoop && !PreLoop->contains(CurLoop);
|
|
|
|
}
|
2015-03-03 18:23:11 +08:00
|
|
|
if (!ShouldSplit && !SplitAllCriticalEdges)
|
2012-07-21 04:49:53 +08:00
|
|
|
continue;
|
|
|
|
if (!PreMBB->SplitCriticalEdge(&MBB, this)) {
|
2014-01-22 10:38:23 +08:00
|
|
|
DEBUG(dbgs() << "Failed to split critical edge.\n");
|
2012-07-21 04:49:53 +08:00
|
|
|
continue;
|
2010-08-18 01:43:50 +08:00
|
|
|
}
|
2012-07-21 04:49:53 +08:00
|
|
|
Changed = true;
|
|
|
|
++NumCriticalEdgesSplit;
|
2009-11-11 06:01:05 +08:00
|
|
|
}
|
|
|
|
}
|
2011-02-17 14:13:43 +08:00
|
|
|
return Changed;
|
2009-11-11 06:01:05 +08:00
|
|
|
}
|
2013-02-11 07:29:49 +08:00
|
|
|
|
2015-06-11 15:45:05 +08:00
|
|
|
bool PHIElimination::isLiveIn(unsigned Reg, const MachineBasicBlock *MBB) {
|
2013-02-11 07:29:49 +08:00
|
|
|
assert((LV || LIS) &&
|
|
|
|
"isLiveIn() requires either LiveVariables or LiveIntervals");
|
|
|
|
if (LIS)
|
|
|
|
return LIS->isLiveInToMBB(LIS->getInterval(Reg), MBB);
|
|
|
|
else
|
|
|
|
return LV->isLiveIn(Reg, *MBB);
|
|
|
|
}
|
|
|
|
|
2015-06-11 15:45:05 +08:00
|
|
|
bool PHIElimination::isLiveOutPastPHIs(unsigned Reg,
|
|
|
|
const MachineBasicBlock *MBB) {
|
2013-02-11 07:29:49 +08:00
|
|
|
assert((LV || LIS) &&
|
|
|
|
"isLiveOutPastPHIs() requires either LiveVariables or LiveIntervals");
|
|
|
|
// LiveVariables considers uses in PHIs to be in the predecessor basic block,
|
|
|
|
// so that a register used only in a PHI is not live out of the block. In
|
|
|
|
// contrast, LiveIntervals considers uses in PHIs to be on the edge rather than
|
|
|
|
// in the predecessor basic block, so that a register used only in a PHI is live
|
|
|
|
// out of the block.
|
|
|
|
if (LIS) {
|
|
|
|
const LiveInterval &LI = LIS->getInterval(Reg);
|
2015-06-11 15:45:05 +08:00
|
|
|
for (const MachineBasicBlock *SI : MBB->successors())
|
|
|
|
if (LI.liveAt(LIS->getMBBStartIdx(SI)))
|
2013-02-11 07:29:49 +08:00
|
|
|
return true;
|
|
|
|
return false;
|
|
|
|
} else {
|
|
|
|
return LV->isLiveOut(Reg, *MBB);
|
|
|
|
}
|
|
|
|
}
|