2015-11-24 05:33:58 +08:00
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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2016-02-01 15:56:09 +08:00
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; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+avx < %s | FileCheck %s --check-prefix=AVX
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; RUN: llc -mtriple=i386-unknown-linux-gnu -mcpu=knl < %s | FileCheck %s --check-prefix=KNL-32
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[x86] Fix wrong lowering of vsetcc nodes (PR25080).
Function LowerVSETCC (in X86ISelLowering.cpp) worked under the wrong
assumption that for non-AVX512 targets, the source type and destination type
of a type-legalized setcc node were always the same type.
This assumption was unfortunately incorrect; the type legalizer is not always
able to promote the return type of a setcc to the same type as the first
operand of a setcc.
In the case of a vsetcc node, the legalizer firstly checks if the first input
operand has a legal type. If so, then it promotes the return type of the vsetcc
to that same type. Otherwise, the return type is promoted to the 'next legal
type', which, for vectors of MVT::i1 is always a 128-bit integer vector type.
Example (-mattr=+avx):
%0 = trunc <8 x i32> %a to <8 x i23>
%1 = icmp eq <8 x i23> %0, zeroinitializer
The initial selection dag for the code above is:
v8i1 = setcc t5, t7, seteq:ch
t5: v8i23 = truncate t2
t2: v8i32,ch = CopyFromReg t0, Register:v8i32 %vreg1
t7: v8i32 = build_vector of all zeroes.
The type legalizer would firstly check if 't5' has a legal type. If so, then it
would reuse that same type to promote the return type of the setcc node.
Unfortunately 't5' is of illegal type v8i23, and therefore it cannot be used to
promote the return type of the setcc node. Consequently, the setcc return type
is promoted to v8i16. Later on, 't5' is promoted to v8i32 thus leading to the
following dag node:
v8i16 = setcc t32, t25, seteq:ch
where t32 and t25 are now values of type v8i32.
Before this patch, function LowerVSETCC would have wrongly expanded the setcc
to a single X86ISD::PCMPEQ. Surprisingly, ISel was still able to match an
instruction. In our case, ISel would have matched a VPCMPEQWrr:
t37: v8i16 = X86ISD::VPCMPEQWrr t36, t25
However, t36 and t25 are both VR256, while the result type is instead of class
VR128. This inconsistency ended up causing the insertion of COPY instructions
like this:
%vreg7<def> = COPY %vreg3; VR128:%vreg7 VR256:%vreg3
Which is an invalid full copy (not a sub register copy).
Eventually, the backend would have hit an UNREACHABLE "Cannot emit physreg copy
instruction" in the attempt to expand the malformed pseudo COPY instructions.
This patch fixes the problem adding the missing logic in LowerVSETCC to handle
the corner case of a setcc with 128-bit return type and 256-bit operand type.
This problem was originally reported by Dimitry as PR25080. It has been latent
for a very long time. I have added the minimal reproducible from that bugzilla
as test setcc-lowering.ll.
Differential Revision: http://reviews.llvm.org/D13660
llvm-svn: 250085
2015-10-13 03:22:30 +08:00
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; Verify that we don't crash during codegen due to a wrong lowering
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; of a setcc node with illegal operand types and return type.
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define <8 x i16> @pr25080(<8 x i32> %a) {
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2016-02-01 15:56:09 +08:00
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; AVX-LABEL: pr25080:
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; AVX: # BB#0: # %entry
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; AVX-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
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; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1
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; AVX-NEXT: vpxor %xmm2, %xmm2, %xmm2
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; AVX-NEXT: vpcmpeqd %xmm2, %xmm1, %xmm1
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; AVX-NEXT: vpcmpeqd %xmm2, %xmm0, %xmm0
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2016-07-29 18:23:10 +08:00
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; AVX-NEXT: vpacksswb %xmm1, %xmm0, %xmm0
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2016-02-01 15:56:09 +08:00
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; AVX-NEXT: vpor {{.*}}(%rip), %xmm0, %xmm0
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; AVX-NEXT: vpsllw $15, %xmm0, %xmm0
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; AVX-NEXT: vpsraw $15, %xmm0, %xmm0
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; AVX-NEXT: vzeroupper
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; AVX-NEXT: retq
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2017-02-12 03:27:15 +08:00
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;
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; KNL-32-LABEL: pr25080:
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; KNL-32: # BB#0: # %entry
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; KNL-32-NEXT: vpbroadcastd {{\.LCPI.*}}, %ymm1
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; KNL-32-NEXT: vpand %ymm1, %ymm0, %ymm0
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; KNL-32-NEXT: vpxor %ymm1, %ymm1, %ymm1
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; KNL-32-NEXT: vpcmpeqd %zmm1, %zmm0, %k0
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; KNL-32-NEXT: movb $15, %al
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; KNL-32-NEXT: kmovw %eax, %k1
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; KNL-32-NEXT: korw %k1, %k0, %k1
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; KNL-32-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
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; KNL-32-NEXT: vpmovqw %zmm0, %xmm0
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; KNL-32-NEXT: retl
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[x86] Fix wrong lowering of vsetcc nodes (PR25080).
Function LowerVSETCC (in X86ISelLowering.cpp) worked under the wrong
assumption that for non-AVX512 targets, the source type and destination type
of a type-legalized setcc node were always the same type.
This assumption was unfortunately incorrect; the type legalizer is not always
able to promote the return type of a setcc to the same type as the first
operand of a setcc.
In the case of a vsetcc node, the legalizer firstly checks if the first input
operand has a legal type. If so, then it promotes the return type of the vsetcc
to that same type. Otherwise, the return type is promoted to the 'next legal
type', which, for vectors of MVT::i1 is always a 128-bit integer vector type.
Example (-mattr=+avx):
%0 = trunc <8 x i32> %a to <8 x i23>
%1 = icmp eq <8 x i23> %0, zeroinitializer
The initial selection dag for the code above is:
v8i1 = setcc t5, t7, seteq:ch
t5: v8i23 = truncate t2
t2: v8i32,ch = CopyFromReg t0, Register:v8i32 %vreg1
t7: v8i32 = build_vector of all zeroes.
The type legalizer would firstly check if 't5' has a legal type. If so, then it
would reuse that same type to promote the return type of the setcc node.
Unfortunately 't5' is of illegal type v8i23, and therefore it cannot be used to
promote the return type of the setcc node. Consequently, the setcc return type
is promoted to v8i16. Later on, 't5' is promoted to v8i32 thus leading to the
following dag node:
v8i16 = setcc t32, t25, seteq:ch
where t32 and t25 are now values of type v8i32.
Before this patch, function LowerVSETCC would have wrongly expanded the setcc
to a single X86ISD::PCMPEQ. Surprisingly, ISel was still able to match an
instruction. In our case, ISel would have matched a VPCMPEQWrr:
t37: v8i16 = X86ISD::VPCMPEQWrr t36, t25
However, t36 and t25 are both VR256, while the result type is instead of class
VR128. This inconsistency ended up causing the insertion of COPY instructions
like this:
%vreg7<def> = COPY %vreg3; VR128:%vreg7 VR256:%vreg3
Which is an invalid full copy (not a sub register copy).
Eventually, the backend would have hit an UNREACHABLE "Cannot emit physreg copy
instruction" in the attempt to expand the malformed pseudo COPY instructions.
This patch fixes the problem adding the missing logic in LowerVSETCC to handle
the corner case of a setcc with 128-bit return type and 256-bit operand type.
This problem was originally reported by Dimitry as PR25080. It has been latent
for a very long time. I have added the minimal reproducible from that bugzilla
as test setcc-lowering.ll.
Differential Revision: http://reviews.llvm.org/D13660
llvm-svn: 250085
2015-10-13 03:22:30 +08:00
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entry:
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%0 = trunc <8 x i32> %a to <8 x i23>
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%1 = icmp eq <8 x i23> %0, zeroinitializer
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%2 = or <8 x i1> %1, <i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false>
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%3 = sext <8 x i1> %2 to <8 x i16>
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ret <8 x i16> %3
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}
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2016-02-01 15:56:09 +08:00
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2017-05-30 02:27:00 +08:00
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define void @pr26232(i64 %a, <16 x i1> %b) {
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2017-02-12 03:27:15 +08:00
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; AVX-LABEL: pr26232:
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; AVX: # BB#0: # %for_loop599.preheader
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2017-05-30 02:27:00 +08:00
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; AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1
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2017-06-01 19:27:57 +08:00
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; AVX-NEXT: vmovdqa {{.*#+}} xmm2 = [128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128]
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2017-02-12 03:27:15 +08:00
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; AVX-NEXT: .p2align 4, 0x90
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; AVX-NEXT: .LBB1_1: # %for_loop599
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; AVX-NEXT: # =>This Inner Loop Header: Depth=1
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2017-05-30 02:27:00 +08:00
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; AVX-NEXT: xorl %eax, %eax
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2017-02-12 03:27:15 +08:00
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; AVX-NEXT: cmpq $65536, %rdi # imm = 0x10000
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2017-05-30 02:27:00 +08:00
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; AVX-NEXT: setl %al
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2017-06-01 19:27:57 +08:00
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; AVX-NEXT: vmovd %eax, %xmm3
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; AVX-NEXT: vpshufb %xmm1, %xmm3, %xmm3
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; AVX-NEXT: vpand %xmm0, %xmm3, %xmm3
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; AVX-NEXT: vpsllw $7, %xmm3, %xmm3
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; AVX-NEXT: vpand %xmm2, %xmm3, %xmm3
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; AVX-NEXT: vpcmpgtb %xmm3, %xmm1, %xmm3
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; AVX-NEXT: vpmovmskb %xmm3, %eax
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; AVX-NEXT: testw %ax, %ax
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2017-02-12 03:27:15 +08:00
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; AVX-NEXT: jne .LBB1_1
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; AVX-NEXT: # BB#2: # %for_exit600
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; AVX-NEXT: retq
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;
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2016-02-01 15:56:09 +08:00
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; KNL-32-LABEL: pr26232:
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2016-04-05 22:06:20 +08:00
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; KNL-32: # BB#0: # %for_loop599.preheader
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2016-02-01 15:56:09 +08:00
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; KNL-32-NEXT: pushl %esi
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2016-12-01 07:48:26 +08:00
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; KNL-32-NEXT: .Lcfi0:
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2016-02-01 15:56:09 +08:00
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; KNL-32-NEXT: .cfi_def_cfa_offset 8
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2016-12-01 07:48:26 +08:00
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; KNL-32-NEXT: .Lcfi1:
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2016-02-01 15:56:09 +08:00
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; KNL-32-NEXT: .cfi_offset %esi, -8
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2017-05-30 02:27:00 +08:00
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; KNL-32-NEXT: vpmovsxbd %xmm0, %zmm0
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; KNL-32-NEXT: vpslld $31, %zmm0, %zmm0
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; KNL-32-NEXT: vptestmd %zmm0, %zmm0, %k0
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2016-02-01 15:56:09 +08:00
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; KNL-32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; KNL-32-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; KNL-32-NEXT: movw $-1, %dx
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; KNL-32-NEXT: .p2align 4, 0x90
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; KNL-32-NEXT: .LBB1_1: # %for_loop599
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; KNL-32-NEXT: # =>This Inner Loop Header: Depth=1
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; KNL-32-NEXT: cmpl $65536, %ecx # imm = 0x10000
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; KNL-32-NEXT: movl %eax, %esi
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; KNL-32-NEXT: sbbl $0, %esi
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; KNL-32-NEXT: movl $0, %esi
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; KNL-32-NEXT: cmovlw %dx, %si
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2017-05-30 02:27:00 +08:00
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; KNL-32-NEXT: kmovw %esi, %k1
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; KNL-32-NEXT: kandw %k0, %k1, %k1
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; KNL-32-NEXT: kmovw %k1, %esi
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2016-02-01 15:56:09 +08:00
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; KNL-32-NEXT: testw %si, %si
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; KNL-32-NEXT: jne .LBB1_1
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; KNL-32-NEXT: # BB#2: # %for_exit600
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; KNL-32-NEXT: popl %esi
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2017-06-28 18:21:17 +08:00
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; KNL-32-NEXT: .Lcfi2:
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; KNL-32-NEXT: .cfi_def_cfa_offset 4
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2016-02-01 15:56:09 +08:00
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; KNL-32-NEXT: retl
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allocas:
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br label %for_test11.preheader
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for_test11.preheader: ; preds = %for_test11.preheader, %allocas
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br i1 undef, label %for_loop599, label %for_test11.preheader
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for_loop599: ; preds = %for_loop599, %for_test11.preheader
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%less_i_load605_ = icmp slt i64 %a, 65536
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%less_i_load605__broadcast_init = insertelement <16 x i1> undef, i1 %less_i_load605_, i32 0
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%less_i_load605__broadcast = shufflevector <16 x i1> %less_i_load605__broadcast_init, <16 x i1> undef, <16 x i32> zeroinitializer
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2017-05-30 02:27:00 +08:00
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%"oldMask&test607" = and <16 x i1> %less_i_load605__broadcast, %b
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2016-02-01 15:56:09 +08:00
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%intmask.i894 = bitcast <16 x i1> %"oldMask&test607" to i16
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%res.i895 = icmp eq i16 %intmask.i894, 0
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br i1 %res.i895, label %for_exit600, label %for_loop599
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for_exit600: ; preds = %for_loop599
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ret void
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}
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