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llvm-project/llvm/test/CodeGen/Mips/mno-ldc1-sdc1.ll

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[mips] Enhance command line option "-mno-ldc1-sdc1" to expand base+index double precision loads and stores as well as reg+imm double precision loads and stores. Previously, expansion of loads and stores was done after register allocation, but now it takes place during legalization. As a result, users will see double precision stores and loads being emitted to spill and restore 64-bit FP registers. llvm-svn: 190235
2013-09-07 08:52:30 +08:00
; RUN: llc -march=mipsel -relocation-model=pic -mno-ldc1-sdc1 -mcpu=mips32r2 \
; RUN: < %s | FileCheck %s -check-prefix=LE-PIC
[mips] Add option -mno-ldc1-sdc1. This option is used when the user wants to avoid emitting double precision FP loads and stores. Double precision FP loads and stores are expanded to single precision instructions after register allocation. llvm-svn: 181718
2013-05-14 02:23:35 +08:00
; RUN: llc -march=mipsel -relocation-model=static -mno-ldc1-sdc1 < %s | \
; RUN: FileCheck %s -check-prefix=LE-STATIC
; RUN: llc -march=mips -relocation-model=pic -mno-ldc1-sdc1 < %s | \
; RUN: FileCheck %s -check-prefix=BE-PIC
[mips] Enhance command line option "-mno-ldc1-sdc1" to expand base+index double precision loads and stores as well as reg+imm double precision loads and stores. Previously, expansion of loads and stores was done after register allocation, but now it takes place during legalization. As a result, users will see double precision stores and loads being emitted to spill and restore 64-bit FP registers. llvm-svn: 190235
2013-09-07 08:52:30 +08:00
; RUN: llc -march=mipsel -mcpu=mips32r2 < %s | \
; RUN: FileCheck %s -check-prefix=CHECK-LDC1-SDC1
[mips] Add option -mno-ldc1-sdc1. This option is used when the user wants to avoid emitting double precision FP loads and stores. Double precision FP loads and stores are expanded to single precision instructions after register allocation. llvm-svn: 181718
2013-05-14 02:23:35 +08:00
@g0 = common global double 0.000000e+00, align 8
Mass update to CodeGen tests to use CHECK-LABEL for labels corresponding to function definitions for more informative error messages. No functionality change and all updated tests passed locally. This update was done with the following bash script: find test/CodeGen -name "*.ll" | \ while read NAME; do echo "$NAME" if ! grep -q "^; *RUN: *llc.*debug" $NAME; then TEMP=`mktemp -t temp` cp $NAME $TEMP sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \ while read FUNC; do sed -i '' "s/;\(.*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC: *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP done sed -i '' "s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP sed -i '' "s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP sed -i '' "s/;\(.*\)-NOT-LABEL:/;\1-NOT:/" $TEMP sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP mv $TEMP $NAME fi done llvm-svn: 186280
2013-07-14 14:24:09 +08:00
; LE-PIC-LABEL: test_ldc1:
[mips] Enhance command line option "-mno-ldc1-sdc1" to expand base+index double precision loads and stores as well as reg+imm double precision loads and stores. Previously, expansion of loads and stores was done after register allocation, but now it takes place during legalization. As a result, users will see double precision stores and loads being emitted to spill and restore 64-bit FP registers. llvm-svn: 190235
2013-09-07 08:52:30 +08:00
; LE-PIC-DAG: lw $[[R0:[0-9]+]], 0(${{[0-9]+}})
; LE-PIC-DAG: lw $[[R1:[0-9]+]], 4(${{[0-9]+}})
; LE-PIC-DAG: mtc1 $[[R0]], $f0
[mips] Use MTHC1 when it is available (MIPS32r2 and later) for both FP32 and FP64 Summary: To make this work for both AFGR64 and FGR64 register sets, I've had to make the instruction definition consistent with the white lie (that it reads the lower 32-bits of the register) when they are generated by expandBuildPairF64(). Corrected the definition of hasMips32r2() and hasMips64r2() to include MIPS32r6 and MIPS64r6. Depends on D3956 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3957 llvm-svn: 210771
2014-06-12 19:55:58 +08:00
; LE-PIC-DAG: mthc1 $[[R1]], $f0
Mass update to CodeGen tests to use CHECK-LABEL for labels corresponding to function definitions for more informative error messages. No functionality change and all updated tests passed locally. This update was done with the following bash script: find test/CodeGen -name "*.ll" | \ while read NAME; do echo "$NAME" if ! grep -q "^; *RUN: *llc.*debug" $NAME; then TEMP=`mktemp -t temp` cp $NAME $TEMP sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \ while read FUNC; do sed -i '' "s/;\(.*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC: *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP done sed -i '' "s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP sed -i '' "s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP sed -i '' "s/;\(.*\)-NOT-LABEL:/;\1-NOT:/" $TEMP sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP mv $TEMP $NAME fi done llvm-svn: 186280
2013-07-14 14:24:09 +08:00
; LE-STATIC-LABEL: test_ldc1:
[mips] Enhance command line option "-mno-ldc1-sdc1" to expand base+index double precision loads and stores as well as reg+imm double precision loads and stores. Previously, expansion of loads and stores was done after register allocation, but now it takes place during legalization. As a result, users will see double precision stores and loads being emitted to spill and restore 64-bit FP registers. llvm-svn: 190235
2013-09-07 08:52:30 +08:00
; LE-STATIC-DAG: lui $[[R0:[0-9]+]], %hi(g0)
; LE-STATIC-DAG: lw $[[R1:[0-9]+]], %lo(g0)($[[R0]])
; LE-STATIC-DAG: addiu $[[R2:[0-9]+]], $[[R0]], %lo(g0)
; LE-STATIC-DAG: lw $[[R3:[0-9]+]], 4($[[R2]])
; LE-STATIC-DAG: mtc1 $[[R1]], $f0
; LE-STATIC-DAG: mtc1 $[[R3]], $f1
Mass update to CodeGen tests to use CHECK-LABEL for labels corresponding to function definitions for more informative error messages. No functionality change and all updated tests passed locally. This update was done with the following bash script: find test/CodeGen -name "*.ll" | \ while read NAME; do echo "$NAME" if ! grep -q "^; *RUN: *llc.*debug" $NAME; then TEMP=`mktemp -t temp` cp $NAME $TEMP sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \ while read FUNC; do sed -i '' "s/;\(.*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC: *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP done sed -i '' "s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP sed -i '' "s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP sed -i '' "s/;\(.*\)-NOT-LABEL:/;\1-NOT:/" $TEMP sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP mv $TEMP $NAME fi done llvm-svn: 186280
2013-07-14 14:24:09 +08:00
; BE-PIC-LABEL: test_ldc1:
[mips] Enhance command line option "-mno-ldc1-sdc1" to expand base+index double precision loads and stores as well as reg+imm double precision loads and stores. Previously, expansion of loads and stores was done after register allocation, but now it takes place during legalization. As a result, users will see double precision stores and loads being emitted to spill and restore 64-bit FP registers. llvm-svn: 190235
2013-09-07 08:52:30 +08:00
; BE-PIC-DAG: lw $[[R0:[0-9]+]], 0(${{[0-9]+}})
; BE-PIC-DAG: lw $[[R1:[0-9]+]], 4(${{[0-9]+}})
; BE-PIC-DAG: mtc1 $[[R1]], $f0
; BE-PIC-DAG: mtc1 $[[R0]], $f1
Mass update to CodeGen tests to use CHECK-LABEL for labels corresponding to function definitions for more informative error messages. No functionality change and all updated tests passed locally. This update was done with the following bash script: find test/CodeGen -name "*.ll" | \ while read NAME; do echo "$NAME" if ! grep -q "^; *RUN: *llc.*debug" $NAME; then TEMP=`mktemp -t temp` cp $NAME $TEMP sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \ while read FUNC; do sed -i '' "s/;\(.*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC: *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP done sed -i '' "s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP sed -i '' "s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP sed -i '' "s/;\(.*\)-NOT-LABEL:/;\1-NOT:/" $TEMP sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP mv $TEMP $NAME fi done llvm-svn: 186280
2013-07-14 14:24:09 +08:00
; CHECK-LDC1-SDC1-LABEL: test_ldc1:
[mips] Add option -mno-ldc1-sdc1. This option is used when the user wants to avoid emitting double precision FP loads and stores. Double precision FP loads and stores are expanded to single precision instructions after register allocation. llvm-svn: 181718
2013-05-14 02:23:35 +08:00
; CHECK-LDC1-SDC1: ldc1 $f{{[0-9]+}}
define double @test_ldc1() {
entry:
%0 = load double* @g0, align 8
ret double %0
}
Mass update to CodeGen tests to use CHECK-LABEL for labels corresponding to function definitions for more informative error messages. No functionality change and all updated tests passed locally. This update was done with the following bash script: find test/CodeGen -name "*.ll" | \ while read NAME; do echo "$NAME" if ! grep -q "^; *RUN: *llc.*debug" $NAME; then TEMP=`mktemp -t temp` cp $NAME $TEMP sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \ while read FUNC; do sed -i '' "s/;\(.*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC: *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP done sed -i '' "s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP sed -i '' "s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP sed -i '' "s/;\(.*\)-NOT-LABEL:/;\1-NOT:/" $TEMP sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP mv $TEMP $NAME fi done llvm-svn: 186280
2013-07-14 14:24:09 +08:00
; LE-PIC-LABEL: test_sdc1:
[mips] Enhance command line option "-mno-ldc1-sdc1" to expand base+index double precision loads and stores as well as reg+imm double precision loads and stores. Previously, expansion of loads and stores was done after register allocation, but now it takes place during legalization. As a result, users will see double precision stores and loads being emitted to spill and restore 64-bit FP registers. llvm-svn: 190235
2013-09-07 08:52:30 +08:00
; LE-PIC-DAG: mfc1 $[[R0:[0-9]+]], $f12
; LE-PIC-DAG: mfc1 $[[R1:[0-9]+]], $f13
; LE-PIC-DAG: sw $[[R0]], 0(${{[0-9]+}})
; LE-PIC-DAG: sw $[[R1]], 4(${{[0-9]+}})
Mass update to CodeGen tests to use CHECK-LABEL for labels corresponding to function definitions for more informative error messages. No functionality change and all updated tests passed locally. This update was done with the following bash script: find test/CodeGen -name "*.ll" | \ while read NAME; do echo "$NAME" if ! grep -q "^; *RUN: *llc.*debug" $NAME; then TEMP=`mktemp -t temp` cp $NAME $TEMP sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \ while read FUNC; do sed -i '' "s/;\(.*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC: *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP done sed -i '' "s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP sed -i '' "s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP sed -i '' "s/;\(.*\)-NOT-LABEL:/;\1-NOT:/" $TEMP sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP mv $TEMP $NAME fi done llvm-svn: 186280
2013-07-14 14:24:09 +08:00
; LE-STATIC-LABEL: test_sdc1:
[mips] Enhance command line option "-mno-ldc1-sdc1" to expand base+index double precision loads and stores as well as reg+imm double precision loads and stores. Previously, expansion of loads and stores was done after register allocation, but now it takes place during legalization. As a result, users will see double precision stores and loads being emitted to spill and restore 64-bit FP registers. llvm-svn: 190235
2013-09-07 08:52:30 +08:00
; LE-STATIC-DAG: mfc1 $[[R0:[0-9]+]], $f12
; LE-STATIC-DAG: mfc1 $[[R1:[0-9]+]], $f13
; LE-STATIC-DAG: lui $[[R2:[0-9]+]], %hi(g0)
; LE-STATIC-DAG: sw $[[R0]], %lo(g0)($[[R2]])
; LE-STATIC-DAG: addiu $[[R3:[0-9]+]], $[[R2]], %lo(g0)
; LE-STATIC-DAG: sw $[[R1]], 4($[[R3]])
Mass update to CodeGen tests to use CHECK-LABEL for labels corresponding to function definitions for more informative error messages. No functionality change and all updated tests passed locally. This update was done with the following bash script: find test/CodeGen -name "*.ll" | \ while read NAME; do echo "$NAME" if ! grep -q "^; *RUN: *llc.*debug" $NAME; then TEMP=`mktemp -t temp` cp $NAME $TEMP sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \ while read FUNC; do sed -i '' "s/;\(.*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC: *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP done sed -i '' "s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP sed -i '' "s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP sed -i '' "s/;\(.*\)-NOT-LABEL:/;\1-NOT:/" $TEMP sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP mv $TEMP $NAME fi done llvm-svn: 186280
2013-07-14 14:24:09 +08:00
; BE-PIC-LABEL: test_sdc1:
[mips] Enhance command line option "-mno-ldc1-sdc1" to expand base+index double precision loads and stores as well as reg+imm double precision loads and stores. Previously, expansion of loads and stores was done after register allocation, but now it takes place during legalization. As a result, users will see double precision stores and loads being emitted to spill and restore 64-bit FP registers. llvm-svn: 190235
2013-09-07 08:52:30 +08:00
; BE-PIC-DAG: mfc1 $[[R0:[0-9]+]], $f12
; BE-PIC-DAG: mfc1 $[[R1:[0-9]+]], $f13
; BE-PIC-DAG: sw $[[R1]], 0(${{[0-9]+}})
; BE-PIC-DAG: sw $[[R0]], 4(${{[0-9]+}})
Mass update to CodeGen tests to use CHECK-LABEL for labels corresponding to function definitions for more informative error messages. No functionality change and all updated tests passed locally. This update was done with the following bash script: find test/CodeGen -name "*.ll" | \ while read NAME; do echo "$NAME" if ! grep -q "^; *RUN: *llc.*debug" $NAME; then TEMP=`mktemp -t temp` cp $NAME $TEMP sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \ while read FUNC; do sed -i '' "s/;\(.*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC: *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP done sed -i '' "s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP sed -i '' "s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP sed -i '' "s/;\(.*\)-NOT-LABEL:/;\1-NOT:/" $TEMP sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP mv $TEMP $NAME fi done llvm-svn: 186280
2013-07-14 14:24:09 +08:00
; CHECK-LDC1-SDC1-LABEL: test_sdc1:
[mips] Add option -mno-ldc1-sdc1. This option is used when the user wants to avoid emitting double precision FP loads and stores. Double precision FP loads and stores are expanded to single precision instructions after register allocation. llvm-svn: 181718
2013-05-14 02:23:35 +08:00
; CHECK-LDC1-SDC1: sdc1 $f{{[0-9]+}}
define void @test_sdc1(double %a) {
entry:
store double %a, double* @g0, align 8
ret void
}
[mips] Enhance command line option "-mno-ldc1-sdc1" to expand base+index double precision loads and stores as well as reg+imm double precision loads and stores. Previously, expansion of loads and stores was done after register allocation, but now it takes place during legalization. As a result, users will see double precision stores and loads being emitted to spill and restore 64-bit FP registers. llvm-svn: 190235
2013-09-07 08:52:30 +08:00
[mips] Fix typos. llvm-svn: 190236
2013-09-07 09:14:42 +08:00
; LE-PIC-LABEL: test_ldxc1:
[mips] Enhance command line option "-mno-ldc1-sdc1" to expand base+index double precision loads and stores as well as reg+imm double precision loads and stores. Previously, expansion of loads and stores was done after register allocation, but now it takes place during legalization. As a result, users will see double precision stores and loads being emitted to spill and restore 64-bit FP registers. llvm-svn: 190235
2013-09-07 08:52:30 +08:00
; LE-PIC-DAG: lw $[[R0:[0-9]+]], 0(${{[0-9]+}})
; LE-PIC-DAG: lw $[[R1:[0-9]+]], 4(${{[0-9]+}})
; LE-PIC-DAG: mtc1 $[[R0]], $f0
[mips] Use MTHC1 when it is available (MIPS32r2 and later) for both FP32 and FP64 Summary: To make this work for both AFGR64 and FGR64 register sets, I've had to make the instruction definition consistent with the white lie (that it reads the lower 32-bits of the register) when they are generated by expandBuildPairF64(). Corrected the definition of hasMips32r2() and hasMips64r2() to include MIPS32r6 and MIPS64r6. Depends on D3956 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3957 llvm-svn: 210771
2014-06-12 19:55:58 +08:00
; LE-PIC-DAG: mthc1 $[[R1]], $f0
[mips] Enhance command line option "-mno-ldc1-sdc1" to expand base+index double precision loads and stores as well as reg+imm double precision loads and stores. Previously, expansion of loads and stores was done after register allocation, but now it takes place during legalization. As a result, users will see double precision stores and loads being emitted to spill and restore 64-bit FP registers. llvm-svn: 190235
2013-09-07 08:52:30 +08:00
; CHECK-LDC1-SDC1-LABEL: test_ldxc1:
; CHECK-LDC1-SDC1: ldxc1 $f{{[0-9]+}}
define double @test_ldxc1(double* nocapture readonly %a, i32 %i) {
entry:
%arrayidx = getelementptr inbounds double* %a, i32 %i
%0 = load double* %arrayidx, align 8
ret double %0
}
[mips] Fix typos. llvm-svn: 190236
2013-09-07 09:14:42 +08:00
; LE-PIC-LABEL: test_sdxc1:
[mips] Enhance command line option "-mno-ldc1-sdc1" to expand base+index double precision loads and stores as well as reg+imm double precision loads and stores. Previously, expansion of loads and stores was done after register allocation, but now it takes place during legalization. As a result, users will see double precision stores and loads being emitted to spill and restore 64-bit FP registers. llvm-svn: 190235
2013-09-07 08:52:30 +08:00
; LE-PIC-DAG: mfc1 $[[R0:[0-9]+]], $f12
; LE-PIC-DAG: mfc1 $[[R1:[0-9]+]], $f13
; LE-PIC-DAG: sw $[[R0]], 0(${{[0-9]+}})
; LE-PIC-DAG: sw $[[R1]], 4(${{[0-9]+}})
; CHECK-LDC1-SDC1-LABEL: test_sdxc1:
; CHECK-LDC1-SDC1: sdxc1 $f{{[0-9]+}}
define void @test_sdxc1(double %b, double* nocapture %a, i32 %i) {
entry:
%arrayidx = getelementptr inbounds double* %a, i32 %i
store double %b, double* %arrayidx, align 8
ret void
}