llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck %s

---
name: test_and_s32
body: |
  bb.0:
    liveins: $vgpr0, $vgpr1

    ; CHECK-LABEL: name: test_and_s32
    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
    ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[COPY1]]
    ; CHECK: $vgpr0 = COPY [[AND]](s32)
    %0:_(s32) = COPY $vgpr0
    %1:_(s32) = COPY $vgpr1
    %2:_(s32) = G_AND %0, %1
    $vgpr0 = COPY %2
...

---
name: test_and_s1
body: |
  bb.0:
    liveins: $vgpr0, $vgpr1

    ; CHECK-LABEL: name: test_and_s1
    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
    ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[COPY1]]
    ; CHECK: S_NOP 0, implicit [[AND]](s32)
    %0:_(s32) = COPY $vgpr0
    %1:_(s32) = COPY $vgpr1
    %2:_(s32) = G_CONSTANT i32 0
    %3:_(s1) = G_ICMP intpred(ne), %0, %2
    %4:_(s1) = G_ICMP intpred(ne), %1, %2
    %5:_(s32) = G_AND %0, %1
    S_NOP 0, implicit %5
...

---
name: test_and_s64
body: |
  bb.0:
    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3

    ; CHECK-LABEL: name: test_and_s64
    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
    ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
    ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[COPY1]]
    ; CHECK: $vgpr0_vgpr1 = COPY [[AND]](s64)
    %0:_(s64) = COPY $vgpr0_vgpr1
    %1:_(s64) = COPY $vgpr2_vgpr3
    %2:_(s64) = G_AND %0, %1
    $vgpr0_vgpr1 = COPY %2
...

---
name: test_and_s7
body: |
  bb.0:
    liveins: $vgpr0, $vgpr1

    ; CHECK-LABEL: name: test_and_s7
    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
    ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
    ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
    ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[COPY3]]
    ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[AND]](s32)
    ; CHECK: $vgpr0 = COPY [[COPY4]](s32)
    %0:_(s32) = COPY $vgpr0
    %1:_(s32) = COPY $vgpr1
    %2:_(s7) = G_TRUNC %0
    %3:_(s7) = G_TRUNC %1
    %4:_(s7) = G_AND %2, %3
    %5:_(s32) = G_ANYEXT %4
    $vgpr0 = COPY %5
...

---
name: test_and_s8
body: |
  bb.0:
    liveins: $vgpr0, $vgpr1

    ; CHECK-LABEL: name: test_and_s8
    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
    ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
    ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
    ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[COPY3]]
    ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[AND]](s32)
    ; CHECK: $vgpr0 = COPY [[COPY4]](s32)
    %0:_(s32) = COPY $vgpr0
    %1:_(s32) = COPY $vgpr1
    %2:_(s8) = G_TRUNC %0
    %3:_(s8) = G_TRUNC %1
    %4:_(s8) = G_AND %2, %3
    %5:_(s32) = G_ANYEXT %4
    $vgpr0 = COPY %5
...

---
name: test_and_s16
body: |
  bb.0:
    liveins: $vgpr0, $vgpr1

    ; CHECK-LABEL: name: test_and_s16
    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
    ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
    ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
    ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[COPY3]]
    ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[AND]](s32)
    ; CHECK: $vgpr0 = COPY [[COPY4]](s32)
    %0:_(s32) = COPY $vgpr0
    %1:_(s32) = COPY $vgpr1
    %2:_(s16) = G_TRUNC %0
    %3:_(s16) = G_TRUNC %1
    %4:_(s16) = G_AND %2, %3
    %5:_(s32) = G_ANYEXT %4
    $vgpr0 = COPY %5
...

---
name: test_and_s24
body: |
  bb.0:
    liveins: $vgpr0, $vgpr1

    ; CHECK-LABEL: name: test_and_s24
    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
    ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
    ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
    ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[COPY3]]
    ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[AND]](s32)
    ; CHECK: $vgpr0 = COPY [[COPY4]](s32)
    %0:_(s32) = COPY $vgpr0
    %1:_(s32) = COPY $vgpr1
    %2:_(s24) = G_TRUNC %0
    %3:_(s24) = G_TRUNC %1
    %4:_(s24) = G_AND %2, %3
    %5:_(s32) = G_ANYEXT %4
    $vgpr0 = COPY %5
...

---
name: test_and_v2s32
body: |
  bb.0:
    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3

    ; CHECK-LABEL: name: test_and_v2s32
    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
    ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
    ; CHECK: [[AND:%[0-9]+]]:_(<2 x s32>) = G_AND [[COPY]], [[COPY1]]
    ; CHECK: $vgpr0_vgpr1 = COPY [[AND]](<2 x s32>)
    %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
    %1:_(<2 x s32>) = COPY $vgpr2_vgpr3
    %2:_(<2 x s32>) = G_AND %0, %1
    $vgpr0_vgpr1 = COPY %2
...

---
name: test_and_v3s32
body: |
  bb.0:
    liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5

    ; CHECK-LABEL: name: test_and_v3s32
    ; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
    ; CHECK: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr3_vgpr4_vgpr5
    ; CHECK: [[DEF:%[0-9]+]]:_(<3 x s32>) = G_IMPLICIT_DEF
    ; CHECK: [[EXTRACT:%[0-9]+]]:_(<2 x s32>) = G_EXTRACT [[COPY]](<3 x s32>), 0
    ; CHECK: [[EXTRACT1:%[0-9]+]]:_(<2 x s32>) = G_EXTRACT [[COPY1]](<3 x s32>), 0
    ; CHECK: [[AND:%[0-9]+]]:_(<2 x s32>) = G_AND [[EXTRACT]], [[EXTRACT1]]
    ; CHECK: [[INSERT:%[0-9]+]]:_(<3 x s32>) = G_INSERT [[DEF]], [[AND]](<2 x s32>), 0
    ; CHECK: [[EXTRACT2:%[0-9]+]]:_(s32) = G_EXTRACT [[COPY]](<3 x s32>), 64
    ; CHECK: [[EXTRACT3:%[0-9]+]]:_(s32) = G_EXTRACT [[COPY1]](<3 x s32>), 64
    ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[EXTRACT2]], [[EXTRACT3]]
    ; CHECK: [[INSERT1:%[0-9]+]]:_(<3 x s32>) = G_INSERT [[INSERT]], [[AND1]](s32), 64
    ; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[INSERT1]](<3 x s32>)
    %0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
    %1:_(<3 x s32>) = COPY $vgpr3_vgpr4_vgpr5
    %2:_(<3 x s32>) = G_AND %0, %1
    $vgpr0_vgpr1_vgpr2 = COPY %2
...

---
name: test_and_v4s32
body: |
  bb.0:
    liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7

    ; CHECK-LABEL: name: test_and_v4s32
    ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
    ; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
    ; CHECK: [[UV:%[0-9]+]]:_(<2 x s32>), [[UV1:%[0-9]+]]:_(<2 x s32>) = G_UNMERGE_VALUES [[COPY]](<4 x s32>)
    ; CHECK: [[UV2:%[0-9]+]]:_(<2 x s32>), [[UV3:%[0-9]+]]:_(<2 x s32>) = G_UNMERGE_VALUES [[COPY1]](<4 x s32>)
    ; CHECK: [[AND:%[0-9]+]]:_(<2 x s32>) = G_AND [[UV]], [[UV2]]
    ; CHECK: [[AND1:%[0-9]+]]:_(<2 x s32>) = G_AND [[UV1]], [[UV3]]
    ; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s32>) = G_CONCAT_VECTORS [[AND]](<2 x s32>), [[AND1]](<2 x s32>)
    ; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[CONCAT_VECTORS]](<4 x s32>)
    %0:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
    %1:_(<4 x s32>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
    %2:_(<4 x s32>) = G_AND %0, %1
    $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %2
...

---
name: test_and_v5s32
body: |
  bb.0:

    ; CHECK-LABEL: name: test_and_v5s32
    ; CHECK: [[DEF:%[0-9]+]]:_(<5 x s32>) = G_IMPLICIT_DEF
    ; CHECK: [[DEF1:%[0-9]+]]:_(<5 x s32>) = G_IMPLICIT_DEF
    ; CHECK: [[DEF2:%[0-9]+]]:_(<5 x s32>) = G_IMPLICIT_DEF
    ; CHECK: [[EXTRACT:%[0-9]+]]:_(<2 x s32>) = G_EXTRACT [[DEF]](<5 x s32>), 0
    ; CHECK: [[EXTRACT1:%[0-9]+]]:_(<2 x s32>) = G_EXTRACT [[DEF1]](<5 x s32>), 0
    ; CHECK: [[AND:%[0-9]+]]:_(<2 x s32>) = G_AND [[EXTRACT]], [[EXTRACT1]]
    ; CHECK: [[INSERT:%[0-9]+]]:_(<5 x s32>) = G_INSERT [[DEF2]], [[AND]](<2 x s32>), 0
    ; CHECK: [[EXTRACT2:%[0-9]+]]:_(<2 x s32>) = G_EXTRACT [[DEF]](<5 x s32>), 64
    ; CHECK: [[EXTRACT3:%[0-9]+]]:_(<2 x s32>) = G_EXTRACT [[DEF1]](<5 x s32>), 64
    ; CHECK: [[AND1:%[0-9]+]]:_(<2 x s32>) = G_AND [[EXTRACT2]], [[EXTRACT3]]
    ; CHECK: [[INSERT1:%[0-9]+]]:_(<5 x s32>) = G_INSERT [[INSERT]], [[AND1]](<2 x s32>), 64
    ; CHECK: [[EXTRACT4:%[0-9]+]]:_(s32) = G_EXTRACT [[DEF]](<5 x s32>), 128
    ; CHECK: [[EXTRACT5:%[0-9]+]]:_(s32) = G_EXTRACT [[DEF1]](<5 x s32>), 128
    ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[EXTRACT4]], [[EXTRACT5]]
    ; CHECK: [[INSERT2:%[0-9]+]]:_(<5 x s32>) = G_INSERT [[INSERT1]], [[AND2]](s32), 128
    ; CHECK: [[DEF3:%[0-9]+]]:_(<8 x s32>) = G_IMPLICIT_DEF
    ; CHECK: [[INSERT3:%[0-9]+]]:_(<8 x s32>) = G_INSERT [[DEF3]], [[INSERT2]](<5 x s32>), 0
    ; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[INSERT3]](<8 x s32>)
    %0:_(<5 x s32>) = G_IMPLICIT_DEF
    %1:_(<5 x s32>) = G_IMPLICIT_DEF
    %2:_(<5 x s32>) = G_AND %0, %1
    %3:_(<8 x s32>) = G_IMPLICIT_DEF
    %4:_(<8 x s32>) = G_INSERT %3, %2, 0
    $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY %4
...

---
name: test_and_v2s64
body: |
  bb.0:
    liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7

    ; CHECK-LABEL: name: test_and_v2s64
    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
    ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
    ; CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
    ; CHECK: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY1]](<2 x s64>)
    ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[UV]], [[UV2]]
    ; CHECK: [[AND1:%[0-9]+]]:_(s64) = G_AND [[UV1]], [[UV3]]
    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[AND]](s64), [[AND1]](s64)
    ; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
    %0:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
    %1:_(<2 x s64>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
    %2:_(<2 x s64>) = G_AND %0, %1
    $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %2
...

---
name: test_and_v2s16
body: |
  bb.0:
    liveins: $vgpr0, $vgpr1

    ; CHECK-LABEL: name: test_and_v2s16
    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
    ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
    ; CHECK: [[AND:%[0-9]+]]:_(<2 x s16>) = G_AND [[COPY]], [[COPY1]]
    ; CHECK: $vgpr0 = COPY [[AND]](<2 x s16>)
    %0:_(<2 x s16>) = COPY $vgpr0
    %1:_(<2 x s16>) = COPY $vgpr1
    %2:_(<2 x s16>) = G_AND %0, %1
    $vgpr0 = COPY %2
...

---
name: test_and_v3s16
body: |
  bb.0:

    ; CHECK-LABEL: name: test_and_v3s16
    ; CHECK: [[DEF:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
    ; CHECK: [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[DEF]](<4 x s16>), 0
    ; CHECK: [[DEF1:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
    ; CHECK: [[EXTRACT1:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[DEF1]](<4 x s16>), 0
    ; CHECK: [[DEF2:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
    ; CHECK: [[INSERT:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF2]], [[EXTRACT]](<3 x s16>), 0
    ; CHECK: [[DEF3:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
    ; CHECK: [[INSERT1:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF3]], [[EXTRACT1]](<3 x s16>), 0
    ; CHECK: [[AND:%[0-9]+]]:_(<4 x s16>) = G_AND [[INSERT]], [[INSERT1]]
    ; CHECK: [[EXTRACT2:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[AND]](<4 x s16>), 0
    ; CHECK: [[DEF4:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
    ; CHECK: [[INSERT2:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF4]], [[EXTRACT2]](<3 x s16>), 0
    ; CHECK: $vgpr0_vgpr1 = COPY [[INSERT2]](<4 x s16>)
    %0:_(<3 x s16>) = G_IMPLICIT_DEF
    %1:_(<3 x s16>) = G_IMPLICIT_DEF
    %2:_(<3 x s16>) = G_AND %0, %1
    %4:_(<4 x s16>) = G_IMPLICIT_DEF
    %5:_(<4 x s16>) = G_INSERT %4, %2, 0
    $vgpr0_vgpr1 = COPY %5
...

---
name: test_and_v4s16
body: |
  bb.0:
    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3

    ; CHECK-LABEL: name: test_and_v4s16
    ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
    ; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr2_vgpr3
    ; CHECK: [[AND:%[0-9]+]]:_(<4 x s16>) = G_AND [[COPY]], [[COPY1]]
    ; CHECK: $vgpr0_vgpr1 = COPY [[AND]](<4 x s16>)
    %0:_(<4 x s16>) = COPY $vgpr0_vgpr1
    %1:_(<4 x s16>) = COPY $vgpr2_vgpr3
    %2:_(<4 x s16>) = G_AND %0, %1
    $vgpr0_vgpr1 = COPY %2
...

---
name: test_and_v5s16
body: |
  bb.0:

    ; CHECK-LABEL: name: test_and_v5s16
    ; CHECK: [[DEF:%[0-9]+]]:_(<6 x s32>) = G_IMPLICIT_DEF
    ; CHECK: [[TRUNC:%[0-9]+]]:_(<6 x s16>) = G_TRUNC [[DEF]](<6 x s32>)
    ; CHECK: [[EXTRACT:%[0-9]+]]:_(<5 x s16>) = G_EXTRACT [[TRUNC]](<6 x s16>), 0
    ; CHECK: [[DEF1:%[0-9]+]]:_(<6 x s32>) = G_IMPLICIT_DEF
    ; CHECK: [[TRUNC1:%[0-9]+]]:_(<6 x s16>) = G_TRUNC [[DEF1]](<6 x s32>)
    ; CHECK: [[EXTRACT1:%[0-9]+]]:_(<5 x s16>) = G_EXTRACT [[TRUNC1]](<6 x s16>), 0
    ; CHECK: [[DEF2:%[0-9]+]]:_(<6 x s32>) = G_IMPLICIT_DEF
    ; CHECK: [[TRUNC2:%[0-9]+]]:_(<6 x s16>) = G_TRUNC [[DEF2]](<6 x s32>)
    ; CHECK: [[INSERT:%[0-9]+]]:_(<6 x s16>) = G_INSERT [[TRUNC2]], [[EXTRACT]](<5 x s16>), 0
    ; CHECK: [[DEF3:%[0-9]+]]:_(<6 x s32>) = G_IMPLICIT_DEF
    ; CHECK: [[TRUNC3:%[0-9]+]]:_(<6 x s16>) = G_TRUNC [[DEF3]](<6 x s32>)
    ; CHECK: [[INSERT1:%[0-9]+]]:_(<6 x s16>) = G_INSERT [[TRUNC3]], [[EXTRACT1]](<5 x s16>), 0
    ; CHECK: [[UV:%[0-9]+]]:_(<3 x s16>), [[UV1:%[0-9]+]]:_(<3 x s16>) = G_UNMERGE_VALUES [[INSERT]](<6 x s16>)
    ; CHECK: [[UV2:%[0-9]+]]:_(<3 x s16>), [[UV3:%[0-9]+]]:_(<3 x s16>) = G_UNMERGE_VALUES [[INSERT1]](<6 x s16>)
    ; CHECK: [[DEF4:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
    ; CHECK: [[INSERT2:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF4]], [[UV]](<3 x s16>), 0
    ; CHECK: [[DEF5:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
    ; CHECK: [[INSERT3:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF5]], [[UV2]](<3 x s16>), 0
    ; CHECK: [[AND:%[0-9]+]]:_(<4 x s16>) = G_AND [[INSERT2]], [[INSERT3]]
    ; CHECK: [[EXTRACT2:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[AND]](<4 x s16>), 0
    ; CHECK: [[DEF6:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
    ; CHECK: [[INSERT4:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF6]], [[UV1]](<3 x s16>), 0
    ; CHECK: [[DEF7:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
    ; CHECK: [[INSERT5:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF7]], [[UV3]](<3 x s16>), 0
    ; CHECK: [[AND1:%[0-9]+]]:_(<4 x s16>) = G_AND [[INSERT4]], [[INSERT5]]
    ; CHECK: [[EXTRACT3:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[AND1]](<4 x s16>), 0
    ; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[EXTRACT2]](<3 x s16>), [[EXTRACT3]](<3 x s16>)
    ; CHECK: [[EXTRACT4:%[0-9]+]]:_(<5 x s16>) = G_EXTRACT [[CONCAT_VECTORS]](<6 x s16>), 0
    ; CHECK: [[DEF8:%[0-9]+]]:_(<8 x s32>) = G_IMPLICIT_DEF
    ; CHECK: [[TRUNC4:%[0-9]+]]:_(<8 x s16>) = G_TRUNC [[DEF8]](<8 x s32>)
    ; CHECK: [[INSERT6:%[0-9]+]]:_(<8 x s16>) = G_INSERT [[TRUNC4]], [[EXTRACT4]](<5 x s16>), 0
    ; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[INSERT6]](<8 x s16>)
    %0:_(<5 x s16>) = G_IMPLICIT_DEF
    %1:_(<5 x s16>) = G_IMPLICIT_DEF
    %2:_(<5 x s16>) = G_AND %0, %1
    %3:_(<8 x s16>) = G_IMPLICIT_DEF
    %4:_(<8 x s16>) = G_INSERT %3, %2, 0
    $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %4
...

---
name: test_and_v3s8
body: |
  bb.0:

    ; CHECK-LABEL: name: test_and_v3s8
    ; CHECK: [[DEF:%[0-9]+]]:_(<3 x s8>) = G_IMPLICIT_DEF
    ; CHECK: [[DEF1:%[0-9]+]]:_(<3 x s8>) = G_IMPLICIT_DEF
    ; CHECK: [[DEF2:%[0-9]+]]:_(<4 x s8>) = G_IMPLICIT_DEF
    ; CHECK: [[INSERT:%[0-9]+]]:_(<4 x s8>) = G_INSERT [[DEF2]], [[DEF]](<3 x s8>), 0
    ; CHECK: [[DEF3:%[0-9]+]]:_(<4 x s8>) = G_IMPLICIT_DEF
    ; CHECK: [[ANYEXT:%[0-9]+]]:_(<4 x s16>) = G_ANYEXT [[DEF3]](<4 x s8>)
    ; CHECK: [[INSERT1:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[ANYEXT]], [[DEF1]](<3 x s8>), 0
    ; CHECK: [[TRUNC:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[INSERT1]](<4 x s16>)
    ; CHECK: [[UV:%[0-9]+]]:_(s8), [[UV1:%[0-9]+]]:_(s8), [[UV2:%[0-9]+]]:_(s8), [[UV3:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[INSERT]](<4 x s8>)
    ; CHECK: [[UV4:%[0-9]+]]:_(s8), [[UV5:%[0-9]+]]:_(s8), [[UV6:%[0-9]+]]:_(s8), [[UV7:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[TRUNC]](<4 x s8>)
    ; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[UV]](s8)
    ; CHECK: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[UV4]](s8)
    ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[ANYEXT2]]
    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[AND]](s32)
    ; CHECK: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[UV1]](s8)
    ; CHECK: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[UV5]](s8)
    ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT3]], [[ANYEXT4]]
    ; CHECK: [[TRUNC2:%[0-9]+]]:_(s8) = G_TRUNC [[AND1]](s32)
    ; CHECK: [[ANYEXT5:%[0-9]+]]:_(s32) = G_ANYEXT [[UV2]](s8)
    ; CHECK: [[ANYEXT6:%[0-9]+]]:_(s32) = G_ANYEXT [[UV6]](s8)
    ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ANYEXT5]], [[ANYEXT6]]
    ; CHECK: [[TRUNC3:%[0-9]+]]:_(s8) = G_TRUNC [[AND2]](s32)
    ; CHECK: [[ANYEXT7:%[0-9]+]]:_(s32) = G_ANYEXT [[UV3]](s8)
    ; CHECK: [[ANYEXT8:%[0-9]+]]:_(s32) = G_ANYEXT [[UV7]](s8)
    ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ANYEXT7]], [[ANYEXT8]]
    ; CHECK: [[TRUNC4:%[0-9]+]]:_(s8) = G_TRUNC [[AND3]](s32)
    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s8>) = G_BUILD_VECTOR [[TRUNC1]](s8), [[TRUNC2]](s8), [[TRUNC3]](s8), [[TRUNC4]](s8)
    ; CHECK: [[EXTRACT:%[0-9]+]]:_(<3 x s8>) = G_EXTRACT [[BUILD_VECTOR]](<4 x s8>), 0
    ; CHECK: [[ANYEXT9:%[0-9]+]]:_(<3 x s32>) = G_ANYEXT [[EXTRACT]](<3 x s8>)
    ; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[ANYEXT9]](<3 x s32>)
    %0:_(<3 x s8>) = G_IMPLICIT_DEF
    %1:_(<3 x s8>) = G_IMPLICIT_DEF
    %2:_(<3 x s8>) = G_AND %0, %1
    %3:_(<3 x s32>) = G_ANYEXT %2
    $vgpr0_vgpr1_vgpr2 = COPY %3
...

---
name: test_and_v4s8
body: |
  bb.0:

    ; CHECK-LABEL: name: test_and_v4s8
    ; CHECK: [[DEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF
    ; CHECK: [[TRUNC:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[DEF]](<4 x s32>)
    ; CHECK: [[DEF1:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF
    ; CHECK: [[TRUNC1:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[DEF1]](<4 x s32>)
    ; CHECK: [[UV:%[0-9]+]]:_(s8), [[UV1:%[0-9]+]]:_(s8), [[UV2:%[0-9]+]]:_(s8), [[UV3:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[TRUNC]](<4 x s8>)
    ; CHECK: [[UV4:%[0-9]+]]:_(s8), [[UV5:%[0-9]+]]:_(s8), [[UV6:%[0-9]+]]:_(s8), [[UV7:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[TRUNC1]](<4 x s8>)
    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UV]](s8)
    ; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[UV4]](s8)
    ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[ANYEXT1]]
    ; CHECK: [[TRUNC2:%[0-9]+]]:_(s8) = G_TRUNC [[AND]](s32)
    ; CHECK: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[UV1]](s8)
    ; CHECK: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[UV5]](s8)
    ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT2]], [[ANYEXT3]]
    ; CHECK: [[TRUNC3:%[0-9]+]]:_(s8) = G_TRUNC [[AND1]](s32)
    ; CHECK: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[UV2]](s8)
    ; CHECK: [[ANYEXT5:%[0-9]+]]:_(s32) = G_ANYEXT [[UV6]](s8)
    ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ANYEXT4]], [[ANYEXT5]]
    ; CHECK: [[TRUNC4:%[0-9]+]]:_(s8) = G_TRUNC [[AND2]](s32)
    ; CHECK: [[ANYEXT6:%[0-9]+]]:_(s32) = G_ANYEXT [[UV3]](s8)
    ; CHECK: [[ANYEXT7:%[0-9]+]]:_(s32) = G_ANYEXT [[UV7]](s8)
    ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ANYEXT6]], [[ANYEXT7]]
    ; CHECK: [[TRUNC5:%[0-9]+]]:_(s8) = G_TRUNC [[AND3]](s32)
    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s8>) = G_BUILD_VECTOR [[TRUNC2]](s8), [[TRUNC3]](s8), [[TRUNC4]](s8), [[TRUNC5]](s8)
    ; CHECK: [[UV8:%[0-9]+]]:_(s8), [[UV9:%[0-9]+]]:_(s8), [[UV10:%[0-9]+]]:_(s8), [[UV11:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s8>)
    ; CHECK: [[ANYEXT8:%[0-9]+]]:_(s32) = G_ANYEXT [[UV8]](s8)
    ; CHECK: [[ANYEXT9:%[0-9]+]]:_(s32) = G_ANYEXT [[UV9]](s8)
    ; CHECK: [[ANYEXT10:%[0-9]+]]:_(s32) = G_ANYEXT [[UV10]](s8)
    ; CHECK: [[ANYEXT11:%[0-9]+]]:_(s32) = G_ANYEXT [[UV11]](s8)
    ; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[ANYEXT8]](s32), [[ANYEXT9]](s32), [[ANYEXT10]](s32), [[ANYEXT11]](s32)
    ; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR1]](<4 x s32>)
    %0:_(<4 x s8>) = G_IMPLICIT_DEF
    %1:_(<4 x s8>) = G_IMPLICIT_DEF
    %2:_(<4 x s8>) = G_AND %0, %1
    %3:_(<4 x s32>) = G_ANYEXT %2
    $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %3
...