maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
llvm-project/llvm/test/MC/ARM/mode-switch.s

18 lines
541 B
ArmAsm
Raw Normal View History

Add support for ARM / Thumb mode switching with .code 16 and .code 32. llvm-svn: 134760
2011-07-09 06:36:29 +08:00
@ Test ARM / Thumb mode switching with .code
@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s
- Eliminate MCCodeEmitter's dependency on TargetMachine. It now uses MCInstrInfo and MCSubtargetInfo. - Added methods to update subtarget features (used when targets automatically detect subtarget features or switch modes). - Teach X86Subtarget to update MCSubtargetInfo features bits since the MCSubtargetInfo layer can be shared with other modules. - These fixes .code 16 / .code 32 support since mode switch is updated in MCSubtargetInfo so MC code emitter can do the right thing. llvm-svn: 134884
2011-07-11 11:57:24 +08:00
@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unknown -show-encoding < %s | FileCheck %s
Add support for ARM / Thumb mode switching with .code 16 and .code 32. llvm-svn: 134760
2011-07-09 06:36:29 +08:00
.code 16
- Eliminate MCCodeEmitter's dependency on TargetMachine. It now uses MCInstrInfo and MCSubtargetInfo. - Added methods to update subtarget features (used when targets automatically detect subtarget features or switch modes). - Teach X86Subtarget to update MCSubtargetInfo features bits since the MCSubtargetInfo layer can be shared with other modules. - These fixes .code 16 / .code 32 support since mode switch is updated in MCSubtargetInfo so MC code emitter can do the right thing. llvm-svn: 134884
2011-07-11 11:57:24 +08:00
@ CHECK: add.w r0, r0, r1 @ encoding: [0x00,0xeb,0x01,0x00]
Add support for ARM / Thumb mode switching with .code 16 and .code 32. llvm-svn: 134760
2011-07-09 06:36:29 +08:00
add.w r0, r0, r1
.code 32
@ CHECK: add r0, r0, r1 @ encoding: [0x01,0x00,0x80,0xe0]
add r0, r0, r1
.code 16
@ CHECK: add r0, r0, r1 @ encoding: [0x40,0x18]
add r0, r0, r1