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llvm-project/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.h

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Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. llvm-svn: 150878
2012-02-18 20:03:15 +08:00
//===- ARMInstPrinter.h - Convert ARM MCInst to assembly syntax -*- C++ -*-===//
stub out a minimal ARMInstPrinter. llvm-svn: 84527
2009-10-20 03:56:26 +08:00
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This class prints an ARM MCInst to a .s file.
//
//===----------------------------------------------------------------------===//
Canonicalize header guards into a common format. Add header guards to files that were missing guards. Remove #endif comments as they don't seem common in LLVM (we can easily add them back if we decide they're useful) Changes made by clang-tidy with minor tweaks. llvm-svn: 215558
2014-08-14 00:26:38 +08:00
#ifndef LLVM_LIB_TARGET_ARM_INSTPRINTER_ARMINSTPRINTER_H
#define LLVM_LIB_TARGET_ARM_INSTPRINTER_ARMINSTPRINTER_H
stub out a minimal ARMInstPrinter. llvm-svn: 84527
2009-10-20 03:56:26 +08:00
#include "llvm/MC/MCInstPrinter.h"
Refactor instprinter and mcdisassembler to take a SubtargetInfo. Add -mattr= handling to llvm-mc. Reviewed by Owen Anderson. llvm-svn: 139237
2011-09-08 01:24:38 +08:00
#include "llvm/MC/MCSubtargetInfo.h"
stub out a minimal ARMInstPrinter. llvm-svn: 84527
2009-10-20 03:56:26 +08:00
namespace llvm {
We need to pass the TargetMachine object to the InstPrinter if we are printing the alias of an InstAlias instead of the thing being aliased. Because we need to know the features that are valid for an InstAlias. This is part of a work-in-progress. llvm-svn: 127986
2011-03-21 12:13:46 +08:00
class MCOperand;
trailing whitespace llvm-svn: 114212
2010-09-18 05:25:10 +08:00
stub out a minimal ARMInstPrinter. llvm-svn: 84527
2009-10-20 03:56:26 +08:00
class ARMInstPrinter : public MCInstPrinter {
public:
Make MCInstrInfo available to the MCInstPrinter. This will be used to remove getInstructionName and the static data it contains since the same tables are already in MCInstrInfo. llvm-svn: 153860
2012-04-02 14:09:36 +08:00
ARMInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
Remove unused MCSubtargetInfo argument from the ARM MCInstPrinter ctors. llvm-svn: 233609
2015-03-31 05:52:28 +08:00
const MCRegisterInfo &MRI);
stub out a minimal ARMInstPrinter. llvm-svn: 84527
2009-10-20 03:56:26 +08:00
[MCInstPrinter] Enable MCInstPrinter to change its behavior based on the per-function subtarget. Currently, code-gen passes the default or generic subtarget to the constructors of MCInstPrinter subclasses (see LLVMTargetMachine::addPassesToEmitFile), which enables some targets (AArch64, ARM, and X86) to change their instprinter's behavior based on the subtarget feature bits. Since the backend can now use different subtargets for each function, instprinter has to be changed to use the per-function subtarget rather than the default subtarget. This patch takes the first step towards enabling instprinter to change its behavior based on the per-function subtarget. It adds a bit "PassSubtarget" to AsmWriter which tells table-gen to pass a reference to MCSubtargetInfo to the various print methods table-gen auto-generates. I will follow up with changes to instprinters of AArch64, ARM, and X86. llvm-svn: 233411
2015-03-28 04:36:02 +08:00
void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot,
const MCSubtargetInfo &STI) override;
[C++11] Add 'override' keyword to virtual methods that override their base class. llvm-svn: 203433
2014-03-10 10:09:33 +08:00
void printRegName(raw_ostream &OS, unsigned RegNo) const override;
hook up getOpcodeName for ARM so that "llc -show-mc-inst" includes the opcode string in the inst dump, e.g.: vmov r2, r3, d17 @ encoding: [0x31,0x2b,0x53,0xec] @ <MCInst #989 VMOVRRD @ <MCOperand Reg:68> @ <MCOperand Reg:69> @ <MCOperand Reg:19> @ <MCOperand Imm:14> @ <MCOperand Reg:0>> The "VMOVRRD" is new. llvm-svn: 117609
2010-10-29 05:37:33 +08:00
stub out a minimal ARMInstPrinter. llvm-svn: 84527
2009-10-20 03:56:26 +08:00
// Autogenerated by tblgen.
[ARM] Enable changing instprinter's behavior based on the per-function subtarget. llvm-svn: 233451
2015-03-28 07:41:42 +08:00
void printInstruction(const MCInst *MI, const MCSubtargetInfo &STI,
raw_ostream &O);
stub out a minimal ARMInstPrinter. llvm-svn: 84527
2009-10-20 03:56:26 +08:00
static const char *getRegisterName(unsigned RegNo);
[ARM] Enable changing instprinter's behavior based on the per-function subtarget. llvm-svn: 233451
2015-03-28 07:41:42 +08:00
void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
raw_ostream &O);
void printSORegRegOperand(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI, raw_ostream &O);
void printSORegImmOperand(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI, raw_ostream &O);
void printAddrModeTBB(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI, raw_ostream &O);
void printAddrModeTBH(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI, raw_ostream &O);
void printAddrMode2Operand(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI, raw_ostream &O);
void printAM2PostIndexOp(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI, raw_ostream &O);
Apply again changes to support ARM memory asm parsing. I removed all LDR/STR changes and left them to a future patch. Passing all checks now. - Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and fix the encoding wherever is possible. - Add a new encoding bit to describe the index mode used and teach printAddrMode2Operand to check by the addressing mode which index mode to print. - Testcases llvm-svn: 128689
2011-04-01 07:26:08 +08:00
void printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned OpNum,
[ARM] Enable changing instprinter's behavior based on the per-function subtarget. llvm-svn: 233451
2015-03-28 07:41:42 +08:00
const MCSubtargetInfo &STI, raw_ostream &O);
change a ton of code to not implicitly use the "O" raw_ostream member of AsmPrinter. Instead, pass it in explicitly. llvm-svn: 100306
2010-04-04 12:47:45 +08:00
void printAddrMode2OffsetOperand(const MCInst *MI, unsigned OpNum,
[ARM] Enable changing instprinter's behavior based on the per-function subtarget. llvm-svn: 233451
2015-03-28 07:41:42 +08:00
const MCSubtargetInfo &STI, raw_ostream &O);
ARM: Correct printing of pre-indexed operands. According to the ARM reference manual, constant offsets are mandatory for pre-indexed addressing modes. The MC disassembler was not obeying this when the offset is 0. It was producing instructions like: str r0, [r1]!. Correct syntax is: str r0, [r1, #0]!. This change modifies the dumping of operands so that the offset is always printed, regardless of its value, when pre-indexed addressing mode is used. Patch by Mihail Popa <Mihail.Popa@arm.com> llvm-svn: 179398
2013-04-13 02:47:25 +08:00
template <bool AlwaysPrintImm0>
[ARM] Enable changing instprinter's behavior based on the per-function subtarget. llvm-svn: 233451
2015-03-28 07:41:42 +08:00
void printAddrMode3Operand(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI, raw_ostream &O);
change a ton of code to not implicitly use the "O" raw_ostream member of AsmPrinter. Instead, pass it in explicitly. llvm-svn: 100306
2010-04-04 12:47:45 +08:00
void printAddrMode3OffsetOperand(const MCInst *MI, unsigned OpNum,
[ARM] Enable changing instprinter's behavior based on the per-function subtarget. llvm-svn: 233451
2015-03-28 07:41:42 +08:00
const MCSubtargetInfo &STI, raw_ostream &O);
ARM: Correct printing of pre-indexed operands. According to the ARM reference manual, constant offsets are mandatory for pre-indexed addressing modes. The MC disassembler was not obeying this when the offset is 0. It was producing instructions like: str r0, [r1]!. Correct syntax is: str r0, [r1, #0]!. This change modifies the dumping of operands so that the offset is always printed, regardless of its value, when pre-indexed addressing mode is used. Patch by Mihail Popa <Mihail.Popa@arm.com> llvm-svn: 179398
2013-04-13 02:47:25 +08:00
void printAM3PreOrOffsetIndexOp(const MCInst *MI, unsigned Op, raw_ostream &O,
bool AlwaysPrintImm0);
ARM refactoring assembly parsing of memory address operands. Memory operand parsing is a bit haphazzard at the moment, in no small part due to the even more haphazzard representations of memory operands in the .td files. Start cleaning that all up, at least a bit. The addressing modes in the .td files will be being simplified to not be so monolithic, especially with regards to immediate vs. register offsets and post-indexed addressing. addrmode3 is on its way with this patch, for example. This patch is foundational to enable going back to smaller incremental patches for the individual memory referencing instructions themselves. It does just enough to get the basics in place and handle the "make check" regression tests we already have. Follow-up work will be fleshing out the details and adding more robust test cases for the individual instructions, starting with ARM mode and moving from there into Thumb and Thumb2. llvm-svn: 136845
2011-08-04 07:50:40 +08:00
void printPostIdxImm8Operand(const MCInst *MI, unsigned OpNum,
[ARM] Enable changing instprinter's behavior based on the per-function subtarget. llvm-svn: 233451
2015-03-28 07:41:42 +08:00
const MCSubtargetInfo &STI, raw_ostream &O);
void printPostIdxRegOperand(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI, raw_ostream &O);
LDCL_POST and STCL_POST need one's-complement offsets, rather than two's complement offsets. Add an appropriate immediate type for them. llvm-svn: 136896
2011-08-05 02:24:14 +08:00
void printPostIdxImm8s4Operand(const MCInst *MI, unsigned OpNum,
[ARM] Enable changing instprinter's behavior based on the per-function subtarget. llvm-svn: 233451
2015-03-28 07:41:42 +08:00
const MCSubtargetInfo &STI, raw_ostream &O);
- Implement asm parsing support for LDRSBT, LDRHT, LDRSHT and STRHT also fix the encoding of the later. - Add a new encoding bit to describe the index mode used in AM3. - Teach printAddrMode3Operand to check by the addressing mode which index mode to print. - Testcases. llvm-svn: 128832
2011-04-05 01:18:19 +08:00
[ARM] Enable changing instprinter's behavior based on the per-function subtarget. llvm-svn: 233451
2015-03-28 07:41:42 +08:00
void printLdStmModeOperand(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI, raw_ostream &O);
ARM: Correct printing of pre-indexed operands. According to the ARM reference manual, constant offsets are mandatory for pre-indexed addressing modes. The MC disassembler was not obeying this when the offset is 0. It was producing instructions like: str r0, [r1]!. Correct syntax is: str r0, [r1, #0]!. This change modifies the dumping of operands so that the offset is always printed, regardless of its value, when pre-indexed addressing mode is used. Patch by Mihail Popa <Mihail.Popa@arm.com> llvm-svn: 179398
2013-04-13 02:47:25 +08:00
template <bool AlwaysPrintImm0>
[ARM] Enable changing instprinter's behavior based on the per-function subtarget. llvm-svn: 233451
2015-03-28 07:41:42 +08:00
void printAddrMode5Operand(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI, raw_ostream &O);
void printAddrMode6Operand(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI, raw_ostream &O);
void printAddrMode7Operand(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI, raw_ostream &O);
change a ton of code to not implicitly use the "O" raw_ostream member of AsmPrinter. Instead, pass it in explicitly. llvm-svn: 100306
2010-04-04 12:47:45 +08:00
void printAddrMode6OffsetOperand(const MCInst *MI, unsigned OpNum,
[ARM] Enable changing instprinter's behavior based on the per-function subtarget. llvm-svn: 233451
2015-03-28 07:41:42 +08:00
const MCSubtargetInfo &STI, raw_ostream &O);
Factored out the disassembly printing of CPS option, MSR mask, and Negative Zero operands into their own PrintMethod, in order not to pollute the printOperand() impl with disassembly only Imm modifiers. llvm-svn: 98172
2010-03-11 02:59:38 +08:00
change a ton of code to not implicitly use the "O" raw_ostream member of AsmPrinter. Instead, pass it in explicitly. llvm-svn: 100306
2010-04-04 12:47:45 +08:00
void printBitfieldInvMaskImmOperand(const MCInst *MI, unsigned OpNum,
[ARM] Enable changing instprinter's behavior based on the per-function subtarget. llvm-svn: 233451
2015-03-28 07:41:42 +08:00
const MCSubtargetInfo &STI,
change a ton of code to not implicitly use the "O" raw_ostream member of AsmPrinter. Instead, pass it in explicitly. llvm-svn: 100306
2010-04-04 12:47:45 +08:00
raw_ostream &O);
[ARM] Enable changing instprinter's behavior based on the per-function subtarget. llvm-svn: 233451
2015-03-28 07:41:42 +08:00
void printMemBOption(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI, raw_ostream &O);
void printInstSyncBOption(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI, raw_ostream &O);
void printShiftImmOperand(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI, raw_ostream &O);
void printPKHLSLShiftImm(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI, raw_ostream &O);
void printPKHASRShiftImm(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI, raw_ostream &O);
More consistent thumb1 asm printing. llvm-svn: 89328
2009-11-19 14:57:41 +08:00
This corrects the implementation of Thumb ADR instruction. There are three issues: 1. it should accept only 4-byte aligned addresses 2. the maximum offset should be 1020 3. it should be encoded with the offset scaled by two bits llvm-svn: 185528
2013-07-03 17:21:44 +08:00
template <unsigned scale>
[ARM] Enable changing instprinter's behavior based on the per-function subtarget. llvm-svn: 233451
2015-03-28 07:41:42 +08:00
void printAdrLabelOperand(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI, raw_ostream &O);
void printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI, raw_ostream &O);
void printThumbSRImm(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI, raw_ostream &O);
void printThumbITMask(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI, raw_ostream &O);
change a ton of code to not implicitly use the "O" raw_ostream member of AsmPrinter. Instead, pass it in explicitly. llvm-svn: 100306
2010-04-04 12:47:45 +08:00
void printThumbAddrModeRROperand(const MCInst *MI, unsigned OpNum,
[ARM] Enable changing instprinter's behavior based on the per-function subtarget. llvm-svn: 233451
2015-03-28 07:41:42 +08:00
const MCSubtargetInfo &STI, raw_ostream &O);
The tLDR et al instructions were emitting either a reg/reg or reg/imm instruction based on the t_addrmode_s# mode and what it returned. There is some obvious badness to this. In particular, it's hard to do MC-encoding when the instruction may change out from underneath you after the t_addrmode_s# variable is finally resolved. The solution is to revert a long-ago change that merged the reg/reg and reg/imm versions. There is the addition of several new addressing modes. They no longer have extraneous operands associated with them. I.e., if it's reg/reg we don't have to have a dummy zero immediate tacked on to the SDNode. There are some obvious cleanups here, which will happen shortly. llvm-svn: 121747
2010-12-14 11:36:38 +08:00
void printThumbAddrModeImm5SOperand(const MCInst *MI, unsigned OpNum,
[ARM] Enable changing instprinter's behavior based on the per-function subtarget. llvm-svn: 233451
2015-03-28 07:41:42 +08:00
const MCSubtargetInfo &STI,
The tLDR et al instructions were emitting either a reg/reg or reg/imm instruction based on the t_addrmode_s# mode and what it returned. There is some obvious badness to this. In particular, it's hard to do MC-encoding when the instruction may change out from underneath you after the t_addrmode_s# variable is finally resolved. The solution is to revert a long-ago change that merged the reg/reg and reg/imm versions. There is the addition of several new addressing modes. They no longer have extraneous operands associated with them. I.e., if it's reg/reg we don't have to have a dummy zero immediate tacked on to the SDNode. There are some obvious cleanups here, which will happen shortly. llvm-svn: 121747
2010-12-14 11:36:38 +08:00
raw_ostream &O, unsigned Scale);
void printThumbAddrModeImm5S1Operand(const MCInst *MI, unsigned OpNum,
[ARM] Enable changing instprinter's behavior based on the per-function subtarget. llvm-svn: 233451
2015-03-28 07:41:42 +08:00
const MCSubtargetInfo &STI,
The tLDR et al instructions were emitting either a reg/reg or reg/imm instruction based on the t_addrmode_s# mode and what it returned. There is some obvious badness to this. In particular, it's hard to do MC-encoding when the instruction may change out from underneath you after the t_addrmode_s# variable is finally resolved. The solution is to revert a long-ago change that merged the reg/reg and reg/imm versions. There is the addition of several new addressing modes. They no longer have extraneous operands associated with them. I.e., if it's reg/reg we don't have to have a dummy zero immediate tacked on to the SDNode. There are some obvious cleanups here, which will happen shortly. llvm-svn: 121747
2010-12-14 11:36:38 +08:00
raw_ostream &O);
void printThumbAddrModeImm5S2Operand(const MCInst *MI, unsigned OpNum,
[ARM] Enable changing instprinter's behavior based on the per-function subtarget. llvm-svn: 233451
2015-03-28 07:41:42 +08:00
const MCSubtargetInfo &STI,
The tLDR et al instructions were emitting either a reg/reg or reg/imm instruction based on the t_addrmode_s# mode and what it returned. There is some obvious badness to this. In particular, it's hard to do MC-encoding when the instruction may change out from underneath you after the t_addrmode_s# variable is finally resolved. The solution is to revert a long-ago change that merged the reg/reg and reg/imm versions. There is the addition of several new addressing modes. They no longer have extraneous operands associated with them. I.e., if it's reg/reg we don't have to have a dummy zero immediate tacked on to the SDNode. There are some obvious cleanups here, which will happen shortly. llvm-svn: 121747
2010-12-14 11:36:38 +08:00
raw_ostream &O);
void printThumbAddrModeImm5S4Operand(const MCInst *MI, unsigned OpNum,
[ARM] Enable changing instprinter's behavior based on the per-function subtarget. llvm-svn: 233451
2015-03-28 07:41:42 +08:00
const MCSubtargetInfo &STI,
The tLDR et al instructions were emitting either a reg/reg or reg/imm instruction based on the t_addrmode_s# mode and what it returned. There is some obvious badness to this. In particular, it's hard to do MC-encoding when the instruction may change out from underneath you after the t_addrmode_s# variable is finally resolved. The solution is to revert a long-ago change that merged the reg/reg and reg/imm versions. There is the addition of several new addressing modes. They no longer have extraneous operands associated with them. I.e., if it's reg/reg we don't have to have a dummy zero immediate tacked on to the SDNode. There are some obvious cleanups here, which will happen shortly. llvm-svn: 121747
2010-12-14 11:36:38 +08:00
raw_ostream &O);
change a ton of code to not implicitly use the "O" raw_ostream member of AsmPrinter. Instead, pass it in explicitly. llvm-svn: 100306
2010-04-04 12:47:45 +08:00
void printThumbAddrModeSPOperand(const MCInst *MI, unsigned OpNum,
[ARM] Enable changing instprinter's behavior based on the per-function subtarget. llvm-svn: 233451
2015-03-28 07:41:42 +08:00
const MCSubtargetInfo &STI, raw_ostream &O);
trailing whitespace llvm-svn: 114212
2010-09-18 05:25:10 +08:00
[ARM] Enable changing instprinter's behavior based on the per-function subtarget. llvm-svn: 233451
2015-03-28 07:41:42 +08:00
void printT2SOOperand(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI, raw_ostream &O);
clang-format ARMInstPrinter.{h,cpp} before I make changes to these files. llvm-svn: 233448
2015-03-28 07:24:22 +08:00
template <bool AlwaysPrintImm0>
imm12 operands aren't Thumb2 only, so rename the printer helper function. llvm-svn: 117291
2010-10-26 04:00:01 +08:00
void printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum,
[ARM] Enable changing instprinter's behavior based on the per-function subtarget. llvm-svn: 233451
2015-03-28 07:41:42 +08:00
const MCSubtargetInfo &STI, raw_ostream &O);
clang-format ARMInstPrinter.{h,cpp} before I make changes to these files. llvm-svn: 233448
2015-03-28 07:24:22 +08:00
template <bool AlwaysPrintImm0>
change a ton of code to not implicitly use the "O" raw_ostream member of AsmPrinter. Instead, pass it in explicitly. llvm-svn: 100306
2010-04-04 12:47:45 +08:00
void printT2AddrModeImm8Operand(const MCInst *MI, unsigned OpNum,
[ARM] Enable changing instprinter's behavior based on the per-function subtarget. llvm-svn: 233451
2015-03-28 07:41:42 +08:00
const MCSubtargetInfo &STI, raw_ostream &O);
clang-format ARMInstPrinter.{h,cpp} before I make changes to these files. llvm-svn: 233448
2015-03-28 07:24:22 +08:00
template <bool AlwaysPrintImm0>
change a ton of code to not implicitly use the "O" raw_ostream member of AsmPrinter. Instead, pass it in explicitly. llvm-svn: 100306
2010-04-04 12:47:45 +08:00
void printT2AddrModeImm8s4Operand(const MCInst *MI, unsigned OpNum,
[ARM] Enable changing instprinter's behavior based on the per-function subtarget. llvm-svn: 233451
2015-03-28 07:41:42 +08:00
const MCSubtargetInfo &STI, raw_ostream &O);
Thumb2 assembly parsing and encoding for LDREX/LDREXB/LDREXD/LDREXH. llvm-svn: 139381
2011-09-10 02:37:27 +08:00
void printT2AddrModeImm0_1020s4Operand(const MCInst *MI, unsigned OpNum,
[ARM] Enable changing instprinter's behavior based on the per-function subtarget. llvm-svn: 233451
2015-03-28 07:41:42 +08:00
const MCSubtargetInfo &STI,
clang-format ARMInstPrinter.{h,cpp} before I make changes to these files. llvm-svn: 233448
2015-03-28 07:24:22 +08:00
raw_ostream &O);
change a ton of code to not implicitly use the "O" raw_ostream member of AsmPrinter. Instead, pass it in explicitly. llvm-svn: 100306
2010-04-04 12:47:45 +08:00
void printT2AddrModeImm8OffsetOperand(const MCInst *MI, unsigned OpNum,
[ARM] Enable changing instprinter's behavior based on the per-function subtarget. llvm-svn: 233451
2015-03-28 07:41:42 +08:00
const MCSubtargetInfo &STI,
change a ton of code to not implicitly use the "O" raw_ostream member of AsmPrinter. Instead, pass it in explicitly. llvm-svn: 100306
2010-04-04 12:47:45 +08:00
raw_ostream &O);
void printT2AddrModeImm8s4OffsetOperand(const MCInst *MI, unsigned OpNum,
[ARM] Enable changing instprinter's behavior based on the per-function subtarget. llvm-svn: 233451
2015-03-28 07:41:42 +08:00
const MCSubtargetInfo &STI,
change a ton of code to not implicitly use the "O" raw_ostream member of AsmPrinter. Instead, pass it in explicitly. llvm-svn: 100306
2010-04-04 12:47:45 +08:00
raw_ostream &O);
void printT2AddrModeSoRegOperand(const MCInst *MI, unsigned OpNum,
[ARM] Enable changing instprinter's behavior based on the per-function subtarget. llvm-svn: 233451
2015-03-28 07:41:42 +08:00
const MCSubtargetInfo &STI, raw_ostream &O);
void printSetendOperand(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI, raw_ostream &O);
void printCPSIMod(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI, raw_ostream &O);
void printCPSIFlag(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI, raw_ostream &O);
void printMSRMaskOperand(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI, raw_ostream &O);
void printBankedRegOperand(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI, raw_ostream &O);
void printPredicateOperand(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI, raw_ostream &O);
change a ton of code to not implicitly use the "O" raw_ostream member of AsmPrinter. Instead, pass it in explicitly. llvm-svn: 100306
2010-04-04 12:47:45 +08:00
void printMandatoryPredicateOperand(const MCInst *MI, unsigned OpNum,
[ARM] Enable changing instprinter's behavior based on the per-function subtarget. llvm-svn: 233451
2015-03-28 07:41:42 +08:00
const MCSubtargetInfo &STI,
change a ton of code to not implicitly use the "O" raw_ostream member of AsmPrinter. Instead, pass it in explicitly. llvm-svn: 100306
2010-04-04 12:47:45 +08:00
raw_ostream &O);
void printSBitModifierOperand(const MCInst *MI, unsigned OpNum,
[ARM] Enable changing instprinter's behavior based on the per-function subtarget. llvm-svn: 233451
2015-03-28 07:41:42 +08:00
const MCSubtargetInfo &STI, raw_ostream &O);
void printRegisterList(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI, raw_ostream &O);
void printNoHashImmediate(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI, raw_ostream &O);
void printPImmediate(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI, raw_ostream &O);
void printCImmediate(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI, raw_ostream &O);
void printCoprocOptionImm(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI, raw_ostream &O);
void printFPImmOperand(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI, raw_ostream &O);
void printNEONModImmOperand(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI, raw_ostream &O);
void printImmPlusOneOperand(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI, raw_ostream &O);
void printRotImmOperand(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI, raw_ostream &O);
void printModImmOperand(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI, raw_ostream &O);
void printGPRPairOperand(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI, raw_ostream &O);
void printPCLabel(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI, raw_ostream &O);
ARM: Better disassembly for pc-relative LDR. When the operand is a plain immediate rather than a label, print it as [pc, #imm] like we do for the Thumb2 wide encoding variant. rdar://12154503 llvm-svn: 166991
2012-10-30 09:04:51 +08:00
void printThumbLdrLabelOperand(const MCInst *MI, unsigned OpNum,
[ARM] Enable changing instprinter's behavior based on the per-function subtarget. llvm-svn: 233451
2015-03-28 07:41:42 +08:00
const MCSubtargetInfo &STI, raw_ostream &O);
void printFBits16(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI, raw_ostream &O);
void printFBits32(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI, raw_ostream &O);
void printVectorIndex(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI, raw_ostream &O);
void printVectorListOne(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI, raw_ostream &O);
void printVectorListTwo(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI, raw_ostream &O);
ARM refactor more NEON VLD/VST instructions to use composite physregs Register pair VLD1/VLD2 all-lanes instructions. Kill off more of the pseudos as a result. llvm-svn: 152150
2012-03-07 06:01:44 +08:00
void printVectorListTwoSpaced(const MCInst *MI, unsigned OpNum,
[ARM] Enable changing instprinter's behavior based on the per-function subtarget. llvm-svn: 233451
2015-03-28 07:41:42 +08:00
const MCSubtargetInfo &STI, raw_ostream &O);
void printVectorListThree(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI, raw_ostream &O);
void printVectorListFour(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI, raw_ostream &O);
ARM parsing aliases for VLD1 single register all lanes. llvm-svn: 145464
2011-11-30 09:09:44 +08:00
void printVectorListOneAllLanes(const MCInst *MI, unsigned OpNum,
[ARM] Enable changing instprinter's behavior based on the per-function subtarget. llvm-svn: 233451
2015-03-28 07:41:42 +08:00
const MCSubtargetInfo &STI, raw_ostream &O);
ARM parsing for VLD1 two register all lanes, no writeback. llvm-svn: 145504
2011-12-01 02:21:25 +08:00
void printVectorListTwoAllLanes(const MCInst *MI, unsigned OpNum,
[ARM] Enable changing instprinter's behavior based on the per-function subtarget. llvm-svn: 233451
2015-03-28 07:41:42 +08:00
const MCSubtargetInfo &STI, raw_ostream &O);
NEON VLD3(all lanes) assembly parsing and encoding. llvm-svn: 148882
2012-01-25 07:47:04 +08:00
void printVectorListThreeAllLanes(const MCInst *MI, unsigned OpNum,
[ARM] Enable changing instprinter's behavior based on the per-function subtarget. llvm-svn: 233451
2015-03-28 07:41:42 +08:00
const MCSubtargetInfo &STI, raw_ostream &O);
NEON VLD4(all lanes) assembly parsing and encoding. llvm-svn: 148884
2012-01-25 08:01:08 +08:00
void printVectorListFourAllLanes(const MCInst *MI, unsigned OpNum,
[ARM] Enable changing instprinter's behavior based on the per-function subtarget. llvm-svn: 233451
2015-03-28 07:41:42 +08:00
const MCSubtargetInfo &STI, raw_ostream &O);
ARM NEON VLD2 assembly parsing for structure to all lanes, non-writeback. llvm-svn: 147025
2011-12-21 08:38:54 +08:00
void printVectorListTwoSpacedAllLanes(const MCInst *MI, unsigned OpNum,
[ARM] Enable changing instprinter's behavior based on the per-function subtarget. llvm-svn: 233451
2015-03-28 07:41:42 +08:00
const MCSubtargetInfo &STI,
ARM NEON VLD2 assembly parsing for structure to all lanes, non-writeback. llvm-svn: 147025
2011-12-21 08:38:54 +08:00
raw_ostream &O);
NEON VLD3(all lanes) assembly parsing and encoding. llvm-svn: 148882
2012-01-25 07:47:04 +08:00
void printVectorListThreeSpacedAllLanes(const MCInst *MI, unsigned OpNum,
[ARM] Enable changing instprinter's behavior based on the per-function subtarget. llvm-svn: 233451
2015-03-28 07:41:42 +08:00
const MCSubtargetInfo &STI,
NEON VLD3(all lanes) assembly parsing and encoding. llvm-svn: 148882
2012-01-25 07:47:04 +08:00
raw_ostream &O);
NEON VLD4(all lanes) assembly parsing and encoding. llvm-svn: 148884
2012-01-25 08:01:08 +08:00
void printVectorListFourSpacedAllLanes(const MCInst *MI, unsigned OpNum,
[ARM] Enable changing instprinter's behavior based on the per-function subtarget. llvm-svn: 233451
2015-03-28 07:41:42 +08:00
const MCSubtargetInfo &STI,
NEON VLD4(all lanes) assembly parsing and encoding. llvm-svn: 148884
2012-01-25 08:01:08 +08:00
raw_ostream &O);
NEON VLD3(multiple 3-element structures) assembly parsing. llvm-svn: 148745
2012-01-24 07:20:46 +08:00
void printVectorListThreeSpaced(const MCInst *MI, unsigned OpNum,
[ARM] Enable changing instprinter's behavior based on the per-function subtarget. llvm-svn: 233451
2015-03-28 07:41:42 +08:00
const MCSubtargetInfo &STI, raw_ostream &O);
NEON VLD4(multiple 4 element structures) assembly parsing. llvm-svn: 148762
2012-01-24 08:43:17 +08:00
void printVectorListFourSpaced(const MCInst *MI, unsigned OpNum,
[ARM] Enable changing instprinter's behavior based on the per-function subtarget. llvm-svn: 233451
2015-03-28 07:41:42 +08:00
const MCSubtargetInfo &STI, raw_ostream &O);
stub out a minimal ARMInstPrinter. llvm-svn: 84527
2009-10-20 03:56:26 +08:00
};
trailing whitespace llvm-svn: 114212
2010-09-18 05:25:10 +08:00
stub out a powerpc MCInstPrinter implementation. llvm-svn: 119059
2010-11-15 03:40:38 +08:00
} // end namespace llvm
stub out a minimal ARMInstPrinter. llvm-svn: 84527
2009-10-20 03:56:26 +08:00
#endif