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llvm-project/llvm/test/MC/AMDGPU/sopc.s

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AMDGPU: Use i64 scalar compare instructions VI added eq/ne for i64, so use them. llvm-svn: 281800
2016-09-17 10:02:19 +08:00
// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s | FileCheck -check-prefix=GCN -check-prefix=SICI %s
// RUN: llvm-mc -arch=amdgcn -mcpu=fiji -show-encoding %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s 2>&1 | FileCheck -check-prefix=NOSICI %s
R600/SI: Initial support for assembler and inline assembly This is currently considered experimental, but most of the more commonly used instructions should work. So far only SI has been extensively tested, CI and VI probably work too, but may be buggy. The current set of tests cases do not give complete coverage, but I think it is sufficient for an experimental assembler. See the documentation in R600Usage for more information. llvm-svn: 234381
2015-04-08 09:09:26 +08:00
//===----------------------------------------------------------------------===//
[AMDGPU] Assembler: SOP* instruction fixes s_bitset0_b64, s_bitset1_b64 has 32-bit src0, not 64-bit. s_rfe_b64 has just one destination operand and no source. Uncomment S_BITCMP* and S_SETVSKIP, adjust SOPC_* classes for that. Add s_memrealtime test and change comments in smem.s to follow common style. Change test for s_memtime to use non-zero register to make it really test encoding. Add tests for s_buffer_load*. Add tests for SOPC instructions (same for SI and VI) Differential Revision: http://reviews.llvm.org/D18040 llvm-svn: 263420
2016-03-14 19:17:19 +08:00
// SOPC Instructions
R600/SI: Initial support for assembler and inline assembly This is currently considered experimental, but most of the more commonly used instructions should work. So far only SI has been extensively tested, CI and VI probably work too, but may be buggy. The current set of tests cases do not give complete coverage, but I think it is sufficient for an experimental assembler. See the documentation in R600Usage for more information. llvm-svn: 234381
2015-04-08 09:09:26 +08:00
//===----------------------------------------------------------------------===//
s_cmp_eq_i32 s1, s2
[AMDGPU] Assembler: Update SOP* tests Add VI encodings. Reformat sopp.s to match style of other files. Differential Revision: http://reviews.llvm.org/D18084 llvm-svn: 263540
2016-03-15 15:44:57 +08:00
// GCN: s_cmp_eq_i32 s1, s2 ; encoding: [0x01,0x02,0x00,0xbf]
[AMDGPU] Assembler: SOP* instruction fixes s_bitset0_b64, s_bitset1_b64 has 32-bit src0, not 64-bit. s_rfe_b64 has just one destination operand and no source. Uncomment S_BITCMP* and S_SETVSKIP, adjust SOPC_* classes for that. Add s_memrealtime test and change comments in smem.s to follow common style. Change test for s_memtime to use non-zero register to make it really test encoding. Add tests for s_buffer_load*. Add tests for SOPC instructions (same for SI and VI) Differential Revision: http://reviews.llvm.org/D18040 llvm-svn: 263420
2016-03-14 19:17:19 +08:00
s_cmp_lg_i32 s1, s2
[AMDGPU] Assembler: Update SOP* tests Add VI encodings. Reformat sopp.s to match style of other files. Differential Revision: http://reviews.llvm.org/D18084 llvm-svn: 263540
2016-03-15 15:44:57 +08:00
// GCN: s_cmp_lg_i32 s1, s2 ; encoding: [0x01,0x02,0x01,0xbf]
[AMDGPU] Assembler: SOP* instruction fixes s_bitset0_b64, s_bitset1_b64 has 32-bit src0, not 64-bit. s_rfe_b64 has just one destination operand and no source. Uncomment S_BITCMP* and S_SETVSKIP, adjust SOPC_* classes for that. Add s_memrealtime test and change comments in smem.s to follow common style. Change test for s_memtime to use non-zero register to make it really test encoding. Add tests for s_buffer_load*. Add tests for SOPC instructions (same for SI and VI) Differential Revision: http://reviews.llvm.org/D18040 llvm-svn: 263420
2016-03-14 19:17:19 +08:00
s_cmp_gt_i32 s1, s2
[AMDGPU] Assembler: Update SOP* tests Add VI encodings. Reformat sopp.s to match style of other files. Differential Revision: http://reviews.llvm.org/D18084 llvm-svn: 263540
2016-03-15 15:44:57 +08:00
// GCN: s_cmp_gt_i32 s1, s2 ; encoding: [0x01,0x02,0x02,0xbf]
[AMDGPU] Assembler: SOP* instruction fixes s_bitset0_b64, s_bitset1_b64 has 32-bit src0, not 64-bit. s_rfe_b64 has just one destination operand and no source. Uncomment S_BITCMP* and S_SETVSKIP, adjust SOPC_* classes for that. Add s_memrealtime test and change comments in smem.s to follow common style. Change test for s_memtime to use non-zero register to make it really test encoding. Add tests for s_buffer_load*. Add tests for SOPC instructions (same for SI and VI) Differential Revision: http://reviews.llvm.org/D18040 llvm-svn: 263420
2016-03-14 19:17:19 +08:00
s_cmp_ge_i32 s1, s2
[AMDGPU] Assembler: Update SOP* tests Add VI encodings. Reformat sopp.s to match style of other files. Differential Revision: http://reviews.llvm.org/D18084 llvm-svn: 263540
2016-03-15 15:44:57 +08:00
// GCN: s_cmp_ge_i32 s1, s2 ; encoding: [0x01,0x02,0x03,0xbf]
[AMDGPU] Assembler: SOP* instruction fixes s_bitset0_b64, s_bitset1_b64 has 32-bit src0, not 64-bit. s_rfe_b64 has just one destination operand and no source. Uncomment S_BITCMP* and S_SETVSKIP, adjust SOPC_* classes for that. Add s_memrealtime test and change comments in smem.s to follow common style. Change test for s_memtime to use non-zero register to make it really test encoding. Add tests for s_buffer_load*. Add tests for SOPC instructions (same for SI and VI) Differential Revision: http://reviews.llvm.org/D18040 llvm-svn: 263420
2016-03-14 19:17:19 +08:00
s_cmp_lt_i32 s1, s2
[AMDGPU] Assembler: Update SOP* tests Add VI encodings. Reformat sopp.s to match style of other files. Differential Revision: http://reviews.llvm.org/D18084 llvm-svn: 263540
2016-03-15 15:44:57 +08:00
// GCN: s_cmp_lt_i32 s1, s2 ; encoding: [0x01,0x02,0x04,0xbf]
[AMDGPU] Assembler: SOP* instruction fixes s_bitset0_b64, s_bitset1_b64 has 32-bit src0, not 64-bit. s_rfe_b64 has just one destination operand and no source. Uncomment S_BITCMP* and S_SETVSKIP, adjust SOPC_* classes for that. Add s_memrealtime test and change comments in smem.s to follow common style. Change test for s_memtime to use non-zero register to make it really test encoding. Add tests for s_buffer_load*. Add tests for SOPC instructions (same for SI and VI) Differential Revision: http://reviews.llvm.org/D18040 llvm-svn: 263420
2016-03-14 19:17:19 +08:00
s_cmp_le_i32 s1, s2
[AMDGPU] Assembler: Update SOP* tests Add VI encodings. Reformat sopp.s to match style of other files. Differential Revision: http://reviews.llvm.org/D18084 llvm-svn: 263540
2016-03-15 15:44:57 +08:00
// GCN: s_cmp_le_i32 s1, s2 ; encoding: [0x01,0x02,0x05,0xbf]
[AMDGPU] Assembler: SOP* instruction fixes s_bitset0_b64, s_bitset1_b64 has 32-bit src0, not 64-bit. s_rfe_b64 has just one destination operand and no source. Uncomment S_BITCMP* and S_SETVSKIP, adjust SOPC_* classes for that. Add s_memrealtime test and change comments in smem.s to follow common style. Change test for s_memtime to use non-zero register to make it really test encoding. Add tests for s_buffer_load*. Add tests for SOPC instructions (same for SI and VI) Differential Revision: http://reviews.llvm.org/D18040 llvm-svn: 263420
2016-03-14 19:17:19 +08:00
s_cmp_eq_u32 s1, s2
[AMDGPU] Assembler: Update SOP* tests Add VI encodings. Reformat sopp.s to match style of other files. Differential Revision: http://reviews.llvm.org/D18084 llvm-svn: 263540
2016-03-15 15:44:57 +08:00
// GCN: s_cmp_eq_u32 s1, s2 ; encoding: [0x01,0x02,0x06,0xbf]
[AMDGPU] Assembler: SOP* instruction fixes s_bitset0_b64, s_bitset1_b64 has 32-bit src0, not 64-bit. s_rfe_b64 has just one destination operand and no source. Uncomment S_BITCMP* and S_SETVSKIP, adjust SOPC_* classes for that. Add s_memrealtime test and change comments in smem.s to follow common style. Change test for s_memtime to use non-zero register to make it really test encoding. Add tests for s_buffer_load*. Add tests for SOPC instructions (same for SI and VI) Differential Revision: http://reviews.llvm.org/D18040 llvm-svn: 263420
2016-03-14 19:17:19 +08:00
s_cmp_lg_u32 s1, s2
[AMDGPU] Assembler: Update SOP* tests Add VI encodings. Reformat sopp.s to match style of other files. Differential Revision: http://reviews.llvm.org/D18084 llvm-svn: 263540
2016-03-15 15:44:57 +08:00
// GCN: s_cmp_lg_u32 s1, s2 ; encoding: [0x01,0x02,0x07,0xbf]
[AMDGPU] Assembler: SOP* instruction fixes s_bitset0_b64, s_bitset1_b64 has 32-bit src0, not 64-bit. s_rfe_b64 has just one destination operand and no source. Uncomment S_BITCMP* and S_SETVSKIP, adjust SOPC_* classes for that. Add s_memrealtime test and change comments in smem.s to follow common style. Change test for s_memtime to use non-zero register to make it really test encoding. Add tests for s_buffer_load*. Add tests for SOPC instructions (same for SI and VI) Differential Revision: http://reviews.llvm.org/D18040 llvm-svn: 263420
2016-03-14 19:17:19 +08:00
s_cmp_gt_u32 s1, s2
[AMDGPU] Assembler: Update SOP* tests Add VI encodings. Reformat sopp.s to match style of other files. Differential Revision: http://reviews.llvm.org/D18084 llvm-svn: 263540
2016-03-15 15:44:57 +08:00
// GCN: s_cmp_gt_u32 s1, s2 ; encoding: [0x01,0x02,0x08,0xbf]
[AMDGPU] Assembler: SOP* instruction fixes s_bitset0_b64, s_bitset1_b64 has 32-bit src0, not 64-bit. s_rfe_b64 has just one destination operand and no source. Uncomment S_BITCMP* and S_SETVSKIP, adjust SOPC_* classes for that. Add s_memrealtime test and change comments in smem.s to follow common style. Change test for s_memtime to use non-zero register to make it really test encoding. Add tests for s_buffer_load*. Add tests for SOPC instructions (same for SI and VI) Differential Revision: http://reviews.llvm.org/D18040 llvm-svn: 263420
2016-03-14 19:17:19 +08:00
s_cmp_ge_u32 s1, s2
[AMDGPU] Assembler: Update SOP* tests Add VI encodings. Reformat sopp.s to match style of other files. Differential Revision: http://reviews.llvm.org/D18084 llvm-svn: 263540
2016-03-15 15:44:57 +08:00
// GCN: s_cmp_ge_u32 s1, s2 ; encoding: [0x01,0x02,0x09,0xbf]
[AMDGPU] Assembler: SOP* instruction fixes s_bitset0_b64, s_bitset1_b64 has 32-bit src0, not 64-bit. s_rfe_b64 has just one destination operand and no source. Uncomment S_BITCMP* and S_SETVSKIP, adjust SOPC_* classes for that. Add s_memrealtime test and change comments in smem.s to follow common style. Change test for s_memtime to use non-zero register to make it really test encoding. Add tests for s_buffer_load*. Add tests for SOPC instructions (same for SI and VI) Differential Revision: http://reviews.llvm.org/D18040 llvm-svn: 263420
2016-03-14 19:17:19 +08:00
s_cmp_lt_u32 s1, s2
[AMDGPU] Assembler: Update SOP* tests Add VI encodings. Reformat sopp.s to match style of other files. Differential Revision: http://reviews.llvm.org/D18084 llvm-svn: 263540
2016-03-15 15:44:57 +08:00
// GCN: s_cmp_lt_u32 s1, s2 ; encoding: [0x01,0x02,0x0a,0xbf]
[AMDGPU] Assembler: SOP* instruction fixes s_bitset0_b64, s_bitset1_b64 has 32-bit src0, not 64-bit. s_rfe_b64 has just one destination operand and no source. Uncomment S_BITCMP* and S_SETVSKIP, adjust SOPC_* classes for that. Add s_memrealtime test and change comments in smem.s to follow common style. Change test for s_memtime to use non-zero register to make it really test encoding. Add tests for s_buffer_load*. Add tests for SOPC instructions (same for SI and VI) Differential Revision: http://reviews.llvm.org/D18040 llvm-svn: 263420
2016-03-14 19:17:19 +08:00
s_cmp_le_u32 s1, s2
[AMDGPU] Assembler: Update SOP* tests Add VI encodings. Reformat sopp.s to match style of other files. Differential Revision: http://reviews.llvm.org/D18084 llvm-svn: 263540
2016-03-15 15:44:57 +08:00
// GCN: s_cmp_le_u32 s1, s2 ; encoding: [0x01,0x02,0x0b,0xbf]
[AMDGPU] Assembler: SOP* instruction fixes s_bitset0_b64, s_bitset1_b64 has 32-bit src0, not 64-bit. s_rfe_b64 has just one destination operand and no source. Uncomment S_BITCMP* and S_SETVSKIP, adjust SOPC_* classes for that. Add s_memrealtime test and change comments in smem.s to follow common style. Change test for s_memtime to use non-zero register to make it really test encoding. Add tests for s_buffer_load*. Add tests for SOPC instructions (same for SI and VI) Differential Revision: http://reviews.llvm.org/D18040 llvm-svn: 263420
2016-03-14 19:17:19 +08:00
s_bitcmp0_b32 s1, s2
[AMDGPU] Assembler: Update SOP* tests Add VI encodings. Reformat sopp.s to match style of other files. Differential Revision: http://reviews.llvm.org/D18084 llvm-svn: 263540
2016-03-15 15:44:57 +08:00
// GCN: s_bitcmp0_b32 s1, s2 ; encoding: [0x01,0x02,0x0c,0xbf]
[AMDGPU] Assembler: SOP* instruction fixes s_bitset0_b64, s_bitset1_b64 has 32-bit src0, not 64-bit. s_rfe_b64 has just one destination operand and no source. Uncomment S_BITCMP* and S_SETVSKIP, adjust SOPC_* classes for that. Add s_memrealtime test and change comments in smem.s to follow common style. Change test for s_memtime to use non-zero register to make it really test encoding. Add tests for s_buffer_load*. Add tests for SOPC instructions (same for SI and VI) Differential Revision: http://reviews.llvm.org/D18040 llvm-svn: 263420
2016-03-14 19:17:19 +08:00
s_bitcmp1_b32 s1, s2
[AMDGPU] Assembler: Update SOP* tests Add VI encodings. Reformat sopp.s to match style of other files. Differential Revision: http://reviews.llvm.org/D18084 llvm-svn: 263540
2016-03-15 15:44:57 +08:00
// GCN: s_bitcmp1_b32 s1, s2 ; encoding: [0x01,0x02,0x0d,0xbf]
[AMDGPU] Assembler: SOP* instruction fixes s_bitset0_b64, s_bitset1_b64 has 32-bit src0, not 64-bit. s_rfe_b64 has just one destination operand and no source. Uncomment S_BITCMP* and S_SETVSKIP, adjust SOPC_* classes for that. Add s_memrealtime test and change comments in smem.s to follow common style. Change test for s_memtime to use non-zero register to make it really test encoding. Add tests for s_buffer_load*. Add tests for SOPC instructions (same for SI and VI) Differential Revision: http://reviews.llvm.org/D18040 llvm-svn: 263420
2016-03-14 19:17:19 +08:00
s_bitcmp0_b64 s[2:3], s4
[AMDGPU] Assembler: Update SOP* tests Add VI encodings. Reformat sopp.s to match style of other files. Differential Revision: http://reviews.llvm.org/D18084 llvm-svn: 263540
2016-03-15 15:44:57 +08:00
// GCN: s_bitcmp0_b64 s[2:3], s4 ; encoding: [0x02,0x04,0x0e,0xbf]
[AMDGPU] Assembler: SOP* instruction fixes s_bitset0_b64, s_bitset1_b64 has 32-bit src0, not 64-bit. s_rfe_b64 has just one destination operand and no source. Uncomment S_BITCMP* and S_SETVSKIP, adjust SOPC_* classes for that. Add s_memrealtime test and change comments in smem.s to follow common style. Change test for s_memtime to use non-zero register to make it really test encoding. Add tests for s_buffer_load*. Add tests for SOPC instructions (same for SI and VI) Differential Revision: http://reviews.llvm.org/D18040 llvm-svn: 263420
2016-03-14 19:17:19 +08:00
s_bitcmp1_b64 s[2:3], s4
[AMDGPU] Assembler: Update SOP* tests Add VI encodings. Reformat sopp.s to match style of other files. Differential Revision: http://reviews.llvm.org/D18084 llvm-svn: 263540
2016-03-15 15:44:57 +08:00
// GCN: s_bitcmp1_b64 s[2:3], s4 ; encoding: [0x02,0x04,0x0f,0xbf]
[AMDGPU] Assembler: SOP* instruction fixes s_bitset0_b64, s_bitset1_b64 has 32-bit src0, not 64-bit. s_rfe_b64 has just one destination operand and no source. Uncomment S_BITCMP* and S_SETVSKIP, adjust SOPC_* classes for that. Add s_memrealtime test and change comments in smem.s to follow common style. Change test for s_memtime to use non-zero register to make it really test encoding. Add tests for s_buffer_load*. Add tests for SOPC instructions (same for SI and VI) Differential Revision: http://reviews.llvm.org/D18040 llvm-svn: 263420
2016-03-14 19:17:19 +08:00
s_setvskip s3, s5
[AMDGPU] Assembler: Update SOP* tests Add VI encodings. Reformat sopp.s to match style of other files. Differential Revision: http://reviews.llvm.org/D18084 llvm-svn: 263540
2016-03-15 15:44:57 +08:00
// GCN: s_setvskip s3, s5 ; encoding: [0x03,0x05,0x10,0xbf]
AMDGPU: Use i64 scalar compare instructions VI added eq/ne for i64, so use them. llvm-svn: 281800
2016-09-17 10:02:19 +08:00
s_cmp_eq_u64 s[0:1], s[2:3]
// VI: s_cmp_eq_u64 s[0:1], s[2:3] ; encoding: [0x00,0x02,0x12,0xbf]
// NOSICI: error: instruction not supported on this GPU
s_cmp_lg_u64 s[0:1], s[2:3]
// VI: s_cmp_lg_u64 s[0:1], s[2:3] ; encoding: [0x00,0x02,0x13,0xbf]
// NOSICI: error: instruction not supported on this GPU
AMDGPU: Add instruction definitions for VGPR indexing VI added a second method of indexing into VGPRs besides using v_movrel* llvm-svn: 284027
2016-10-13 02:00:51 +08:00
s_set_gpr_idx_on s0, 0
// VI: s_set_gpr_idx_on s0, 0 ; encoding: [0x00,0x00,0x11,0xbf]
// NOSICI: error: instruction not supported on this GPU
s_set_gpr_idx_on s0, 1
// VI: s_set_gpr_idx_on s0, src0 ; encoding: [0x00,0x01,0x11,0xbf]
// NOSICI: error: instruction not supported on this GPU
s_set_gpr_idx_on s0, 3
// VI: s_set_gpr_idx_on s0, src0 src1 ; encoding: [0x00,0x03,0x11,0xbf]
// NOSICI: error: instruction not supported on this GPU
s_set_gpr_idx_on s0, 15
// VI: s_set_gpr_idx_on s0, dst src0 src1 src2 ; encoding: [0x00,0x0f,0x11,0xbf]
// NOSICI: error: instruction not supported on this GPU