2017-08-07 22:58:04 +08:00
|
|
|
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
|
|
|
|
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
|
2016-11-13 15:01:11 +08:00
|
|
|
|
|
|
|
declare half @llvm.exp2.f16(half %a)
|
|
|
|
declare <2 x half> @llvm.exp2.v2f16(<2 x half> %a)
|
|
|
|
|
|
|
|
; GCN-LABEL: {{^}}exp2_f16
|
|
|
|
; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
|
|
|
|
; SI: v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]
|
|
|
|
; SI: v_exp_f32_e32 v[[R_F32:[0-9]+]], v[[A_F32]]
|
|
|
|
; SI: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[R_F32]]
|
|
|
|
; VI: v_exp_f16_e32 v[[R_F16:[0-9]+]], v[[A_F16]]
|
|
|
|
; GCN: buffer_store_short v[[R_F16]]
|
|
|
|
; GCN: s_endpgm
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @exp2_f16(
|
2016-11-13 15:01:11 +08:00
|
|
|
half addrspace(1)* %r,
|
|
|
|
half addrspace(1)* %a) {
|
|
|
|
entry:
|
|
|
|
%a.val = load half, half addrspace(1)* %a
|
|
|
|
%r.val = call half @llvm.exp2.f16(half %a.val)
|
|
|
|
store half %r.val, half addrspace(1)* %r
|
|
|
|
ret void
|
|
|
|
}
|
|
|
|
|
|
|
|
; GCN-LABEL: {{^}}exp2_v2f16
|
|
|
|
; GCN: buffer_load_dword v[[A_V2_F16:[0-9]+]]
|
|
|
|
; SI: v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[A_V2_F16]]
|
2017-04-06 23:03:28 +08:00
|
|
|
; SI: v_lshrrev_b32_e32 v[[A_F16_1:[0-9]+]], 16, v[[A_V2_F16]]
|
2016-11-13 15:01:11 +08:00
|
|
|
; SI: v_cvt_f32_f16_e32 v[[A_F32_1:[0-9]+]], v[[A_F16_1]]
|
|
|
|
; SI: v_exp_f32_e32 v[[R_F32_0:[0-9]+]], v[[A_F32_0]]
|
|
|
|
; SI: v_cvt_f16_f32_e32 v[[R_F16_0:[0-9]+]], v[[R_F32_0]]
|
|
|
|
; SI: v_exp_f32_e32 v[[R_F32_1:[0-9]+]], v[[A_F32_1]]
|
|
|
|
; SI: v_cvt_f16_f32_e32 v[[R_F16_1:[0-9]+]], v[[R_F32_1]]
|
2017-04-06 23:03:28 +08:00
|
|
|
; SI-DAG: v_lshlrev_b32_e32 v[[R_F16_HI:[0-9]+]], 16, v[[R_F16_1]]
|
|
|
|
; SI-NOT: and
|
2017-07-11 03:53:57 +08:00
|
|
|
; SI: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_0]], v[[R_F16_HI]]
|
2017-04-06 23:03:28 +08:00
|
|
|
|
|
|
|
; VI-DAG: v_exp_f16_e32 v[[R_F16_0:[0-9]+]], v[[A_V2_F16]]
|
|
|
|
; VI-DAG: v_exp_f16_sdwa v[[R_F16_1:[0-9]+]], v[[A_V2_F16]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1
|
|
|
|
; VI-NOT: and
|
2017-07-11 03:53:57 +08:00
|
|
|
; VI: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_0]], v[[R_F16_1]]
|
2017-04-06 23:03:28 +08:00
|
|
|
|
2016-11-13 15:01:11 +08:00
|
|
|
; GCN: buffer_store_dword v[[R_V2_F16]]
|
|
|
|
; GCN: s_endpgm
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @exp2_v2f16(
|
2016-11-13 15:01:11 +08:00
|
|
|
<2 x half> addrspace(1)* %r,
|
|
|
|
<2 x half> addrspace(1)* %a) {
|
|
|
|
entry:
|
|
|
|
%a.val = load <2 x half>, <2 x half> addrspace(1)* %a
|
|
|
|
%r.val = call <2 x half> @llvm.exp2.v2f16(<2 x half> %a.val)
|
|
|
|
store <2 x half> %r.val, <2 x half> addrspace(1)* %r
|
|
|
|
ret void
|
|
|
|
}
|