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llvm-project/llvm/test/CodeGen/ARM/bswap16.ll

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[ARM] Regenerate BSWAP16 tests llvm-svn: 367543
2019-08-01 19:12:10 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
[ARM] Remove more unused check prefixes, NFC
2020-11-14 23:37:53 +08:00
; RUN: llc < %s -mtriple=arm-darwin -mattr=v6 | FileCheck %s --check-prefixes=CHECK
; RUN: llc < %s -mtriple=thumb-darwin -mattr=v6 | FileCheck %s --check-prefixes=CHECK
Add support bswap16 to/from memory compiling to rev16 on ARM/Thumb The current patterns for REV16 misses mostn __builtin_bswap16() due to legalization promoting the operands to from load/stores toi32s and then truncing/extending them. This patch adds new patterns that catch the resultant DAGs and codegens them to rev16 instructions. Tests included. rdar://15353652 llvm-svn: 208620
2014-05-13 03:53:52 +08:00
define void @test1(i16* nocapture %data) {
[ARM] Regenerate BSWAP16 tests llvm-svn: 367543
2019-08-01 19:12:10 +08:00
; CHECK-LABEL: test1:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrh r1, [r0]
; CHECK-NEXT: rev16 r1, r1
; CHECK-NEXT: strh r1, [r0]
; CHECK-NEXT: bx lr
Add support bswap16 to/from memory compiling to rev16 on ARM/Thumb The current patterns for REV16 misses mostn __builtin_bswap16() due to legalization promoting the operands to from load/stores toi32s and then truncing/extending them. This patch adds new patterns that catch the resultant DAGs and codegens them to rev16 instructions. Tests included. rdar://15353652 llvm-svn: 208620
2014-05-13 03:53:52 +08:00
entry:
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%0 = load i16, i16* %data, align 2
Add support bswap16 to/from memory compiling to rev16 on ARM/Thumb The current patterns for REV16 misses mostn __builtin_bswap16() due to legalization promoting the operands to from load/stores toi32s and then truncing/extending them. This patch adds new patterns that catch the resultant DAGs and codegens them to rev16 instructions. Tests included. rdar://15353652 llvm-svn: 208620
2014-05-13 03:53:52 +08:00
%1 = tail call i16 @llvm.bswap.i16(i16 %0)
store i16 %1, i16* %data, align 2
ret void
}
define void @test2(i16* nocapture %data, i16 zeroext %in) {
[ARM] Regenerate BSWAP16 tests llvm-svn: 367543
2019-08-01 19:12:10 +08:00
; CHECK-LABEL: test2:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: rev16 r1, r1
; CHECK-NEXT: strh r1, [r0]
; CHECK-NEXT: bx lr
Add support bswap16 to/from memory compiling to rev16 on ARM/Thumb The current patterns for REV16 misses mostn __builtin_bswap16() due to legalization promoting the operands to from load/stores toi32s and then truncing/extending them. This patch adds new patterns that catch the resultant DAGs and codegens them to rev16 instructions. Tests included. rdar://15353652 llvm-svn: 208620
2014-05-13 03:53:52 +08:00
entry:
%0 = tail call i16 @llvm.bswap.i16(i16 %in)
store i16 %0, i16* %data, align 2
ret void
}
define i16 @test3(i16* nocapture %data) {
[ARM] Regenerate BSWAP16 tests llvm-svn: 367543
2019-08-01 19:12:10 +08:00
; CHECK-LABEL: test3:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrh r0, [r0]
; CHECK-NEXT: rev16 r0, r0
; CHECK-NEXT: bx lr
Add support bswap16 to/from memory compiling to rev16 on ARM/Thumb The current patterns for REV16 misses mostn __builtin_bswap16() due to legalization promoting the operands to from load/stores toi32s and then truncing/extending them. This patch adds new patterns that catch the resultant DAGs and codegens them to rev16 instructions. Tests included. rdar://15353652 llvm-svn: 208620
2014-05-13 03:53:52 +08:00
entry:
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%0 = load i16, i16* %data, align 2
Add support bswap16 to/from memory compiling to rev16 on ARM/Thumb The current patterns for REV16 misses mostn __builtin_bswap16() due to legalization promoting the operands to from load/stores toi32s and then truncing/extending them. This patch adds new patterns that catch the resultant DAGs and codegens them to rev16 instructions. Tests included. rdar://15353652 llvm-svn: 208620
2014-05-13 03:53:52 +08:00
%1 = tail call i16 @llvm.bswap.i16(i16 %0)
ret i16 %1
}
declare i16 @llvm.bswap.i16(i16)