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[PowerPC][NFC] Precommit a test case where ppc-mi-peepholes miscompiles extswsli Added a test case to show codegen differences. llvm-svn: 366666
2019-07-22 13:32:20 +08:00
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O3 -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown -mcpu=pwr9 -run-pass=ppc-mi-peepholes \
# RUN: -simplify-mir %s -o - | FileCheck %s
---
name: poc
[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing Summary: This catches malformed mir files which specify alignment as log2 instead of pow2. See https://reviews.llvm.org/D65945 for reference, This is patch is part of a series to introduce an Alignment type. See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this patch for the introduction of the type: https://reviews.llvm.org/D64790 Reviewers: courbet Subscribers: MatzeB, qcolombet, dschuff, arsenm, sdardis, nemanjai, jvesely, nhaehnle, hiraditya, kbarton, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, s.egerton, pzheng, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67433 llvm-svn: 371608
2019-09-11 19:16:48 +08:00
alignment: 16
[PowerPC][NFC] Precommit a test case where ppc-mi-peepholes miscompiles extswsli Added a test case to show codegen differences. llvm-svn: 366666
2019-07-22 13:32:20 +08:00
tracksRegLiveness: true
body: |
; CHECK-LABEL: name: poc
; CHECK: bb.0.entry:
; CHECK: successors: %bb.1, %bb.2
; CHECK: liveins: $x3, $x4, $x5, $x6
; CHECK: [[COPY:%[0-9]+]]:g8rc = COPY $x6
; CHECK: [[COPY1:%[0-9]+]]:g8rc = COPY $x5
; CHECK: [[COPY2:%[0-9]+]]:g8rc = COPY $x4
; CHECK: [[COPY3:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY $x3
[PowerPC][NFC] Rename record instructions to use _rec suffix instead of o We use o suffix to indicate record form instuctions, (as it is similar to dot '.' in mne?) This was fine before, as we did not support XO-form. However, with https://reviews.llvm.org/D66902, we now have XO-form support. It becomes confusing now to still use 'o' for record form, and it is weird to have something like 'Oo' . This patch rename all 'o' instructions to use '_rec' instead. Also rename `isDot` to `isRecordForm`. Reviewed By: #powerpc, hfinkel, nemanjai, steven.zhang, lkail Differential Revision: https://reviews.llvm.org/D70758
2020-01-07 03:05:12 +08:00
; CHECK: [[ANDI8_rec_:%[0-9]+]]:g8rc = ANDI8_rec [[COPY1]], 1, implicit-def $cr0
[PowerPC][NFC] Precommit a test case where ppc-mi-peepholes miscompiles extswsli Added a test case to show codegen differences. llvm-svn: 366666
2019-07-22 13:32:20 +08:00
; CHECK: [[COPY4:%[0-9]+]]:crbitrc = COPY $cr0gt
; CHECK: BCn killed [[COPY4]], %bb.2
; CHECK: B %bb.1
; CHECK: bb.1:
; CHECK: liveins: $x3
[PowerPC][Peephole] Check if `extsw`'s second operand is a virtual register Summary: When combining `extsw` and `sldi` in `PPCMIPeephole`, we have to check if `extsw`'s second operand is a virtual register, otherwise we might get miscompile. Differential Revision: https://reviews.llvm.org/D65315 llvm-svn: 367645
2019-08-02 11:14:17 +08:00
; CHECK: [[EXTSW:%[0-9]+]]:g8rc = EXTSW $x3
[PowerPC][NFC] Rename record instructions to use _rec suffix instead of o We use o suffix to indicate record form instuctions, (as it is similar to dot '.' in mne?) This was fine before, as we did not support XO-form. However, with https://reviews.llvm.org/D66902, we now have XO-form support. It becomes confusing now to still use 'o' for record form, and it is weird to have something like 'Oo' . This patch rename all 'o' instructions to use '_rec' instead. Also rename `isDot` to `isRecordForm`. Reviewed By: #powerpc, hfinkel, nemanjai, steven.zhang, lkail Differential Revision: https://reviews.llvm.org/D70758
2020-01-07 03:05:12 +08:00
; CHECK: [[RLDICR:%[0-9]+]]:g8rc = RLDICR [[ANDI8_rec_]], 2, 61
[PowerPC][NFC] Precommit a test case where ppc-mi-peepholes miscompiles extswsli Added a test case to show codegen differences. llvm-svn: 366666
2019-07-22 13:32:20 +08:00
; CHECK: $x3 = COPY [[RLDICR]]
[PowerPC][Peephole] Check if `extsw`'s second operand is a virtual register Summary: When combining `extsw` and `sldi` in `PPCMIPeephole`, we have to check if `extsw`'s second operand is a virtual register, otherwise we might get miscompile. Differential Revision: https://reviews.llvm.org/D65315 llvm-svn: 367645
2019-08-02 11:14:17 +08:00
; CHECK: [[RLDICR1:%[0-9]+]]:g8rc = RLDICR [[EXTSW]], 2, 61
; CHECK: [[ADD8_:%[0-9]+]]:g8rc = ADD8 [[COPY3]], [[RLDICR1]]
[PowerPC][NFC] Precommit a test case where ppc-mi-peepholes miscompiles extswsli Added a test case to show codegen differences. llvm-svn: 366666
2019-07-22 13:32:20 +08:00
; CHECK: $x3 = COPY [[ADD8_]]
; CHECK: BLR8 implicit $lr8, implicit $rm, implicit $x3
; CHECK: bb.2:
; CHECK: [[COPY5:%[0-9]+]]:gprc = COPY [[COPY]].sub_32
; CHECK: [[DEF:%[0-9]+]]:g8rc = IMPLICIT_DEF
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:g8rc = INSERT_SUBREG [[DEF]], [[COPY5]], %subreg.sub_32
; CHECK: $x3 = COPY [[INSERT_SUBREG]]
; CHECK: BLR8 implicit $lr8, implicit $rm, implicit $x3
bb.0.entry:
successors: %bb.1, %bb.2
liveins: $x3, $x4, $x5, $x6
%4:g8rc = COPY $x6
%3:g8rc = COPY $x5
%2:g8rc = COPY $x4
%1:g8rc_and_g8rc_nox0 = COPY $x3
[PowerPC][NFC] Rename record instructions to use _rec suffix instead of o We use o suffix to indicate record form instuctions, (as it is similar to dot '.' in mne?) This was fine before, as we did not support XO-form. However, with https://reviews.llvm.org/D66902, we now have XO-form support. It becomes confusing now to still use 'o' for record form, and it is weird to have something like 'Oo' . This patch rename all 'o' instructions to use '_rec' instead. Also rename `isDot` to `isRecordForm`. Reviewed By: #powerpc, hfinkel, nemanjai, steven.zhang, lkail Differential Revision: https://reviews.llvm.org/D70758
2020-01-07 03:05:12 +08:00
%11:g8rc = ANDI8_rec %3, 1, implicit-def $cr0
[PowerPC][NFC] Precommit a test case where ppc-mi-peepholes miscompiles extswsli Added a test case to show codegen differences. llvm-svn: 366666
2019-07-22 13:32:20 +08:00
%6:crbitrc = COPY $cr0gt
BCn killed %6, %bb.2
B %bb.1
bb.1:
liveins: $x3
%0:g8rc = EXTSW $x3
%12:g8rc = RLDICR %11, 2, 61
$x3 = COPY %12:g8rc
%9:g8rc = RLDICR %0, 2, 61
%10:g8rc = ADD8 %1, %9
$x3 = COPY %10
BLR8 implicit $lr8, implicit $rm, implicit $x3
bb.2:
%5:gprc = COPY %4.sub_32
%8:g8rc = IMPLICIT_DEF
%7:g8rc = INSERT_SUBREG %8, %5, %subreg.sub_32
$x3 = COPY %7
BLR8 implicit $lr8, implicit $rm, implicit $x3
...