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llvm-project/llvm/lib/Target/R600/AMDGPU.td

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Add R600 backend A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX llvm-svn: 169915
2012-12-12 05:25:42 +08:00
//===-- AMDIL.td - AMDIL Tablegen files --*- tablegen -*-------------------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//==-----------------------------------------------------------------------===//
// Include AMDIL TD files
include "AMDILBase.td"
R600: Move Subtarget feature definitions into AMDGPU.td This is the convention used by the other targets. Reviewed-by: Vincent Lejeune <vljn@ovi.com> llvm-svn: 183559
2013-06-08 04:28:49 +08:00
//===----------------------------------------------------------------------===//
// Subtarget Features
//===----------------------------------------------------------------------===//
R600: Rework subtarget info and remove AMDILDevice classes This should simplify the subtarget definitions and make it easier to add new ones. Reviewed-by: Vincent Lejeune <vljn@ovi.com> llvm-svn: 183566
2013-06-08 04:37:48 +08:00
// Debugging Features
def FeatureDumpCode : SubtargetFeature <"DumpCode",
"DumpCode",
"true",
"Dump MachineInstrs in the CodeEmitter">;
R600: Enable the IR structurizer by default llvm-svn: 195031
2013-11-19 03:43:44 +08:00
def FeatureIRStructurizer : SubtargetFeature <"disable-irstructurizer",
R600: Use StructurizeCFGPass for non SI targets StructurizeCFG pass allows to make complex cfg reducible ; it allows a lot of shader from shadertoy (which exhibits complex control flow constructs) to works correctly with respect to CFG handling (and allow us to detect potential bug in other part of the backend). We provide a cmd line argument to disable the pass for debug purpose. Patch by: Vincent Lejeune Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 192363
2013-10-11 01:11:12 +08:00
"EnableIRStructurizer",
R600: Enable the IR structurizer by default llvm-svn: 195031
2013-11-19 03:43:44 +08:00
"false",
"Disable IR Structurizer">;
R600: Use StructurizeCFGPass for non SI targets StructurizeCFG pass allows to make complex cfg reducible ; it allows a lot of shader from shadertoy (which exhibits complex control flow constructs) to works correctly with respect to CFG handling (and allow us to detect potential bug in other part of the backend). We provide a cmd line argument to disable the pass for debug purpose. Patch by: Vincent Lejeune Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 192363
2013-10-11 01:11:12 +08:00
R600: Rework subtarget info and remove AMDILDevice classes This should simplify the subtarget definitions and make it easier to add new ones. Reviewed-by: Vincent Lejeune <vljn@ovi.com> llvm-svn: 183566
2013-06-08 04:37:48 +08:00
// Target features
R600: Add a SubtargetFeatture for disabling the ifcvt pass. This is useful when writing test cases for the AMDIL structurizer. llvm-svn: 195029
2013-11-19 03:43:33 +08:00
def FeatureIfCvt : SubtargetFeature <"disable-ifcvt",
"EnableIfCvt",
"false",
"Disable the if conversion pass">;
R600: Move Subtarget feature definitions into AMDGPU.td This is the convention used by the other targets. Reviewed-by: Vincent Lejeune <vljn@ovi.com> llvm-svn: 183559
2013-06-08 04:28:49 +08:00
def FeatureFP64 : SubtargetFeature<"fp64",
R600: Rework subtarget info and remove AMDILDevice classes This should simplify the subtarget definitions and make it easier to add new ones. Reviewed-by: Vincent Lejeune <vljn@ovi.com> llvm-svn: 183566
2013-06-08 04:37:48 +08:00
"FP64",
R600: Move Subtarget feature definitions into AMDGPU.td This is the convention used by the other targets. Reviewed-by: Vincent Lejeune <vljn@ovi.com> llvm-svn: 183559
2013-06-08 04:28:49 +08:00
"true",
"Enable 64bit double precision operations">;
def Feature64BitPtr : SubtargetFeature<"64BitPtr",
"Is64bit",
R600: Rework subtarget info and remove AMDILDevice classes This should simplify the subtarget definitions and make it easier to add new ones. Reviewed-by: Vincent Lejeune <vljn@ovi.com> llvm-svn: 183566
2013-06-08 04:37:48 +08:00
"true",
R600: Move Subtarget feature definitions into AMDGPU.td This is the convention used by the other targets. Reviewed-by: Vincent Lejeune <vljn@ovi.com> llvm-svn: 183559
2013-06-08 04:28:49 +08:00
"Specify if 64bit addressing should be used.">;
def Feature32on64BitPtr : SubtargetFeature<"64on32BitPtr",
"Is32on64bit",
"false",
"Specify if 64bit sized pointers with 32bit addressing should be used.">;
def FeatureR600ALUInst : SubtargetFeature<"R600ALUInst",
"R600ALUInst",
"false",
"Older version of ALU instructions encoding.">;
def FeatureVertexCache : SubtargetFeature<"HasVertexCache",
"HasVertexCache",
"true",
"Specify use of dedicated vertex cache.">;
R600: Rework subtarget info and remove AMDILDevice classes This should simplify the subtarget definitions and make it easier to add new ones. Reviewed-by: Vincent Lejeune <vljn@ovi.com> llvm-svn: 183566
2013-06-08 04:37:48 +08:00
def FeatureCaymanISA : SubtargetFeature<"caymanISA",
"CaymanISA",
"true",
"Use Cayman ISA">;
R600: Fix the fetch limits for R600 generation GPUs Reviewed-by: Vincent Lejeune <vljn@ovi.com> https://bugs.freedesktop.org/show_bug.cgi?id=64257 llvm-svn: 183560
2013-06-08 04:28:55 +08:00
class SubtargetFeatureFetchLimit <string Value> :
SubtargetFeature <"fetch"#Value,
"TexVTXClauseSize",
Value,
"Limit the maximum number of fetches in a clause to "#Value>;
R600: Move Subtarget feature definitions into AMDGPU.td This is the convention used by the other targets. Reviewed-by: Vincent Lejeune <vljn@ovi.com> llvm-svn: 183559
2013-06-08 04:28:49 +08:00
R600: Fix the fetch limits for R600 generation GPUs Reviewed-by: Vincent Lejeune <vljn@ovi.com> https://bugs.freedesktop.org/show_bug.cgi?id=64257 llvm-svn: 183560
2013-06-08 04:28:55 +08:00
def FeatureFetchLimit8 : SubtargetFeatureFetchLimit <"8">;
def FeatureFetchLimit16 : SubtargetFeatureFetchLimit <"16">;
R600: Rework subtarget info and remove AMDILDevice classes This should simplify the subtarget definitions and make it easier to add new ones. Reviewed-by: Vincent Lejeune <vljn@ovi.com> llvm-svn: 183566
2013-06-08 04:37:48 +08:00
class SubtargetFeatureGeneration <string Value,
list<SubtargetFeature> Implies> :
SubtargetFeature <Value, "Gen", "AMDGPUSubtarget::"#Value,
Value#" GPU generation", Implies>;
def FeatureR600 : SubtargetFeatureGeneration<"R600",
[FeatureR600ALUInst, FeatureFetchLimit8]>;
def FeatureR700 : SubtargetFeatureGeneration<"R700",
[FeatureFetchLimit16]>;
def FeatureEvergreen : SubtargetFeatureGeneration<"EVERGREEN",
[FeatureFetchLimit16]>;
def FeatureNorthernIslands : SubtargetFeatureGeneration<"NORTHERN_ISLANDS",
[FeatureFetchLimit16]>;
def FeatureSouthernIslands : SubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
[Feature64BitPtr, FeatureFP64]>;
R600/SI: Add compute support for CI v2 v2: - Fix LDS size calculation Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 193621
2013-10-30 00:37:28 +08:00
def FeatureSeaIslands : SubtargetFeatureGeneration<"SEA_ISLANDS",
[Feature64BitPtr, FeatureFP64]>;
R600: Fix the fetch limits for R600 generation GPUs Reviewed-by: Vincent Lejeune <vljn@ovi.com> https://bugs.freedesktop.org/show_bug.cgi?id=64257 llvm-svn: 183560
2013-06-08 04:28:55 +08:00
//===----------------------------------------------------------------------===//
Add R600 backend A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX llvm-svn: 169915
2012-12-12 05:25:42 +08:00
def AMDGPUInstrInfo : InstrInfo {
let guessInstructionProperties = 1;
}
def AMDGPU : Target {
// Pull in Instruction Info:
let InstructionSet = AMDGPUInstrInfo;
}
// Include AMDGPU TD files
include "R600Schedule.td"
include "SISchedule.td"
include "Processors.td"
include "AMDGPUInstrInfo.td"
include "AMDGPUIntrinsics.td"
include "AMDGPURegisterInfo.td"
include "AMDGPUInstructions.td"
R600/SI: add proper formal parameter handling for SI Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 176623
2013-03-07 17:03:52 +08:00
include "AMDGPUCallingConv.td"