forked from OSchip/llvm-project
104 lines
4.2 KiB
LLVM
104 lines
4.2 KiB
LLVM
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; Check that the GHC calling convention works (s390x)
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;
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; RUN: llc -mtriple=s390x-ibm-linux < %s | FileCheck %s
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@base = external global i64 ; assigned to register: r7
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@sp = external global i64 ; assigned to register: r8
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@hp = external global i64 ; assigned to register: r10
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@r1 = external global i64 ; assigned to register: r11
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@r2 = external global i64 ; assigned to register: r12
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@r3 = external global i64 ; assigned to register: r13
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@r4 = external global i64 ; assigned to register: r6
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@r5 = external global i64 ; assigned to register: r2
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@r6 = external global i64 ; assigned to register: r3
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@r7 = external global i64 ; assigned to register: r4
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@r8 = external global i64 ; assigned to register: r5
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@splim = external global i64 ; assigned to register: r9
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@f1 = external global float ; assigned to register: s8
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@f2 = external global float ; assigned to register: s9
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@f3 = external global float ; assigned to register: s10
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@f4 = external global float ; assigned to register: s11
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@f5 = external global float ; assigned to register: s0
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@f6 = external global float ; assigned to register: s1
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@d1 = external global double ; assigned to register: d12
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@d2 = external global double ; assigned to register: d13
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@d3 = external global double ; assigned to register: d14
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@d4 = external global double ; assigned to register: d15
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@d5 = external global double ; assigned to register: d2
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@d6 = external global double ; assigned to register: d3
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define ghccc void @foo() nounwind {
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entry:
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; CHECK: larl {{%r[0-9]+}}, d6
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; CHECK-NEXT: ld %f3, 0({{%r[0-9]+}})
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; CHECK-NEXT: larl {{%r[0-9]+}}, d5
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; CHECK-NEXT: ld %f2, 0({{%r[0-9]+}})
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; CHECK-NEXT: larl {{%r[0-9]+}}, d4
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; CHECK-NEXT: ld %f15, 0({{%r[0-9]+}})
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; CHECK-NEXT: larl {{%r[0-9]+}}, d3
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; CHECK-NEXT: ld %f14, 0({{%r[0-9]+}})
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; CHECK-NEXT: larl {{%r[0-9]+}}, d2
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; CHECK-NEXT: ld %f13, 0({{%r[0-9]+}})
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; CHECK-NEXT: larl {{%r[0-9]+}}, d1
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; CHECK-NEXT: ld %f12, 0({{%r[0-9]+}})
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; CHECK-NEXT: larl {{%r[0-9]+}}, f6
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; CHECK-NEXT: le %f1, 0({{%r[0-9]+}})
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; CHECK-NEXT: larl {{%r[0-9]+}}, f5
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; CHECK-NEXT: le %f0, 0({{%r[0-9]+}})
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; CHECK-NEXT: larl {{%r[0-9]+}}, f4
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; CHECK-NEXT: le %f11, 0({{%r[0-9]+}})
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; CHECK-NEXT: larl {{%r[0-9]+}}, f3
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; CHECK-NEXT: le %f10, 0({{%r[0-9]+}})
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; CHECK-NEXT: larl {{%r[0-9]+}}, f2
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; CHECK-NEXT: le %f9, 0({{%r[0-9]+}})
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; CHECK-NEXT: larl {{%r[0-9]+}}, f1
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; CHECK-NEXT: le %f8, 0({{%r[0-9]+}})
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; CHECK-NEXT: lgrl %r9, splim
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; CHECK-NEXT: lgrl %r5, r8
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; CHECK-NEXT: lgrl %r4, r7
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; CHECK-NEXT: lgrl %r3, r6
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; CHECK-NEXT: lgrl %r2, r5
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; CHECK-NEXT: lgrl %r6, r4
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; CHECK-NEXT: lgrl %r13, r3
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; CHECK-NEXT: lgrl %r12, r2
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; CHECK-NEXT: lgrl %r11, r1
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; CHECK-NEXT: lgrl %r10, hp
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; CHECK-NEXT: lgrl %r8, sp
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; CHECK-NEXT: lgrl %r7, base
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%0 = load double, double* @d6
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%1 = load double, double* @d5
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%2 = load double, double* @d4
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%3 = load double, double* @d3
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%4 = load double, double* @d2
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%5 = load double, double* @d1
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%6 = load float, float* @f6
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%7 = load float, float* @f5
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%8 = load float, float* @f4
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%9 = load float, float* @f3
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%10 = load float, float* @f2
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%11 = load float, float* @f1
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%12 = load i64, i64* @splim
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%13 = load i64, i64* @r8
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%14 = load i64, i64* @r7
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%15 = load i64, i64* @r6
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%16 = load i64, i64* @r5
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%17 = load i64, i64* @r4
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%18 = load i64, i64* @r3
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%19 = load i64, i64* @r2
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%20 = load i64, i64* @r1
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%21 = load i64, i64* @hp
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%22 = load i64, i64* @sp
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%23 = load i64, i64* @base
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; CHECK: brasl %r14, bar
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tail call ghccc void @bar(i64 %23, i64 %22, i64 %21, i64 %20, i64 %19, i64 %18, i64 %17, i64 %16, i64 %15, i64 %14, i64 %13, i64 %12,
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float %11, float %10, float %9, float %8, float %7, float %6,
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double %5, double %4, double %3, double %2, double %1, double %0) nounwind
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ret void
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}
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declare ghccc void @bar(i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64,
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float, float, float, float, float, float,
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double, double, double, double, double, double)
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