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llvm-project/llvm/test/CodeGen/PowerPC/testComparesllltsll.ll

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[PowerPC] Automatically generate various tests. NFC llvm-svn: 369700
2019-08-23 04:26:56 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
[PowerPC] Eliminate compares - add i64 sext/zext handling for SETLT/SETGT As mentioned in https://reviews.llvm.org/D33718, this simply adds another pattern to the compare elimination sequence and is committed without a differential review. llvm-svn: 314106
2017-09-25 22:05:46 +08:00
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
[PowerPC] Recommit r314244 with refactoring and off by default This re-commits everything that was pulled in r314244. The transformation is off by default (patch to enable it to follow). The code is refactored to have a single entry-point and provide fine-grained control over patterns that it selects. This patch also fixes the bugs in the original code. Everything that failed with the original patch has been re-tested with this patch (with the transformation turned on). So the patch to turn this on is soon to follow. Differential Revision: https://reviews.llvm.org/D38575 llvm-svn: 319434
2017-11-30 21:39:10 +08:00
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
[PowerPC] Automatically generate various tests. NFC llvm-svn: 369700
2019-08-23 04:26:56 +08:00
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
; RUN: --check-prefixes=CHECK,BE
[PowerPC] Eliminate compares - add i64 sext/zext handling for SETLT/SETGT As mentioned in https://reviews.llvm.org/D33718, this simply adds another pattern to the compare elimination sequence and is committed without a differential review. llvm-svn: 314106
2017-09-25 22:05:46 +08:00
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
[PowerPC] Recommit r314244 with refactoring and off by default This re-commits everything that was pulled in r314244. The transformation is off by default (patch to enable it to follow). The code is refactored to have a single entry-point and provide fine-grained control over patterns that it selects. This patch also fixes the bugs in the original code. Everything that failed with the original patch has been re-tested with this patch (with the transformation turned on). So the patch to turn this on is soon to follow. Differential Revision: https://reviews.llvm.org/D38575 llvm-svn: 319434
2017-11-30 21:39:10 +08:00
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
[PowerPC] Automatically generate various tests. NFC llvm-svn: 369700
2019-08-23 04:26:56 +08:00
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
; RUN: --check-prefixes=CHECK,LE
[PowerPC] Eliminate compares - add i64 sext/zext handling for SETLT/SETGT As mentioned in https://reviews.llvm.org/D33718, this simply adds another pattern to the compare elimination sequence and is committed without a differential review. llvm-svn: 314106
2017-09-25 22:05:46 +08:00
[NFC][PowerPC] Consolidate testing of common linkage symbols Add a new file to test the code gen for common linkage symbol. Remove common linkage in some other testcases to avoid distraction. llvm-svn: 372426
2019-09-21 04:31:37 +08:00
@glob = local_unnamed_addr global i64 0, align 8
[PowerPC] Eliminate compares - add i64 sext/zext handling for SETLT/SETGT As mentioned in https://reviews.llvm.org/D33718, this simply adds another pattern to the compare elimination sequence and is committed without a differential review. llvm-svn: 314106
2017-09-25 22:05:46 +08:00
; Function Attrs: norecurse nounwind readnone
define i64 @test_llltsll(i64 %a, i64 %b) {
; CHECK-LABEL: test_llltsll:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; CHECK: # %bb.0: # %entry
[PowerPC] Automatically generate various tests. NFC llvm-svn: 369700
2019-08-23 04:26:56 +08:00
; CHECK-NEXT: sradi r5, r3, 63
; CHECK-NEXT: rldicl r6, r4, 1, 63
[PowerPC] Ignore implicit register operands for MCInst Summary: When doing the conversion: MachineInst -> MCInst, we should ignore the implicit operands, it will expose more opportunity for InstiAlias. Reviewed By: steven.zhang Differential Revision: https://reviews.llvm.org/D77118
2020-04-17 00:22:43 +08:00
; CHECK-NEXT: subc r3, r3, r4
[PowerPC] Automatically generate various tests. NFC llvm-svn: 369700
2019-08-23 04:26:56 +08:00
; CHECK-NEXT: adde r3, r6, r5
; CHECK-NEXT: xori r3, r3, 1
[PowerPC] Eliminate compares - add i64 sext/zext handling for SETLT/SETGT As mentioned in https://reviews.llvm.org/D33718, this simply adds another pattern to the compare elimination sequence and is committed without a differential review. llvm-svn: 314106
2017-09-25 22:05:46 +08:00
; CHECK-NEXT: blr
entry:
%cmp = icmp slt i64 %a, %b
%conv1 = zext i1 %cmp to i64
ret i64 %conv1
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llltsll_sext(i64 %a, i64 %b) {
; CHECK-LABEL: test_llltsll_sext:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; CHECK: # %bb.0: # %entry
[PowerPC] Automatically generate various tests. NFC llvm-svn: 369700
2019-08-23 04:26:56 +08:00
; CHECK-NEXT: sradi r5, r3, 63
; CHECK-NEXT: rldicl r6, r4, 1, 63
[PowerPC] Ignore implicit register operands for MCInst Summary: When doing the conversion: MachineInst -> MCInst, we should ignore the implicit operands, it will expose more opportunity for InstiAlias. Reviewed By: steven.zhang Differential Revision: https://reviews.llvm.org/D77118
2020-04-17 00:22:43 +08:00
; CHECK-NEXT: subc r3, r3, r4
[PowerPC] Automatically generate various tests. NFC llvm-svn: 369700
2019-08-23 04:26:56 +08:00
; CHECK-NEXT: adde r3, r6, r5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
[PowerPC] Eliminate compares - add i64 sext/zext handling for SETLT/SETGT As mentioned in https://reviews.llvm.org/D33718, this simply adds another pattern to the compare elimination sequence and is committed without a differential review. llvm-svn: 314106
2017-09-25 22:05:46 +08:00
; CHECK-NEXT: blr
entry:
%cmp = icmp slt i64 %a, %b
%conv1 = sext i1 %cmp to i64
ret i64 %conv1
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llltsll_sext_z(i64 %a) {
; CHECK-LABEL: test_llltsll_sext_z:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; CHECK: # %bb.0: # %entry
[PowerPC] Eliminate compares - add i64 sext/zext handling for SETLT/SETGT As mentioned in https://reviews.llvm.org/D33718, this simply adds another pattern to the compare elimination sequence and is committed without a differential review. llvm-svn: 314106
2017-09-25 22:05:46 +08:00
; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp slt i64 %a, 0
%sub = sext i1 %cmp to i64
ret i64 %sub
}
; Function Attrs: norecurse nounwind
define void @test_llltsll_store(i64 %a, i64 %b) {
[PowerPC] Automatically generate various tests. NFC llvm-svn: 369700
2019-08-23 04:26:56 +08:00
; BE-LABEL: test_llltsll_store:
; BE: # %bb.0: # %entry
; BE-NEXT: sradi r6, r3, 63
; BE-NEXT: addis r5, r2, .LC0@toc@ha
[PowerPC] Ignore implicit register operands for MCInst Summary: When doing the conversion: MachineInst -> MCInst, we should ignore the implicit operands, it will expose more opportunity for InstiAlias. Reviewed By: steven.zhang Differential Revision: https://reviews.llvm.org/D77118
2020-04-17 00:22:43 +08:00
; BE-NEXT: subc r3, r3, r4
[PowerPC] Automatically generate various tests. NFC llvm-svn: 369700
2019-08-23 04:26:56 +08:00
; BE-NEXT: rldicl r3, r4, 1, 63
; BE-NEXT: ld r4, .LC0@toc@l(r5)
; BE-NEXT: adde r3, r3, r6
; BE-NEXT: xori r3, r3, 1
; BE-NEXT: std r3, 0(r4)
; BE-NEXT: blr
;
; LE-LABEL: test_llltsll_store:
; LE: # %bb.0: # %entry
; LE-NEXT: sradi r6, r3, 63
; LE-NEXT: addis r5, r2, glob@toc@ha
[PowerPC] Ignore implicit register operands for MCInst Summary: When doing the conversion: MachineInst -> MCInst, we should ignore the implicit operands, it will expose more opportunity for InstiAlias. Reviewed By: steven.zhang Differential Revision: https://reviews.llvm.org/D77118
2020-04-17 00:22:43 +08:00
; LE-NEXT: subc r3, r3, r4
[PowerPC] Automatically generate various tests. NFC llvm-svn: 369700
2019-08-23 04:26:56 +08:00
; LE-NEXT: rldicl r3, r4, 1, 63
; LE-NEXT: adde r3, r3, r6
; LE-NEXT: xori r3, r3, 1
; LE-NEXT: std r3, glob@toc@l(r5)
; LE-NEXT: blr
[PowerPC] Eliminate compares - add i64 sext/zext handling for SETLT/SETGT As mentioned in https://reviews.llvm.org/D33718, this simply adds another pattern to the compare elimination sequence and is committed without a differential review. llvm-svn: 314106
2017-09-25 22:05:46 +08:00
; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r4, r3
entry:
%cmp = icmp slt i64 %a, %b
%conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}
; Function Attrs: norecurse nounwind
define void @test_llltsll_sext_store(i64 %a, i64 %b) {
[PowerPC] Automatically generate various tests. NFC llvm-svn: 369700
2019-08-23 04:26:56 +08:00
; BE-LABEL: test_llltsll_sext_store:
; BE: # %bb.0: # %entry
; BE-NEXT: sradi r6, r3, 63
; BE-NEXT: addis r5, r2, .LC0@toc@ha
[PowerPC] Ignore implicit register operands for MCInst Summary: When doing the conversion: MachineInst -> MCInst, we should ignore the implicit operands, it will expose more opportunity for InstiAlias. Reviewed By: steven.zhang Differential Revision: https://reviews.llvm.org/D77118
2020-04-17 00:22:43 +08:00
; BE-NEXT: subc r3, r3, r4
[PowerPC] Automatically generate various tests. NFC llvm-svn: 369700
2019-08-23 04:26:56 +08:00
; BE-NEXT: rldicl r3, r4, 1, 63
; BE-NEXT: ld r4, .LC0@toc@l(r5)
; BE-NEXT: adde r3, r3, r6
; BE-NEXT: xori r3, r3, 1
; BE-NEXT: neg r3, r3
; BE-NEXT: std r3, 0(r4)
; BE-NEXT: blr
;
; LE-LABEL: test_llltsll_sext_store:
; LE: # %bb.0: # %entry
; LE-NEXT: sradi r6, r3, 63
; LE-NEXT: addis r5, r2, glob@toc@ha
[PowerPC] Ignore implicit register operands for MCInst Summary: When doing the conversion: MachineInst -> MCInst, we should ignore the implicit operands, it will expose more opportunity for InstiAlias. Reviewed By: steven.zhang Differential Revision: https://reviews.llvm.org/D77118
2020-04-17 00:22:43 +08:00
; LE-NEXT: subc r3, r3, r4
[PowerPC] Automatically generate various tests. NFC llvm-svn: 369700
2019-08-23 04:26:56 +08:00
; LE-NEXT: rldicl r3, r4, 1, 63
; LE-NEXT: adde r3, r3, r6
; LE-NEXT: xori r3, r3, 1
; LE-NEXT: neg r3, r3
; LE-NEXT: std r3, glob@toc@l(r5)
; LE-NEXT: blr
[PowerPC] Eliminate compares - add i64 sext/zext handling for SETLT/SETGT As mentioned in https://reviews.llvm.org/D33718, this simply adds another pattern to the compare elimination sequence and is committed without a differential review. llvm-svn: 314106
2017-09-25 22:05:46 +08:00
; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r4, r3
entry:
%cmp = icmp slt i64 %a, %b
%conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}
; Function Attrs: norecurse nounwind
define void @test_llltsll_sext_z_store(i64 %a) {
[PowerPC] Automatically generate various tests. NFC llvm-svn: 369700
2019-08-23 04:26:56 +08:00
; BE-LABEL: test_llltsll_sext_z_store:
; BE: # %bb.0: # %entry
; BE-NEXT: addis r4, r2, .LC0@toc@ha
; BE-NEXT: sradi r3, r3, 63
; BE-NEXT: ld r4, .LC0@toc@l(r4)
; BE-NEXT: std r3, 0(r4)
; BE-NEXT: blr
;
; LE-LABEL: test_llltsll_sext_z_store:
; LE: # %bb.0: # %entry
; LE-NEXT: addis r4, r2, glob@toc@ha
; LE-NEXT: sradi r3, r3, 63
; LE-NEXT: std r3, glob@toc@l(r4)
; LE-NEXT: blr
[PowerPC] Eliminate compares - add i64 sext/zext handling for SETLT/SETGT As mentioned in https://reviews.llvm.org/D33718, this simply adds another pattern to the compare elimination sequence and is committed without a differential review. llvm-svn: 314106
2017-09-25 22:05:46 +08:00
entry:
%cmp = icmp slt i64 %a, 0
%sub = sext i1 %cmp to i64
store i64 %sub, i64* @glob, align 8
ret void
}