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llvm-project/llvm/test/CodeGen/PowerPC/pr33093.ll

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[PPC CodeGen] Expand the bitreverse.i32 intrinsic. Differential Revision: https://reviews.llvm.org/D33572 Fix PR: https://bugs.llvm.org/show_bug.cgi?id=33093 llvm-svn: 307413
2017-07-08 00:41:55 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
define zeroext i32 @ReverseBits(i32 zeroext %n) {
; CHECK-LABEL: ReverseBits:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; CHECK: # %bb.0: # %entry
[PPC CodeGen] Expand the bitreverse.i32 intrinsic. Differential Revision: https://reviews.llvm.org/D33572 Fix PR: https://bugs.llvm.org/show_bug.cgi?id=33093 llvm-svn: 307413
2017-07-08 00:41:55 +08:00
; CHECK-NEXT: lis 4, -21846
; CHECK-NEXT: lis 5, 21845
; CHECK-NEXT: slwi 6, 3, 1
; CHECK-NEXT: srwi 3, 3, 1
; CHECK-NEXT: ori 4, 4, 43690
; CHECK-NEXT: ori 5, 5, 21845
; CHECK-NEXT: and 4, 6, 4
[PowerPC] Replace the Post RA List Scheduler with the Machine Scheduler We want to run the Machine Scheduler instead of the List Scheduler after RA. Checked with a performance run on a Power 9 machine with SPEC 2006 and while some benchmarks improved and others degraded the geomean was slightly improved with the Machine Scheduler. Differential Revision: https://reviews.llvm.org/D45265 llvm-svn: 336295
2018-07-05 02:54:25 +08:00
; CHECK-NEXT: and 3, 3, 5
; CHECK-NEXT: lis 5, 13107
[PPC CodeGen] Expand the bitreverse.i32 intrinsic. Differential Revision: https://reviews.llvm.org/D33572 Fix PR: https://bugs.llvm.org/show_bug.cgi?id=33093 llvm-svn: 307413
2017-07-08 00:41:55 +08:00
; CHECK-NEXT: or 3, 3, 4
[PowerPC] Replace the Post RA List Scheduler with the Machine Scheduler We want to run the Machine Scheduler instead of the List Scheduler after RA. Checked with a performance run on a Power 9 machine with SPEC 2006 and while some benchmarks improved and others degraded the geomean was slightly improved with the Machine Scheduler. Differential Revision: https://reviews.llvm.org/D45265 llvm-svn: 336295
2018-07-05 02:54:25 +08:00
; CHECK-NEXT: lis 4, -13108
; CHECK-NEXT: ori 5, 5, 13107
; CHECK-NEXT: slwi 6, 3, 2
; CHECK-NEXT: ori 4, 4, 52428
[PPC CodeGen] Expand the bitreverse.i32 intrinsic. Differential Revision: https://reviews.llvm.org/D33572 Fix PR: https://bugs.llvm.org/show_bug.cgi?id=33093 llvm-svn: 307413
2017-07-08 00:41:55 +08:00
; CHECK-NEXT: srwi 3, 3, 2
[PowerPC] Replace the Post RA List Scheduler with the Machine Scheduler We want to run the Machine Scheduler instead of the List Scheduler after RA. Checked with a performance run on a Power 9 machine with SPEC 2006 and while some benchmarks improved and others degraded the geomean was slightly improved with the Machine Scheduler. Differential Revision: https://reviews.llvm.org/D45265 llvm-svn: 336295
2018-07-05 02:54:25 +08:00
; CHECK-NEXT: and 4, 6, 4
[PPC CodeGen] Expand the bitreverse.i32 intrinsic. Differential Revision: https://reviews.llvm.org/D33572 Fix PR: https://bugs.llvm.org/show_bug.cgi?id=33093 llvm-svn: 307413
2017-07-08 00:41:55 +08:00
; CHECK-NEXT: and 3, 3, 5
[PowerPC] Replace the Post RA List Scheduler with the Machine Scheduler We want to run the Machine Scheduler instead of the List Scheduler after RA. Checked with a performance run on a Power 9 machine with SPEC 2006 and while some benchmarks improved and others degraded the geomean was slightly improved with the Machine Scheduler. Differential Revision: https://reviews.llvm.org/D45265 llvm-svn: 336295
2018-07-05 02:54:25 +08:00
; CHECK-NEXT: lis 5, 3855
[PPC CodeGen] Expand the bitreverse.i32 intrinsic. Differential Revision: https://reviews.llvm.org/D33572 Fix PR: https://bugs.llvm.org/show_bug.cgi?id=33093 llvm-svn: 307413
2017-07-08 00:41:55 +08:00
; CHECK-NEXT: or 3, 3, 4
[PowerPC] Replace the Post RA List Scheduler with the Machine Scheduler We want to run the Machine Scheduler instead of the List Scheduler after RA. Checked with a performance run on a Power 9 machine with SPEC 2006 and while some benchmarks improved and others degraded the geomean was slightly improved with the Machine Scheduler. Differential Revision: https://reviews.llvm.org/D45265 llvm-svn: 336295
2018-07-05 02:54:25 +08:00
; CHECK-NEXT: lis 4, -3856
; CHECK-NEXT: ori 5, 5, 3855
; CHECK-NEXT: slwi 6, 3, 4
; CHECK-NEXT: ori 4, 4, 61680
[PPC CodeGen] Expand the bitreverse.i32 intrinsic. Differential Revision: https://reviews.llvm.org/D33572 Fix PR: https://bugs.llvm.org/show_bug.cgi?id=33093 llvm-svn: 307413
2017-07-08 00:41:55 +08:00
; CHECK-NEXT: srwi 3, 3, 4
[PowerPC] Replace the Post RA List Scheduler with the Machine Scheduler We want to run the Machine Scheduler instead of the List Scheduler after RA. Checked with a performance run on a Power 9 machine with SPEC 2006 and while some benchmarks improved and others degraded the geomean was slightly improved with the Machine Scheduler. Differential Revision: https://reviews.llvm.org/D45265 llvm-svn: 336295
2018-07-05 02:54:25 +08:00
; CHECK-NEXT: and 4, 6, 4
[PPC CodeGen] Expand the bitreverse.i32 intrinsic. Differential Revision: https://reviews.llvm.org/D33572 Fix PR: https://bugs.llvm.org/show_bug.cgi?id=33093 llvm-svn: 307413
2017-07-08 00:41:55 +08:00
; CHECK-NEXT: and 3, 3, 5
; CHECK-NEXT: or 3, 3, 4
; CHECK-NEXT: rotlwi 4, 3, 24
; CHECK-NEXT: rlwimi 4, 3, 8, 8, 15
; CHECK-NEXT: rlwimi 4, 3, 8, 24, 31
; CHECK-NEXT: rldicl 3, 4, 0, 32
; CHECK-NEXT: clrldi 3, 3, 32
; CHECK-NEXT: blr
entry:
%shr = lshr i32 %n, 1
%and = and i32 %shr, 1431655765
%and1 = shl i32 %n, 1
%shl = and i32 %and1, -1431655766
%or = or i32 %and, %shl
%shr2 = lshr i32 %or, 2
%and3 = and i32 %shr2, 858993459
%and4 = shl i32 %or, 2
%shl5 = and i32 %and4, -858993460
%or6 = or i32 %and3, %shl5
%shr7 = lshr i32 %or6, 4
%and8 = and i32 %shr7, 252645135
%and9 = shl i32 %or6, 4
%shl10 = and i32 %and9, -252645136
%or11 = or i32 %and8, %shl10
%shr13 = lshr i32 %or11, 24
%and14 = lshr i32 %or11, 8
%shr15 = and i32 %and14, 65280
%and17 = shl i32 %or11, 8
%shl18 = and i32 %and17, 16711680
%shl21 = shl i32 %or11, 24
%or16 = or i32 %shl21, %shr13
%or19 = or i32 %or16, %shr15
%or22 = or i32 %or19, %shl18
ret i32 %or22
}
[PPC CodeGen] Expand the bitreverse.i64 intrinsic. Differential Revision: https://reviews.llvm.org/D34908 Fix PR: https://bugs.llvm.org/show_bug.cgi?id=33093 llvm-svn: 307563
2017-07-11 02:11:23 +08:00
define i64 @ReverseBits64(i64 %n) {
; CHECK-LABEL: ReverseBits64:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; CHECK: # %bb.0: # %entry
[PPC CodeGen] Expand the bitreverse.i64 intrinsic. Differential Revision: https://reviews.llvm.org/D34908 Fix PR: https://bugs.llvm.org/show_bug.cgi?id=33093 llvm-svn: 307563
2017-07-11 02:11:23 +08:00
; CHECK-NEXT: lis 4, -21846
; CHECK-NEXT: lis 5, 21845
[PowerPC] Add Itineraries of IIC_IntRotateDI for P7/P8 When doing some instruction scheduling work, we noticed some missing itineraries. Before we switch to machine scheduler, those missing itineraries might not have impact to actually scheduling, because we can still get same latency due to default values. With machine scheduler, however, itineraries will have impact to scheduling. eg: NumMicroOps will default to be 0 if there is NO itineraries for specific instruction class. And most of the instruction class with itineraries will have NumMicroOps default to 1. This will has impact on the count of RetiredMOps, affects the Pending/Available Queue, then causing different scheduling or suboptimal scheduling further. Patch by jsji (Jinsong Ji) Differential Revision: https://reviews.llvm.org/D51506 llvm-svn: 341293
2018-09-03 11:14:29 +08:00
; CHECK-NEXT: lis 7, -13108
; CHECK-NEXT: lis 8, 13107
[PPC CodeGen] Expand the bitreverse.i64 intrinsic. Differential Revision: https://reviews.llvm.org/D34908 Fix PR: https://bugs.llvm.org/show_bug.cgi?id=33093 llvm-svn: 307563
2017-07-11 02:11:23 +08:00
; CHECK-NEXT: ori 4, 4, 43690
; CHECK-NEXT: ori 5, 5, 21845
[PowerPC] Add Itineraries of IIC_IntRotateDI for P7/P8 When doing some instruction scheduling work, we noticed some missing itineraries. Before we switch to machine scheduler, those missing itineraries might not have impact to actually scheduling, because we can still get same latency due to default values. With machine scheduler, however, itineraries will have impact to scheduling. eg: NumMicroOps will default to be 0 if there is NO itineraries for specific instruction class. And most of the instruction class with itineraries will have NumMicroOps default to 1. This will has impact on the count of RetiredMOps, affects the Pending/Available Queue, then causing different scheduling or suboptimal scheduling further. Patch by jsji (Jinsong Ji) Differential Revision: https://reviews.llvm.org/D51506 llvm-svn: 341293
2018-09-03 11:14:29 +08:00
; CHECK-NEXT: ori 7, 7, 52428
; CHECK-NEXT: ori 8, 8, 13107
[PPC CodeGen] Expand the bitreverse.i64 intrinsic. Differential Revision: https://reviews.llvm.org/D34908 Fix PR: https://bugs.llvm.org/show_bug.cgi?id=33093 llvm-svn: 307563
2017-07-11 02:11:23 +08:00
; CHECK-NEXT: sldi 4, 4, 32
; CHECK-NEXT: sldi 5, 5, 32
; CHECK-NEXT: oris 4, 4, 43690
; CHECK-NEXT: oris 5, 5, 21845
[PowerPC] Add Itineraries of IIC_IntRotateDI for P7/P8 When doing some instruction scheduling work, we noticed some missing itineraries. Before we switch to machine scheduler, those missing itineraries might not have impact to actually scheduling, because we can still get same latency due to default values. With machine scheduler, however, itineraries will have impact to scheduling. eg: NumMicroOps will default to be 0 if there is NO itineraries for specific instruction class. And most of the instruction class with itineraries will have NumMicroOps default to 1. This will has impact on the count of RetiredMOps, affects the Pending/Available Queue, then causing different scheduling or suboptimal scheduling further. Patch by jsji (Jinsong Ji) Differential Revision: https://reviews.llvm.org/D51506 llvm-svn: 341293
2018-09-03 11:14:29 +08:00
; CHECK-NEXT: sldi 6, 3, 1
; CHECK-NEXT: rldicl 3, 3, 63, 1
[PPC CodeGen] Expand the bitreverse.i64 intrinsic. Differential Revision: https://reviews.llvm.org/D34908 Fix PR: https://bugs.llvm.org/show_bug.cgi?id=33093 llvm-svn: 307563
2017-07-11 02:11:23 +08:00
; CHECK-NEXT: ori 4, 4, 43690
; CHECK-NEXT: ori 5, 5, 21845
[PowerPC] Add Itineraries of IIC_IntRotateDI for P7/P8 When doing some instruction scheduling work, we noticed some missing itineraries. Before we switch to machine scheduler, those missing itineraries might not have impact to actually scheduling, because we can still get same latency due to default values. With machine scheduler, however, itineraries will have impact to scheduling. eg: NumMicroOps will default to be 0 if there is NO itineraries for specific instruction class. And most of the instruction class with itineraries will have NumMicroOps default to 1. This will has impact on the count of RetiredMOps, affects the Pending/Available Queue, then causing different scheduling or suboptimal scheduling further. Patch by jsji (Jinsong Ji) Differential Revision: https://reviews.llvm.org/D51506 llvm-svn: 341293
2018-09-03 11:14:29 +08:00
; CHECK-NEXT: sldi 7, 7, 32
; CHECK-NEXT: sldi 8, 8, 32
; CHECK-NEXT: and 4, 6, 4
[PPC CodeGen] Expand the bitreverse.i64 intrinsic. Differential Revision: https://reviews.llvm.org/D34908 Fix PR: https://bugs.llvm.org/show_bug.cgi?id=33093 llvm-svn: 307563
2017-07-11 02:11:23 +08:00
; CHECK-NEXT: and 3, 3, 5
[PowerPC] Add Itineraries of IIC_IntRotateDI for P7/P8 When doing some instruction scheduling work, we noticed some missing itineraries. Before we switch to machine scheduler, those missing itineraries might not have impact to actually scheduling, because we can still get same latency due to default values. With machine scheduler, however, itineraries will have impact to scheduling. eg: NumMicroOps will default to be 0 if there is NO itineraries for specific instruction class. And most of the instruction class with itineraries will have NumMicroOps default to 1. This will has impact on the count of RetiredMOps, affects the Pending/Available Queue, then causing different scheduling or suboptimal scheduling further. Patch by jsji (Jinsong Ji) Differential Revision: https://reviews.llvm.org/D51506 llvm-svn: 341293
2018-09-03 11:14:29 +08:00
; CHECK-NEXT: lis 5, -3856
; CHECK-NEXT: oris 6, 7, 52428
; CHECK-NEXT: oris 7, 8, 13107
[PPC CodeGen] Expand the bitreverse.i64 intrinsic. Differential Revision: https://reviews.llvm.org/D34908 Fix PR: https://bugs.llvm.org/show_bug.cgi?id=33093 llvm-svn: 307563
2017-07-11 02:11:23 +08:00
; CHECK-NEXT: or 3, 3, 4
[PowerPC] Add Itineraries of IIC_IntRotateDI for P7/P8 When doing some instruction scheduling work, we noticed some missing itineraries. Before we switch to machine scheduler, those missing itineraries might not have impact to actually scheduling, because we can still get same latency due to default values. With machine scheduler, however, itineraries will have impact to scheduling. eg: NumMicroOps will default to be 0 if there is NO itineraries for specific instruction class. And most of the instruction class with itineraries will have NumMicroOps default to 1. This will has impact on the count of RetiredMOps, affects the Pending/Available Queue, then causing different scheduling or suboptimal scheduling further. Patch by jsji (Jinsong Ji) Differential Revision: https://reviews.llvm.org/D51506 llvm-svn: 341293
2018-09-03 11:14:29 +08:00
; CHECK-NEXT: lis 4, 3855
; CHECK-NEXT: ori 5, 5, 61680
; CHECK-NEXT: ori 6, 6, 52428
; CHECK-NEXT: ori 7, 7, 13107
; CHECK-NEXT: ori 4, 4, 3855
[PPC CodeGen] Expand the bitreverse.i64 intrinsic. Differential Revision: https://reviews.llvm.org/D34908 Fix PR: https://bugs.llvm.org/show_bug.cgi?id=33093 llvm-svn: 307563
2017-07-11 02:11:23 +08:00
; CHECK-NEXT: sldi 8, 3, 2
; CHECK-NEXT: rldicl 3, 3, 62, 2
[PowerPC] Add Itineraries of IIC_IntRotateDI for P7/P8 When doing some instruction scheduling work, we noticed some missing itineraries. Before we switch to machine scheduler, those missing itineraries might not have impact to actually scheduling, because we can still get same latency due to default values. With machine scheduler, however, itineraries will have impact to scheduling. eg: NumMicroOps will default to be 0 if there is NO itineraries for specific instruction class. And most of the instruction class with itineraries will have NumMicroOps default to 1. This will has impact on the count of RetiredMOps, affects the Pending/Available Queue, then causing different scheduling or suboptimal scheduling further. Patch by jsji (Jinsong Ji) Differential Revision: https://reviews.llvm.org/D51506 llvm-svn: 341293
2018-09-03 11:14:29 +08:00
; CHECK-NEXT: and 6, 8, 6
; CHECK-NEXT: and 3, 3, 7
; CHECK-NEXT: sldi 5, 5, 32
; CHECK-NEXT: sldi 4, 4, 32
; CHECK-NEXT: or 3, 3, 6
; CHECK-NEXT: oris 5, 5, 61680
; CHECK-NEXT: oris 4, 4, 3855
[PPC CodeGen] Expand the bitreverse.i64 intrinsic. Differential Revision: https://reviews.llvm.org/D34908 Fix PR: https://bugs.llvm.org/show_bug.cgi?id=33093 llvm-svn: 307563
2017-07-11 02:11:23 +08:00
; CHECK-NEXT: sldi 6, 3, 4
[PowerPC] Add Itineraries of IIC_IntRotateDI for P7/P8 When doing some instruction scheduling work, we noticed some missing itineraries. Before we switch to machine scheduler, those missing itineraries might not have impact to actually scheduling, because we can still get same latency due to default values. With machine scheduler, however, itineraries will have impact to scheduling. eg: NumMicroOps will default to be 0 if there is NO itineraries for specific instruction class. And most of the instruction class with itineraries will have NumMicroOps default to 1. This will has impact on the count of RetiredMOps, affects the Pending/Available Queue, then causing different scheduling or suboptimal scheduling further. Patch by jsji (Jinsong Ji) Differential Revision: https://reviews.llvm.org/D51506 llvm-svn: 341293
2018-09-03 11:14:29 +08:00
; CHECK-NEXT: ori 5, 5, 61680
; CHECK-NEXT: ori 4, 4, 3855
[PPC CodeGen] Expand the bitreverse.i64 intrinsic. Differential Revision: https://reviews.llvm.org/D34908 Fix PR: https://bugs.llvm.org/show_bug.cgi?id=33093 llvm-svn: 307563
2017-07-11 02:11:23 +08:00
; CHECK-NEXT: rldicl 3, 3, 60, 4
[PowerPC] Add Itineraries of IIC_IntRotateDI for P7/P8 When doing some instruction scheduling work, we noticed some missing itineraries. Before we switch to machine scheduler, those missing itineraries might not have impact to actually scheduling, because we can still get same latency due to default values. With machine scheduler, however, itineraries will have impact to scheduling. eg: NumMicroOps will default to be 0 if there is NO itineraries for specific instruction class. And most of the instruction class with itineraries will have NumMicroOps default to 1. This will has impact on the count of RetiredMOps, affects the Pending/Available Queue, then causing different scheduling or suboptimal scheduling further. Patch by jsji (Jinsong Ji) Differential Revision: https://reviews.llvm.org/D51506 llvm-svn: 341293
2018-09-03 11:14:29 +08:00
; CHECK-NEXT: and 5, 6, 5
; CHECK-NEXT: and 3, 3, 4
; CHECK-NEXT: or 3, 3, 5
[PPC CodeGen] Expand the bitreverse.i64 intrinsic. Differential Revision: https://reviews.llvm.org/D34908 Fix PR: https://bugs.llvm.org/show_bug.cgi?id=33093 llvm-svn: 307563
2017-07-11 02:11:23 +08:00
; CHECK-NEXT: rldicl 4, 3, 32, 32
[PowerPC] Ignore implicit register operands for MCInst Summary: When doing the conversion: MachineInst -> MCInst, we should ignore the implicit operands, it will expose more opportunity for InstiAlias. Reviewed By: steven.zhang Differential Revision: https://reviews.llvm.org/D77118
2020-04-17 00:22:43 +08:00
; CHECK-NEXT: rotlwi 5, 3, 24
; CHECK-NEXT: rotlwi 6, 4, 24
[PPC CodeGen] Fix the bitreverse.i64 intrinsic. Summary: The two 32-bit words were swapped. Update a test omitted in reverted r316270. Reviewers: jtony, aaron.ballman Subscribers: nemanjai, kbarton Differential Revision: https://reviews.llvm.org/D39163 llvm-svn: 316916
2017-10-31 00:03:44 +08:00
; CHECK-NEXT: rlwimi 5, 3, 8, 8, 15
; CHECK-NEXT: rlwimi 5, 3, 8, 24, 31
[PowerPC] Replace the Post RA List Scheduler with the Machine Scheduler We want to run the Machine Scheduler instead of the List Scheduler after RA. Checked with a performance run on a Power 9 machine with SPEC 2006 and while some benchmarks improved and others degraded the geomean was slightly improved with the Machine Scheduler. Differential Revision: https://reviews.llvm.org/D45265 llvm-svn: 336295
2018-07-05 02:54:25 +08:00
; CHECK-NEXT: rlwimi 6, 4, 8, 8, 15
[PPC CodeGen] Fix the bitreverse.i64 intrinsic. Summary: The two 32-bit words were swapped. Update a test omitted in reverted r316270. Reviewers: jtony, aaron.ballman Subscribers: nemanjai, kbarton Differential Revision: https://reviews.llvm.org/D39163 llvm-svn: 316916
2017-10-31 00:03:44 +08:00
; CHECK-NEXT: rlwimi 6, 4, 8, 24, 31
; CHECK-NEXT: sldi 3, 5, 32
; CHECK-NEXT: or 3, 3, 6
[PPC CodeGen] Expand the bitreverse.i64 intrinsic. Differential Revision: https://reviews.llvm.org/D34908 Fix PR: https://bugs.llvm.org/show_bug.cgi?id=33093 llvm-svn: 307563
2017-07-11 02:11:23 +08:00
; CHECK-NEXT: blr
entry:
%shr = lshr i64 %n, 1
%and = and i64 %shr, 6148914691236517205
%and1 = shl i64 %n, 1
%shl = and i64 %and1, -6148914691236517206
%or = or i64 %and, %shl
%shr2 = lshr i64 %or, 2
%and3 = and i64 %shr2, 3689348814741910323
%and4 = shl i64 %or, 2
%shl5 = and i64 %and4, -3689348814741910324
%or6 = or i64 %and3, %shl5
%shr7 = lshr i64 %or6, 4
%and8 = and i64 %shr7, 1085102592571150095
%and9 = shl i64 %or6, 4
%shl10 = and i64 %and9, -1085102592571150096
%or11 = or i64 %and8, %shl10
%shr13 = lshr i64 %or11, 56
%and14 = lshr i64 %or11, 40
%shr15 = and i64 %and14, 65280
%and17 = lshr i64 %or11, 24
%shr18 = and i64 %and17, 16711680
%and20 = lshr i64 %or11, 8
%shr21 = and i64 %and20, 4278190080
%and23 = shl i64 %or11, 8
%shl24 = and i64 %and23, 1095216660480
%and26 = shl i64 %or11, 24
%shl27 = and i64 %and26, 280375465082880
%and29 = shl i64 %or11, 40
%shl30 = and i64 %and29, 71776119061217280
%shl33 = shl i64 %or11, 56
%or16 = or i64 %shl33, %shr13
%or19 = or i64 %or16, %shr15
%or22 = or i64 %or19, %shr18
%or25 = or i64 %or22, %shr21
%or28 = or i64 %or25, %shl24
%or31 = or i64 %or28, %shl27
%or34 = or i64 %or31, %shl30
ret i64 %or34
}