llvm-project/llvm/test/CodeGen/PowerPC/p10-vector-divide.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
; RUN:   FileCheck %s
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
; RUN:   FileCheck %s

; This test case aims to test the vector divide instructions on Power10.
; This includes the low order and extended versions of vector divide,
; that operate on signed and unsigned words and doublewords.

define <2 x i64> @test_vdivud(<2 x i64> %a, <2 x i64> %b) {
; CHECK-LABEL: test_vdivud:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vdivud v2, v2, v3
; CHECK-NEXT:    blr
entry:
  %div = udiv <2 x i64> %a, %b
  ret <2 x i64> %div
}

define <2 x i64> @test_vdivsd(<2 x i64> %a, <2 x i64> %b) {
; CHECK-LABEL: test_vdivsd:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vdivsd v2, v2, v3
; CHECK-NEXT:    blr
entry:
  %div = sdiv <2 x i64> %a, %b
  ret <2 x i64> %div
}

define <4 x i32> @test_vdivuw(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: test_vdivuw:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vdivuw v2, v2, v3
; CHECK-NEXT:    blr
entry:
  %div = udiv <4 x i32> %a, %b
  ret <4 x i32> %div
}

define <4 x i32> @test_vdivsw(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: test_vdivsw:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vdivsw v2, v2, v3
; CHECK-NEXT:    blr
entry:
  %div = sdiv <4 x i32> %a, %b
  ret <4 x i32> %div
}