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llvm-project/llvm/test/CodeGen/PowerPC/dcbf.ll

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Add __builtin_dcbf support for PPC Summary: This patch adds support for __builtin_dcbf for PPC. __builtin_dcbf copies the contents of a modified block from the data cache to main memory and flushes the copy from the data cache. Differential revision: https://reviews.llvm.org/D59843 llvm-svn: 359517
2019-04-30 07:25:33 +08:00
; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu < %s \
; RUN: -verify-machineinstrs -ppc-asm-full-reg-names \
[PowerPC] Fix pattern for DCBFL/DCBFLP instrinsics. The previous implementation used "asm parser only" pseudo-instructions in their output patterns. Those are not meant to emit code and will caused crashes when built with -filetype=obj. Differential Revision: https://reviews.llvm.org/D80151
2020-06-09 09:54:59 +08:00
; RUN: -ppc-vsr-nums-as-vr | FileCheck %s --check-prefix=CHECK-S
; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu < %s \
; RUN: -verify-machineinstrs -ppc-asm-full-reg-names \
; RUN: -ppc-vsr-nums-as-vr --filetype=obj | \
; RUN: llvm-objdump --mcpu=future -dr - | FileCheck %s --check-prefix=CHECK-O
Add __builtin_dcbf support for PPC Summary: This patch adds support for __builtin_dcbf for PPC. __builtin_dcbf copies the contents of a modified block from the data cache to main memory and flushes the copy from the data cache. Differential revision: https://reviews.llvm.org/D59843 llvm-svn: 359517
2019-04-30 07:25:33 +08:00
; Function Attrs: nounwind
define void @dcbf_test(i8* %a) {
entry:
tail call void @llvm.ppc.dcbf(i8* %a)
[PowerPC] Fix pattern for DCBFL/DCBFLP instrinsics. The previous implementation used "asm parser only" pseudo-instructions in their output patterns. Those are not meant to emit code and will caused crashes when built with -filetype=obj. Differential Revision: https://reviews.llvm.org/D80151
2020-06-09 09:54:59 +08:00
; CHECK-S-LABEL: @dcbf_test
; CHECK-S: dcbf 0, r3
; CHECK-S-NEXT: blr
; CHECK-O-LABEL: <dcbf_test>:
; CHECK-O: 0: ac 18 00 7c dcbf 0, 3
; CHECK-O-NEXT: 4: 20 00 80 4e blr
Add __builtin_dcbf support for PPC Summary: This patch adds support for __builtin_dcbf for PPC. __builtin_dcbf copies the contents of a modified block from the data cache to main memory and flushes the copy from the data cache. Differential revision: https://reviews.llvm.org/D59843 llvm-svn: 359517
2019-04-30 07:25:33 +08:00
ret void
}
declare void @llvm.ppc.dcbf(i8*)
[PowerPC] Add support for intrinsics llvm.ppc.dcbfl and llvm.ppc.dcbflp Added support for the intrinsic llvm.ppc.dcbfl and llvm.ppc.dcbflp. These will be used for emitting cache control instructions dcbfl and dcbflp which are actually mnemonics for using dcbf instruction with different immediate arguments. dcbfl ra, rb -> dcbf ra, rb, 1 dcbflp, ra, rb -> dcbf ra, rb, 3 Differential Revision: https://reviews.llvm.org/D68411
2020-02-04 01:03:54 +08:00
; Function Attrs: nounwind
define void @dcbfl_test(i8* %a) {
entry:
tail call void @llvm.ppc.dcbfl(i8* %a)
[PowerPC] Fix pattern for DCBFL/DCBFLP instrinsics. The previous implementation used "asm parser only" pseudo-instructions in their output patterns. Those are not meant to emit code and will caused crashes when built with -filetype=obj. Differential Revision: https://reviews.llvm.org/D80151
2020-06-09 09:54:59 +08:00
; CHECK-S-LABEL: @dcbfl_test
; CHECK-S: dcbfl 0, r3
; CHECK-S-NEXT: blr
; CHECK-O-LABEL: <dcbfl_test>:
; CHECK-O: 20: ac 18 20 7c dcbfl 0, 3
; CHECK-O-NEXT: 24: 20 00 80 4e blr
[PowerPC] Add support for intrinsics llvm.ppc.dcbfl and llvm.ppc.dcbflp Added support for the intrinsic llvm.ppc.dcbfl and llvm.ppc.dcbflp. These will be used for emitting cache control instructions dcbfl and dcbflp which are actually mnemonics for using dcbf instruction with different immediate arguments. dcbfl ra, rb -> dcbf ra, rb, 1 dcbflp, ra, rb -> dcbf ra, rb, 3 Differential Revision: https://reviews.llvm.org/D68411
2020-02-04 01:03:54 +08:00
ret void
}
declare void @llvm.ppc.dcbfl(i8*)
; Function Attrs: nounwind
define void @dcbflp_test(i8* %a) {
entry:
%add.a = getelementptr inbounds i8, i8* %a, i64 3
tail call void @llvm.ppc.dcbflp(i8* %add.a)
[PowerPC] Fix pattern for DCBFL/DCBFLP instrinsics. The previous implementation used "asm parser only" pseudo-instructions in their output patterns. Those are not meant to emit code and will caused crashes when built with -filetype=obj. Differential Revision: https://reviews.llvm.org/D80151
2020-06-09 09:54:59 +08:00
; CHECK-S-LABEL: @dcbflp_test
; CHECK-S: addi r3, r3, 3
; CHECK-S-NEXT: dcbflp 0, r3
; CHECK-S-NEXT: blr
; CHECK-O-LABEL: <dcbflp_test>:
; CHECK-O: 40: 03 00 63 38 addi 3, 3, 3
; CHECK-O-NEXT: 44: ac 18 60 7c dcbflp 0, 3
; CHECK-O-NEXT: 48: 20 00 80 4e blr
[PowerPC] Add support for intrinsics llvm.ppc.dcbfl and llvm.ppc.dcbflp Added support for the intrinsic llvm.ppc.dcbfl and llvm.ppc.dcbflp. These will be used for emitting cache control instructions dcbfl and dcbflp which are actually mnemonics for using dcbf instruction with different immediate arguments. dcbfl ra, rb -> dcbf ra, rb, 1 dcbflp, ra, rb -> dcbf ra, rb, 3 Differential Revision: https://reviews.llvm.org/D68411
2020-02-04 01:03:54 +08:00
ret void
}
declare void @llvm.ppc.dcbflp(i8*)