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llvm-project/llvm/test/CodeGen/PowerPC/aix64-cc-byval.ll

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[PowerPC][AIX] Simplify the check prefixes in the ByVal lit tests. [NFC]
2020-03-19 22:45:56 +08:00
; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -stop-after=machine-cp -mcpu=pwr4 \
; RUN: -mattr=-altivec -verify-machineinstrs < %s | \
; RUN: FileCheck %s
[PowerPC][AIX] Implement by-val caller arguments in a single register. This is the first of a series of patches that adds caller support for by-value arguments. This patch add support for arguments that are passed in a single GPR. There are 3 limitation cases: -The by-value argument is larger than a single register. -There are no remaining GPRs even though the by-value argument would otherwise fit in a single GPR. -The by-value argument requires alignment greater than register width. Future patches will be required to add support for these cases as well as for the callee handling (in LowerFormalArguments_AIX) that corresponds to this work. Differential Revision: https://reviews.llvm.org/D75863
2020-03-18 22:24:34 +08:00
; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec \
; RUN: -mtriple powerpc64-ibm-aix-xcoff < %s | \
[PowerPC][AIX] Simplify the check prefixes in the ByVal lit tests. [NFC]
2020-03-19 22:45:56 +08:00
; RUN: FileCheck --check-prefix=ASM %s
[PowerPC][AIX] Implement by-val caller arguments in a single register. This is the first of a series of patches that adds caller support for by-value arguments. This patch add support for arguments that are passed in a single GPR. There are 3 limitation cases: -The by-value argument is larger than a single register. -There are no remaining GPRs even though the by-value argument would otherwise fit in a single GPR. -The by-value argument requires alignment greater than register width. Future patches will be required to add support for these cases as well as for the callee handling (in LowerFormalArguments_AIX) that corresponds to this work. Differential Revision: https://reviews.llvm.org/D75863
2020-03-18 22:24:34 +08:00
%struct.S5 = type { [5 x i8] }
@gS5 = external global %struct.S5, align 1
define void @call_test_byval_5Byte() {
entry:
[PowerPC][AIX] ByVal formal arguments in a single register. Adds support for passing ByVal formal arguments as long as they fit in a single register. Differential Revision: https://reviews.llvm.org/D76401
2020-03-25 22:17:49 +08:00
%call = call zeroext i8 @test_byval_5Byte(%struct.S5* byval(%struct.S5) align 1 @gS5)
[PowerPC][AIX] Implement by-val caller arguments in a single register. This is the first of a series of patches that adds caller support for by-value arguments. This patch add support for arguments that are passed in a single GPR. There are 3 limitation cases: -The by-value argument is larger than a single register. -There are no remaining GPRs even though the by-value argument would otherwise fit in a single GPR. -The by-value argument requires alignment greater than register width. Future patches will be required to add support for these cases as well as for the callee handling (in LowerFormalArguments_AIX) that corresponds to this work. Differential Revision: https://reviews.llvm.org/D75863
2020-03-18 22:24:34 +08:00
ret void
}
; CHECK-LABEL: name: call_test_byval_5Byte{{.*}}
[PowerPC][AIX] Simplify the check prefixes in the ByVal lit tests. [NFC]
2020-03-19 22:45:56 +08:00
; ASM-LABEL: .call_test_byval_5Byte:
[PowerPC][AIX] Implement by-val caller arguments in a single register. This is the first of a series of patches that adds caller support for by-value arguments. This patch add support for arguments that are passed in a single GPR. There are 3 limitation cases: -The by-value argument is larger than a single register. -There are no remaining GPRs even though the by-value argument would otherwise fit in a single GPR. -The by-value argument requires alignment greater than register width. Future patches will be required to add support for these cases as well as for the callee handling (in LowerFormalArguments_AIX) that corresponds to this work. Differential Revision: https://reviews.llvm.org/D75863
2020-03-18 22:24:34 +08:00
; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
[PowerPC][AIX] Simplify the check prefixes in the ByVal lit tests. [NFC]
2020-03-19 22:45:56 +08:00
; CHECK: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
; CHECK-NEXT: renamable $x[[REGADDR:[0-9]+]] = LDtoc @gS5, $x2 :: (load 8 from got)
; CHECK-DAG: renamable $x[[REG1:[0-9]+]] = LWZ8 0, killed renamable $x[[REGADDR]] :: (load 4)
; CHECK-DAG: renamable $x[[REG2:[0-9]+]] = LBZ8 4, renamable $x[[REGADDR]] :: (load 1)
; CHECK-DAG: renamable $x3 = RLWINM8 killed renamable $x[[REG2]], 24, 0, 7
; CHECK-DAG: renamable $x3 = RLDIMI killed renamable $x3, killed renamable $x[[REG1]], 32, 0
; CHECK-NEXT: BL8_NOP <mcsymbol .test_byval_5Byte>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
; CHECK-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
[PowerPC][AIX] Implement by-val caller arguments in a single register. This is the first of a series of patches that adds caller support for by-value arguments. This patch add support for arguments that are passed in a single GPR. There are 3 limitation cases: -The by-value argument is larger than a single register. -There are no remaining GPRs even though the by-value argument would otherwise fit in a single GPR. -The by-value argument requires alignment greater than register width. Future patches will be required to add support for these cases as well as for the callee handling (in LowerFormalArguments_AIX) that corresponds to this work. Differential Revision: https://reviews.llvm.org/D75863
2020-03-18 22:24:34 +08:00
; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
[PowerPC][AIX] Simplify the check prefixes in the ByVal lit tests. [NFC]
2020-03-19 22:45:56 +08:00
; ASM: stdu 1, -112(1)
; ASM-NEXT: ld [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
; ASM-DAG: lwz [[REG1:[0-9]+]], 0([[REGADDR]])
; ASM-DAG: lbz [[REG2:[0-9]+]], 4([[REGADDR]])
; ASM-DAG: rlwinm 3, [[REG2]], 24, 0, 7
; ASM-DAG: rldimi 3, [[REG1]], 32, 0
; ASM-NEXT: bl .test_byval_5Byte
; ASM-NEXT: nop
[PowerPC][AIX] Implement by-val caller arguments in a single register. This is the first of a series of patches that adds caller support for by-value arguments. This patch add support for arguments that are passed in a single GPR. There are 3 limitation cases: -The by-value argument is larger than a single register. -There are no remaining GPRs even though the by-value argument would otherwise fit in a single GPR. -The by-value argument requires alignment greater than register width. Future patches will be required to add support for these cases as well as for the callee handling (in LowerFormalArguments_AIX) that corresponds to this work. Differential Revision: https://reviews.llvm.org/D75863
2020-03-18 22:24:34 +08:00
[PowerPC][AIX] ByVal formal arguments in a single register. Adds support for passing ByVal formal arguments as long as they fit in a single register. Differential Revision: https://reviews.llvm.org/D76401
2020-03-25 22:17:49 +08:00
define zeroext i8 @test_byval_5Byte(%struct.S5* byval(%struct.S5) align 1 %s) {
entry:
%arrayidx = getelementptr inbounds %struct.S5, %struct.S5* %s, i32 0, i32 0, i32 4
%0 = load i8, i8* %arrayidx, align 1
ret i8 %0
}
; CHECK-LABEL: name: test_byval_5Byte
; CHECK: fixedStack:
; CHECK-NEXT: - { id: 0, type: default, offset: 48, size: 8, alignment: 16,
; CHECK: bb.0.entry:
; CHECK-NEXT: liveins: $x3
; CHECK: STD killed renamable $x3, 0, %fixed-stack.0 :: (store 8 into %fixed-stack.0, align 16)
; CHECK-NEXT: renamable $x3 = LBZ8 4, %fixed-stack.0 :: (dereferenceable load 1
; CHECKASM-LABEL: .test_byval_5Byte:
; ASM: std 3, 48(1)
; ASM-NEXT: lbz 3, 52(1)
; ASM-NEXT: blr
[PowerPC][AIX] Implement by-val caller arguments in a single register. This is the first of a series of patches that adds caller support for by-value arguments. This patch add support for arguments that are passed in a single GPR. There are 3 limitation cases: -The by-value argument is larger than a single register. -There are no remaining GPRs even though the by-value argument would otherwise fit in a single GPR. -The by-value argument requires alignment greater than register width. Future patches will be required to add support for these cases as well as for the callee handling (in LowerFormalArguments_AIX) that corresponds to this work. Differential Revision: https://reviews.llvm.org/D75863
2020-03-18 22:24:34 +08:00
%struct.S6 = type { [6 x i8] }
@gS6 = external global %struct.S6, align 1
define void @call_test_byval_6Byte() {
entry:
[PowerPC][AIX] ByVal formal arguments in a single register. Adds support for passing ByVal formal arguments as long as they fit in a single register. Differential Revision: https://reviews.llvm.org/D76401
2020-03-25 22:17:49 +08:00
%call = call zeroext i8 @test_byval_6Byte(%struct.S6* byval(%struct.S6) align 1 @gS6)
[PowerPC][AIX] Implement by-val caller arguments in a single register. This is the first of a series of patches that adds caller support for by-value arguments. This patch add support for arguments that are passed in a single GPR. There are 3 limitation cases: -The by-value argument is larger than a single register. -There are no remaining GPRs even though the by-value argument would otherwise fit in a single GPR. -The by-value argument requires alignment greater than register width. Future patches will be required to add support for these cases as well as for the callee handling (in LowerFormalArguments_AIX) that corresponds to this work. Differential Revision: https://reviews.llvm.org/D75863
2020-03-18 22:24:34 +08:00
ret void
}
; CHECK-LABEL: name: call_test_byval_6Byte{{.*}}
[PowerPC][AIX] Simplify the check prefixes in the ByVal lit tests. [NFC]
2020-03-19 22:45:56 +08:00
; ASM-LABEL: .call_test_byval_6Byte:
[PowerPC][AIX] Implement by-val caller arguments in a single register. This is the first of a series of patches that adds caller support for by-value arguments. This patch add support for arguments that are passed in a single GPR. There are 3 limitation cases: -The by-value argument is larger than a single register. -There are no remaining GPRs even though the by-value argument would otherwise fit in a single GPR. -The by-value argument requires alignment greater than register width. Future patches will be required to add support for these cases as well as for the callee handling (in LowerFormalArguments_AIX) that corresponds to this work. Differential Revision: https://reviews.llvm.org/D75863
2020-03-18 22:24:34 +08:00
; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
[PowerPC][AIX] Simplify the check prefixes in the ByVal lit tests. [NFC]
2020-03-19 22:45:56 +08:00
; CHECK: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
; CHECK-NEXT: renamable $x[[REGADDR:[0-9]+]] = LDtoc @gS6, $x2 :: (load 8 from got)
; CHECK-DAG: renamable $x[[REG1:[0-9]+]] = LWZ8 0, killed renamable $x[[REGADDR]] :: (load 4)
; CHECK-DAG: renamable $x[[REG2:[0-9]+]] = LHZ8 4, renamable $x[[REGADDR]] :: (load 2)
; CHECK-DAG: renamable $x3 = RLWINM8 killed renamable $x[[REG2]], 16, 0, 15
; CHECK-DAG: renamable $x3 = RLDIMI killed renamable $x3, killed renamable $x[[REG1]], 32, 0
; CHECK-NEXT: BL8_NOP <mcsymbol .test_byval_6Byte>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
; CHECK-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
[PowerPC][AIX] Implement by-val caller arguments in a single register. This is the first of a series of patches that adds caller support for by-value arguments. This patch add support for arguments that are passed in a single GPR. There are 3 limitation cases: -The by-value argument is larger than a single register. -There are no remaining GPRs even though the by-value argument would otherwise fit in a single GPR. -The by-value argument requires alignment greater than register width. Future patches will be required to add support for these cases as well as for the callee handling (in LowerFormalArguments_AIX) that corresponds to this work. Differential Revision: https://reviews.llvm.org/D75863
2020-03-18 22:24:34 +08:00
; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
[PowerPC][AIX] Simplify the check prefixes in the ByVal lit tests. [NFC]
2020-03-19 22:45:56 +08:00
; ASM: stdu 1, -112(1)
; ASM-NEXT: ld [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
; ASM-DAG: lwz [[REG1:[0-9]+]], 0([[REGADDR]])
; ASM-DAG: lhz [[REG2:[0-9]+]], 4([[REGADDR]])
; ASM-DAG: rlwinm 3, [[REG2]], 16, 0, 15
; ASM-DAG: rldimi 3, [[REG1]], 32, 0
; ASM-NEXT: bl .test_byval_6Byte
; ASM-NEXT: nop
[PowerPC][AIX] Implement by-val caller arguments in a single register. This is the first of a series of patches that adds caller support for by-value arguments. This patch add support for arguments that are passed in a single GPR. There are 3 limitation cases: -The by-value argument is larger than a single register. -There are no remaining GPRs even though the by-value argument would otherwise fit in a single GPR. -The by-value argument requires alignment greater than register width. Future patches will be required to add support for these cases as well as for the callee handling (in LowerFormalArguments_AIX) that corresponds to this work. Differential Revision: https://reviews.llvm.org/D75863
2020-03-18 22:24:34 +08:00
[PowerPC][AIX] ByVal formal arguments in a single register. Adds support for passing ByVal formal arguments as long as they fit in a single register. Differential Revision: https://reviews.llvm.org/D76401
2020-03-25 22:17:49 +08:00
define zeroext i8 @test_byval_6Byte(%struct.S6* byval(%struct.S6) align 1 %s) {
entry:
%arrayidx = getelementptr inbounds %struct.S6, %struct.S6* %s, i32 0, i32 0, i32 5
%0 = load i8, i8* %arrayidx, align 1
ret i8 %0
}
; CHECK-LABEL: name: test_byval_6Byte
; CHECK: fixedStack:
; CHECK-NEXT: - { id: 0, type: default, offset: 48, size: 8, alignment: 16,
; CHECK: bb.0.entry:
; CHECK-NEXT: liveins: $x3
; CHECK: STD killed renamable $x3, 0, %fixed-stack.0 :: (store 8 into %fixed-stack.0, align 16)
; CHECK-NEXT: renamable $x3 = LBZ8 5, %fixed-stack.0 :: (dereferenceable load 1
; CHECKASM-LABEL: .test_byval_6Byte:
; ASM: std 3, 48(1)
; ASM-NEXT: lbz 3, 53(1)
; ASM-NEXT: blr
[PowerPC][AIX] Implement by-val caller arguments in a single register. This is the first of a series of patches that adds caller support for by-value arguments. This patch add support for arguments that are passed in a single GPR. There are 3 limitation cases: -The by-value argument is larger than a single register. -There are no remaining GPRs even though the by-value argument would otherwise fit in a single GPR. -The by-value argument requires alignment greater than register width. Future patches will be required to add support for these cases as well as for the callee handling (in LowerFormalArguments_AIX) that corresponds to this work. Differential Revision: https://reviews.llvm.org/D75863
2020-03-18 22:24:34 +08:00
%struct.S7 = type { [7 x i8] }
@gS7 = external global %struct.S7, align 1
define void @call_test_byval_7Byte() {
entry:
[PowerPC][AIX] ByVal formal arguments in a single register. Adds support for passing ByVal formal arguments as long as they fit in a single register. Differential Revision: https://reviews.llvm.org/D76401
2020-03-25 22:17:49 +08:00
%call = call zeroext i8 @test_byval_7Byte(%struct.S7* byval(%struct.S7) align 1 @gS7)
[PowerPC][AIX] Implement by-val caller arguments in a single register. This is the first of a series of patches that adds caller support for by-value arguments. This patch add support for arguments that are passed in a single GPR. There are 3 limitation cases: -The by-value argument is larger than a single register. -There are no remaining GPRs even though the by-value argument would otherwise fit in a single GPR. -The by-value argument requires alignment greater than register width. Future patches will be required to add support for these cases as well as for the callee handling (in LowerFormalArguments_AIX) that corresponds to this work. Differential Revision: https://reviews.llvm.org/D75863
2020-03-18 22:24:34 +08:00
ret void
}
; CHECK-LABEL: name: call_test_byval_7Byte{{.*}}
[PowerPC][AIX] Simplify the check prefixes in the ByVal lit tests. [NFC]
2020-03-19 22:45:56 +08:00
; ASM-LABEL: .call_test_byval_7Byte:
[PowerPC][AIX] Implement by-val caller arguments in a single register. This is the first of a series of patches that adds caller support for by-value arguments. This patch add support for arguments that are passed in a single GPR. There are 3 limitation cases: -The by-value argument is larger than a single register. -There are no remaining GPRs even though the by-value argument would otherwise fit in a single GPR. -The by-value argument requires alignment greater than register width. Future patches will be required to add support for these cases as well as for the callee handling (in LowerFormalArguments_AIX) that corresponds to this work. Differential Revision: https://reviews.llvm.org/D75863
2020-03-18 22:24:34 +08:00
; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
[PowerPC][AIX] Simplify the check prefixes in the ByVal lit tests. [NFC]
2020-03-19 22:45:56 +08:00
; CHECK: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
; CHECK-NEXT: renamable $x[[REGADDR:[0-9]+]] = LDtoc @gS7, $x2 :: (load 8 from got)
; CHECK-DAG: renamable $x[[REG1:[0-9]+]] = LWZ8 0, killed renamable $x[[REGADDR]] :: (load 4)
; CHECK-DAG: renamable $x[[REG2:[0-9]+]] = LHZ8 4, renamable $x[[REGADDR]] :: (load 2)
; CHECK-DAG: renamable $x[[REG3:[0-9]+]] = LBZ8 6, renamable $x[[REGADDR]] :: (load 1)
; CHECK-DAG: renamable $x3 = RLWINM8 killed renamable $x[[REG3]], 8, 16, 23
; CHECK-DAG: renamable $x3 = RLWIMI8 killed renamable $x3, killed renamable $x[[REG2]], 16, 0, 15
; CHECK-DAG: renamable $x3 = RLDIMI killed renamable $x3, killed renamable $x[[REG1]], 32, 0
; CHECK-NEXT: BL8_NOP <mcsymbol .test_byval_7Byte>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
; CHECK-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
[PowerPC][AIX] Implement by-val caller arguments in a single register. This is the first of a series of patches that adds caller support for by-value arguments. This patch add support for arguments that are passed in a single GPR. There are 3 limitation cases: -The by-value argument is larger than a single register. -There are no remaining GPRs even though the by-value argument would otherwise fit in a single GPR. -The by-value argument requires alignment greater than register width. Future patches will be required to add support for these cases as well as for the callee handling (in LowerFormalArguments_AIX) that corresponds to this work. Differential Revision: https://reviews.llvm.org/D75863
2020-03-18 22:24:34 +08:00
; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
[PowerPC][AIX] Simplify the check prefixes in the ByVal lit tests. [NFC]
2020-03-19 22:45:56 +08:00
; ASM: stdu 1, -112(1)
; ASM-NEXT: ld [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
; ASM-DAG: lwz [[REG1:[0-9]+]], 0([[REGADDR]])
; ASM-DAG: lhz [[REG2:[0-9]+]], 4([[REGADDR]])
; ASM-DAG: lbz [[REG3:[0-9]+]], 6([[REGADDR]])
; ASM-DAG: rlwinm 3, [[REG3]], 8, 16, 23
; ASM-DAG: rlwimi 3, [[REG2]], 16, 0, 15
; ASM-DAG: rldimi 3, [[REG1]], 32, 0
; ASM-NEXT: bl .test_byval_7Byte
; ASM-NEXT: nop
[PowerPC][AIX] Implement by-val caller arguments in a single register. This is the first of a series of patches that adds caller support for by-value arguments. This patch add support for arguments that are passed in a single GPR. There are 3 limitation cases: -The by-value argument is larger than a single register. -There are no remaining GPRs even though the by-value argument would otherwise fit in a single GPR. -The by-value argument requires alignment greater than register width. Future patches will be required to add support for these cases as well as for the callee handling (in LowerFormalArguments_AIX) that corresponds to this work. Differential Revision: https://reviews.llvm.org/D75863
2020-03-18 22:24:34 +08:00
[PowerPC][AIX] ByVal formal arguments in a single register. Adds support for passing ByVal formal arguments as long as they fit in a single register. Differential Revision: https://reviews.llvm.org/D76401
2020-03-25 22:17:49 +08:00
define zeroext i8 @test_byval_7Byte(%struct.S7* byval(%struct.S7) align 1 %s) {
entry:
%arrayidx = getelementptr inbounds %struct.S7, %struct.S7* %s, i32 0, i32 0, i32 6
%0 = load i8, i8* %arrayidx, align 1
ret i8 %0
}
; CHECK-LABEL: name: test_byval_7Byte
; CHECK: fixedStack:
; CHECK-NEXT: - { id: 0, type: default, offset: 48, size: 8, alignment: 16,
; CHECK: bb.0.entry:
; CHECK-NEXT: liveins: $x3
; CHECK: STD killed renamable $x3, 0, %fixed-stack.0 :: (store 8 into %fixed-stack.0, align 16)
; CHECK-NEXT: renamable $x3 = LBZ8 6, %fixed-stack.0 :: (dereferenceable load 1
; CHECKASM-LABEL: .test_byval_7Byte:
; ASM: std 3, 48(1)
; ASM-NEXT: lbz 3, 54(1)
; ASM-NEXT: blr
[PowerPC][AIX] Implement by-val caller arguments in a single register. This is the first of a series of patches that adds caller support for by-value arguments. This patch add support for arguments that are passed in a single GPR. There are 3 limitation cases: -The by-value argument is larger than a single register. -There are no remaining GPRs even though the by-value argument would otherwise fit in a single GPR. -The by-value argument requires alignment greater than register width. Future patches will be required to add support for these cases as well as for the callee handling (in LowerFormalArguments_AIX) that corresponds to this work. Differential Revision: https://reviews.llvm.org/D75863
2020-03-18 22:24:34 +08:00
%struct.S8 = type { [8 x i8] }
@gS8 = external global %struct.S8, align 1
define void @call_test_byval_8Byte() {
entry:
[PowerPC][AIX] ByVal formal arguments in a single register. Adds support for passing ByVal formal arguments as long as they fit in a single register. Differential Revision: https://reviews.llvm.org/D76401
2020-03-25 22:17:49 +08:00
%call = call zeroext i8 @test_byval_8Byte(%struct.S8* byval(%struct.S8) align 1 @gS8)
[PowerPC][AIX] Implement by-val caller arguments in a single register. This is the first of a series of patches that adds caller support for by-value arguments. This patch add support for arguments that are passed in a single GPR. There are 3 limitation cases: -The by-value argument is larger than a single register. -There are no remaining GPRs even though the by-value argument would otherwise fit in a single GPR. -The by-value argument requires alignment greater than register width. Future patches will be required to add support for these cases as well as for the callee handling (in LowerFormalArguments_AIX) that corresponds to this work. Differential Revision: https://reviews.llvm.org/D75863
2020-03-18 22:24:34 +08:00
ret void
}
; CHECK-LABEL: name: call_test_byval_8Byte{{.*}}
[PowerPC][AIX] Simplify the check prefixes in the ByVal lit tests. [NFC]
2020-03-19 22:45:56 +08:00
; ASM-LABEL: .call_test_byval_8Byte:
[PowerPC][AIX] Implement by-val caller arguments in a single register. This is the first of a series of patches that adds caller support for by-value arguments. This patch add support for arguments that are passed in a single GPR. There are 3 limitation cases: -The by-value argument is larger than a single register. -There are no remaining GPRs even though the by-value argument would otherwise fit in a single GPR. -The by-value argument requires alignment greater than register width. Future patches will be required to add support for these cases as well as for the callee handling (in LowerFormalArguments_AIX) that corresponds to this work. Differential Revision: https://reviews.llvm.org/D75863
2020-03-18 22:24:34 +08:00
[PowerPC][AIX] Simplify the check prefixes in the ByVal lit tests. [NFC]
2020-03-19 22:45:56 +08:00
; CHECK: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
; CHECK-NEXT: renamable $x[[REGADDR:[0-9]+]] = LDtoc @gS8, $x2 :: (load 8 from got)
; CHECK-NEXT: renamable $x3 = LD 0, killed renamable $x[[REGADDR]] :: (load 8)
; CHECK-NEXT: BL8_NOP <mcsymbol .test_byval_8Byte>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
; CHECK-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
[PowerPC][AIX] Implement by-val caller arguments in a single register. This is the first of a series of patches that adds caller support for by-value arguments. This patch add support for arguments that are passed in a single GPR. There are 3 limitation cases: -The by-value argument is larger than a single register. -There are no remaining GPRs even though the by-value argument would otherwise fit in a single GPR. -The by-value argument requires alignment greater than register width. Future patches will be required to add support for these cases as well as for the callee handling (in LowerFormalArguments_AIX) that corresponds to this work. Differential Revision: https://reviews.llvm.org/D75863
2020-03-18 22:24:34 +08:00
[PowerPC][AIX] Simplify the check prefixes in the ByVal lit tests. [NFC]
2020-03-19 22:45:56 +08:00
; ASM: stdu 1, -112(1)
; ASM-NEXT: ld [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
; ASM-NEXT: ld 3, 0([[REGADDR]])
; ASM-NEXT: bl .test_byval_8Byte
; ASM-NEXT: nop
[PowerPC][AIX] ByVal formal arguments in a single register. Adds support for passing ByVal formal arguments as long as they fit in a single register. Differential Revision: https://reviews.llvm.org/D76401
2020-03-25 22:17:49 +08:00
define zeroext i8 @test_byval_8Byte(%struct.S8* byval(%struct.S8) align 1 %s) {
entry:
%arrayidx = getelementptr inbounds %struct.S8, %struct.S8* %s, i32 0, i32 0, i32 7
%0 = load i8, i8* %arrayidx, align 1
ret i8 %0
}
; CHECK-LABEL: name: test_byval_8Byte
; CHECK: fixedStack:
; CHECK-NEXT: - { id: 0, type: default, offset: 48, size: 8, alignment: 16,
; CHECK: bb.0.entry:
; CHECK-NEXT: liveins: $x3
; CHECK: renamable $x[[SCRATCH:[0-9]+]] = COPY $x3
; CHECK-DAG: renamable $x3 = RLDICL $x3, 0, 56
; CHECK-DAG: STD killed renamable $x[[SCRATCH]], 0, %fixed-stack.0 :: (store 8 into %fixed-stack.0, align 16)
; CHECKASM-LABEL: .test_byval_8Byte:
; ASM: mr [[SCRATCH:[0-9]+]], 3
; ASM-DAG: clrldi 3, 3, 56
; ASM-DAG: std [[SCRATCH]], 48(1)
; ASM-NEXT: blr