2011-08-17 05:11:21 +08:00
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@ RUN: not llvm-mc -triple=thumbv6-apple-darwin < %s 2> %t
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@ RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
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2011-08-20 04:46:54 +08:00
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@ RUN: not llvm-mc -triple=thumbv5-apple-darwin < %s 2> %t
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@ RUN: FileCheck --check-prefix=CHECK-ERRORS-V5 < %t %s
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2011-08-17 05:11:21 +08:00
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@ Check for various assembly diagnostic messages on invalid input.
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@ ADD instruction w/o 'S' suffix.
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add r1, r2, r3
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@ CHECK-ERRORS: error: invalid instruction
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@ CHECK-ERRORS: add r1, r2, r3
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@ CHECK-ERRORS: ^
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2011-08-17 06:20:01 +08:00
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@ Instructions which require v6+ for both registers to be low regs.
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add r2, r3
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mov r2, r3
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@ CHECK-ERRORS: error: instruction variant requires Thumb2
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@ CHECK-ERRORS: add r2, r3
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@ CHECK-ERRORS: ^
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2011-08-20 04:46:54 +08:00
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@ CHECK-ERRORS-V5: error: instruction variant requires ARMv6 or later
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@ CHECK-ERRORS-V5: mov r2, r3
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@ CHECK-ERRORS-V5: ^
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2011-08-18 06:49:09 +08:00
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@ Out of range immediates for ASR instruction.
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asrs r2, r3, #33
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asrs r2, r3, #0
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ CHECK-ERRORS: asrs r2, r3, #33
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ CHECK-ERRORS: asrs r2, r3, #0
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@ CHECK-ERRORS: ^
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2011-08-18 07:11:13 +08:00
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@ Out of range immediates for BKPT instruction.
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bkpt #256
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bkpt #-1
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error: invalid operand for instruction
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bkpt #256
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^
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error: invalid operand for instruction
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bkpt #-1
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^
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2011-08-19 05:50:53 +08:00
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@ Invalid writeback and register lists for LDM
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ldm r2!, {r5, r8}
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ldm r2, {r5, r7}
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@ CHECK-ERRORS: error: registers must be in range r0-r7
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@ CHECK-ERRORS: ldm r2!, {r5, r8}
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: writeback operator '!' expected
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@ CHECK-ERRORS: ldm r2, {r5, r7}
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@ CHECK-ERRORS: ^
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2011-08-20 03:29:25 +08:00
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@ Out of range immediates for LSL instruction.
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lsls r4, r5, #-1
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lsls r4, r5, #32
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ CHECK-ERRORS: lsls r4, r5, #-1
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ CHECK-ERRORS: lsls r4, r5, #32
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@ CHECK-ERRORS: ^
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2011-08-20 06:07:46 +08:00
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@ Mismatched source/destination operands for MUL instruction.
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muls r1, r2, r3
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2011-08-20 06:30:46 +08:00
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@ CHECK-ERRORS: error: destination register must match source register
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2011-08-20 06:07:46 +08:00
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@ CHECK-ERRORS: muls r1, r2, r3
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@ CHECK-ERRORS: ^
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