2017-03-23 23:25:57 +08:00
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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2017-05-21 19:13:56 +08:00
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; RUN: llc -mtriple=x86_64-linux-gnu -global-isel -verify-machineinstrs < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=SSE_FAST
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; RUN: llc -mtriple=x86_64-linux-gnu -regbankselect-greedy -global-isel -verify-machineinstrs < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=SSE_GREEDY
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2017-03-23 23:25:57 +08:00
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2017-07-10 17:26:09 +08:00
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define i1 @test_load_i1(i1 * %p1) {
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; ALL-LABEL: test_load_i1:
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; ALL: # BB#0:
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; ALL-NEXT: movb (%rdi), %al
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; ALL-NEXT: retq
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%r = load i1, i1* %p1
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ret i1 %r
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}
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2017-03-23 23:25:57 +08:00
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define i8 @test_load_i8(i8 * %p1) {
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; ALL-LABEL: test_load_i8:
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; ALL: # BB#0:
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; ALL-NEXT: movb (%rdi), %al
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; ALL-NEXT: retq
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%r = load i8, i8* %p1
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ret i8 %r
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}
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define i16 @test_load_i16(i16 * %p1) {
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; ALL-LABEL: test_load_i16:
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; ALL: # BB#0:
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; ALL-NEXT: movzwl (%rdi), %eax
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; ALL-NEXT: retq
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%r = load i16, i16* %p1
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ret i16 %r
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}
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define i32 @test_load_i32(i32 * %p1) {
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; ALL-LABEL: test_load_i32:
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; ALL: # BB#0:
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; ALL-NEXT: movl (%rdi), %eax
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; ALL-NEXT: retq
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%r = load i32, i32* %p1
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ret i32 %r
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}
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define i64 @test_load_i64(i64 * %p1) {
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; ALL-LABEL: test_load_i64:
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; ALL: # BB#0:
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; ALL-NEXT: movq (%rdi), %rax
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; ALL-NEXT: retq
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%r = load i64, i64* %p1
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ret i64 %r
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}
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define float @test_load_float(float * %p1) {
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; SSE-LABEL: test_load_float:
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; SSE: # BB#0:
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; SSE-NEXT: movl (%rdi), %eax
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; SSE-NEXT: movd %eax, %xmm0
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; SSE-NEXT: retq
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;
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2017-06-19 21:12:57 +08:00
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; ALL-LABEL: test_load_float:
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; ALL: # BB#0:
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; ALL-NEXT: movl (%rdi), %eax
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; ALL-NEXT: movd %eax, %xmm0
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; ALL-NEXT: retq
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2017-03-23 23:25:57 +08:00
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%r = load float, float* %p1
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ret float %r
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}
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define double @test_load_double(double * %p1) {
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; SSE-LABEL: test_load_double:
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; SSE: # BB#0:
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; SSE-NEXT: movq (%rdi), %rax
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2017-04-26 15:08:44 +08:00
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; SSE-NEXT: movq %rax, %xmm0
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2017-03-23 23:25:57 +08:00
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; SSE-NEXT: retq
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;
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2017-06-19 21:12:57 +08:00
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; ALL-LABEL: test_load_double:
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; ALL: # BB#0:
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; ALL-NEXT: movq (%rdi), %rax
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; ALL-NEXT: movq %rax, %xmm0
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; ALL-NEXT: retq
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2017-03-23 23:25:57 +08:00
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%r = load double, double* %p1
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ret double %r
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}
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2017-07-10 17:26:09 +08:00
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define i1 * @test_store_i1(i1 %val, i1 * %p1) {
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; ALL-LABEL: test_store_i1:
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; ALL: # BB#0:
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; ALL-NEXT: andb $1, %dil
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; ALL-NEXT: movb %dil, (%rsi)
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; ALL-NEXT: movq %rsi, %rax
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; ALL-NEXT: retq
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store i1 %val, i1* %p1
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ret i1 * %p1;
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}
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2017-03-23 23:25:57 +08:00
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define i32 * @test_store_i32(i32 %val, i32 * %p1) {
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; ALL-LABEL: test_store_i32:
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; ALL: # BB#0:
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; ALL-NEXT: movl %edi, (%rsi)
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; ALL-NEXT: movq %rsi, %rax
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; ALL-NEXT: retq
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store i32 %val, i32* %p1
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ret i32 * %p1;
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}
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define i64 * @test_store_i64(i64 %val, i64 * %p1) {
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; ALL-LABEL: test_store_i64:
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; ALL: # BB#0:
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; ALL-NEXT: movq %rdi, (%rsi)
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; ALL-NEXT: movq %rsi, %rax
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; ALL-NEXT: retq
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store i64 %val, i64* %p1
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ret i64 * %p1;
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}
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define float * @test_store_float(float %val, float * %p1) {
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;
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[GlobalISel][X86] support G_FRAME_INDEX instruction selection.
Summary:
G_LOAD/G_STORE, add alternative RegisterBank mapping.
For G_LOAD, Fast and Greedy mode choose the same RegisterBank mapping (GprRegBank ) for the G_GLOAD + G_FADD , can't get rid of cross register bank copy GprRegBank->VecRegBank.
Reviewers: zvi, rovka, qcolombet, ab
Reviewed By: zvi
Subscribers: llvm-commits, dberris, kristof.beyls, eladcohen, guyblank
Differential Revision: https://reviews.llvm.org/D30979
llvm-svn: 298907
2017-03-28 17:35:06 +08:00
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; SSE_FAST-LABEL: test_store_float:
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; SSE_FAST: # BB#0:
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; SSE_FAST-NEXT: movd %xmm0, %eax
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; SSE_FAST-NEXT: movl %eax, (%rdi)
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; SSE_FAST-NEXT: movq %rdi, %rax
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; SSE_FAST-NEXT: retq
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;
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; SSE_GREEDY-LABEL: test_store_float:
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; SSE_GREEDY: # BB#0:
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; SSE_GREEDY-NEXT: movss %xmm0, (%rdi)
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; SSE_GREEDY-NEXT: movq %rdi, %rax
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; SSE_GREEDY-NEXT: retq
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2017-03-23 23:25:57 +08:00
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store float %val, float* %p1
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ret float * %p1;
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}
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define double * @test_store_double(double %val, double * %p1) {
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;
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[GlobalISel][X86] support G_FRAME_INDEX instruction selection.
Summary:
G_LOAD/G_STORE, add alternative RegisterBank mapping.
For G_LOAD, Fast and Greedy mode choose the same RegisterBank mapping (GprRegBank ) for the G_GLOAD + G_FADD , can't get rid of cross register bank copy GprRegBank->VecRegBank.
Reviewers: zvi, rovka, qcolombet, ab
Reviewed By: zvi
Subscribers: llvm-commits, dberris, kristof.beyls, eladcohen, guyblank
Differential Revision: https://reviews.llvm.org/D30979
llvm-svn: 298907
2017-03-28 17:35:06 +08:00
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; SSE_FAST-LABEL: test_store_double:
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; SSE_FAST: # BB#0:
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2017-04-26 15:08:44 +08:00
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; SSE_FAST-NEXT: movq %xmm0, %rax
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[GlobalISel][X86] support G_FRAME_INDEX instruction selection.
Summary:
G_LOAD/G_STORE, add alternative RegisterBank mapping.
For G_LOAD, Fast and Greedy mode choose the same RegisterBank mapping (GprRegBank ) for the G_GLOAD + G_FADD , can't get rid of cross register bank copy GprRegBank->VecRegBank.
Reviewers: zvi, rovka, qcolombet, ab
Reviewed By: zvi
Subscribers: llvm-commits, dberris, kristof.beyls, eladcohen, guyblank
Differential Revision: https://reviews.llvm.org/D30979
llvm-svn: 298907
2017-03-28 17:35:06 +08:00
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; SSE_FAST-NEXT: movq %rax, (%rdi)
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; SSE_FAST-NEXT: movq %rdi, %rax
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; SSE_FAST-NEXT: retq
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;
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; SSE_GREEDY-LABEL: test_store_double:
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; SSE_GREEDY: # BB#0:
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; SSE_GREEDY-NEXT: movsd %xmm0, (%rdi)
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; SSE_GREEDY-NEXT: movq %rdi, %rax
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; SSE_GREEDY-NEXT: retq
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2017-03-23 23:25:57 +08:00
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store double %val, double* %p1
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ret double * %p1;
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}
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2017-05-01 14:08:32 +08:00
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define i32* @test_load_ptr(i32** %ptr1) {
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; ALL-LABEL: test_load_ptr:
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; ALL: # BB#0:
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; ALL-NEXT: movq (%rdi), %rax
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; ALL-NEXT: retq
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%p = load i32*, i32** %ptr1
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ret i32* %p
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}
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define void @test_store_ptr(i32** %ptr1, i32* %a) {
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; ALL-LABEL: test_store_ptr:
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; ALL: # BB#0:
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; ALL-NEXT: movq %rsi, (%rdi)
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; ALL-NEXT: retq
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store i32* %a, i32** %ptr1
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ret void
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}
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2017-06-19 21:12:57 +08:00
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define i32 @test_gep_folding(i32* %arr, i32 %val) {
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; ALL-LABEL: test_gep_folding:
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; ALL: # BB#0:
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; ALL-NEXT: movl %esi, 20(%rdi)
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; ALL-NEXT: movl 20(%rdi), %eax
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; ALL-NEXT: retq
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%arrayidx = getelementptr i32, i32* %arr, i32 5
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store i32 %val, i32* %arrayidx
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%r = load i32, i32* %arrayidx
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ret i32 %r
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}
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; check that gep index doesn't folded into memory operand
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define i32 @test_gep_folding_largeGepIndex(i32* %arr, i32 %val) {
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; ALL-LABEL: test_gep_folding_largeGepIndex:
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; ALL: # BB#0:
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; ALL-NEXT: movabsq $228719476720, %rax # imm = 0x3540BE3FF0
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[X86] Improvement in CodeGen instruction selection for LEAs (re-applying post required revision changes.)
Summary:
1/ Operand folding during complex pattern matching for LEAs has been
extended, such that it promotes Scale to accommodate similar operand
appearing in the DAG.
e.g.
T1 = A + B
T2 = T1 + 10
T3 = T2 + A
For above DAG rooted at T3, X86AddressMode will no look like
Base = B , Index = A , Scale = 2 , Disp = 10
2/ During OptimizeLEAPass down the pipeline factorization is now performed over LEAs
so that if there is an opportunity then complex LEAs (having 3 operands)
could be factored out.
e.g.
leal 1(%rax,%rcx,1), %rdx
leal 1(%rax,%rcx,2), %rcx
will be factored as following
leal 1(%rax,%rcx,1), %rdx
leal (%rdx,%rcx) , %edx
3/ Aggressive operand folding for AM based selection for LEAs is sensitive to loops,
thus avoiding creation of any complex LEAs within a loop.
Reviewers: lsaba, RKSimon, craig.topper, qcolombet, jmolloy
Reviewed By: lsaba
Subscribers: jmolloy, spatel, igorb, llvm-commits
Differential Revision: https://reviews.llvm.org/D35014
llvm-svn: 314886
2017-10-04 17:02:10 +08:00
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; ALL-NEXT: addq %rdi, %rax
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2017-06-19 21:12:57 +08:00
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; ALL-NEXT: movl %esi, (%rax)
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; ALL-NEXT: movl (%rax), %eax
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; ALL-NEXT: retq
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%arrayidx = getelementptr i32, i32* %arr, i64 57179869180
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store i32 %val, i32* %arrayidx
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%r = load i32, i32* %arrayidx
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ret i32 %r
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}
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