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llvm-project/llvm/test/CodeGen/PowerPC/retaddr2.ll

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Adding -verify-machineinstrs option to PowerPC tests Currently we have a number of tests that fail with -verify-machineinstrs. To detect this cases earlier we add the option to the testcases with the exception of tests that will currently fail with this option. PR 27456 keeps track of this failures. No code review, as discussed with Hal Finkel. llvm-svn: 277624
2016-08-04 02:17:35 +08:00
; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s
[PowerPC] Don't mark the return-address slot as immutable It is tempting to mark the fixed stack slot used to store the return address as immutable when lowering @llvm.returnaddress(i32 0). Unfortunately, within the function, it is not completely immutable: it is written during the function prologue. When using post-RA instruction scheduling, the prologue instructions are available for scheduling, and we're not free to interchange the order of a particular store in the prologue with loads from that stack location. Fixes PR21976. llvm-svn: 224761
2014-12-23 17:45:06 +08:00
target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu"
; Function Attrs: nounwind readnone
define i8* @test1() #0 {
entry:
%0 = tail call i8* @llvm.returnaddress(i32 0)
ret i8* %0
}
; CHECK-LABEL: @test1
Find available scratch register to use in function prologue and epilogue as part of shrink wrapping. Phabricator: http://reviews.llvm.org/D13955 llvm-svn: 253247
2015-11-17 04:22:15 +08:00
; CHECK: mflr {{[0-9]+}}
[PowerPC] Don't mark the return-address slot as immutable It is tempting to mark the fixed stack slot used to store the return address as immutable when lowering @llvm.returnaddress(i32 0). Unfortunately, within the function, it is not completely immutable: it is written during the function prologue. When using post-RA instruction scheduling, the prologue instructions are available for scheduling, and we're not free to interchange the order of a particular store in the prologue with loads from that stack location. Fixes PR21976. llvm-svn: 224761
2014-12-23 17:45:06 +08:00
; CHECK: std 0, 16(1)
[PowerPC] Fix reverted patch r227976 to avoid register assignment issues See full discussion in http://reviews.llvm.org/D7491. We now hide the add-immediate and call instructions together in a separate pseudo-op, which is tagged to define GPR3 and clobber the call-killed registers. The PPCTLSDynamicCall pass prior to RA now expands this op into the two separate addi and call ops, with explicit definitions of GPR3 on both instructions, and explicit clobbers on the call instruction. The pass is now marked as requiring and preserving the LiveIntervals and SlotIndexes analyses, and fixes these up after the replacement sequences are introduced. Self-hosting has been verified on LE P8 and BE P7 with various optimization levels, etc. It has also been verified with the --no-tls-optimize flag workaround removed. llvm-svn: 228725
2015-02-11 03:09:05 +08:00
; CHECK-DAG: ld 3, 64(1)
Find available scratch register to use in function prologue and epilogue as part of shrink wrapping. Phabricator: http://reviews.llvm.org/D13955 llvm-svn: 253247
2015-11-17 04:22:15 +08:00
; CHECK-DAG: ld [[SR:[0-9]+]], 16(1)
; CHECK: mtlr [[SR]]
[PowerPC] Don't mark the return-address slot as immutable It is tempting to mark the fixed stack slot used to store the return address as immutable when lowering @llvm.returnaddress(i32 0). Unfortunately, within the function, it is not completely immutable: it is written during the function prologue. When using post-RA instruction scheduling, the prologue instructions are available for scheduling, and we're not free to interchange the order of a particular store in the prologue with loads from that stack location. Fixes PR21976. llvm-svn: 224761
2014-12-23 17:45:06 +08:00
; CHECK: blr
; Function Attrs: nounwind readnone
declare i8* @llvm.returnaddress(i32) #0
attributes #0 = { nounwind readnone }