llvm-project/llvm/test/CodeGen/PowerPC/pr30640.ll

; RUN: llc -O2  -mtriple=powerpc64-linux-gnu -mcpu=pwr8 < %s | FileCheck %s

define i64 @foo() {
entry:
  ret i64 -3617008641903833651

; CHECK: lis [[REG1:[0-9]+]], -12851
; CHECK: ori [[REG2:[0-9]+]], [[REG1]], 52685
; CHECK: rldimi 3, 3, 32, 0
}
PowerPC: specify full triple to avoid different Darwin asm syntax. llvm-svn: 284281 2016-10-15 05:25:29 +08:00			`; RUN: llc -O2 -mtriple=powerpc64-linux-gnu -mcpu=pwr8 < %s \| FileCheck %s`
[PPC] Shorter sequence to load 64bit constant with same hi/lo words This is a patch to implement pr30640. When a 64bit constant has the same hi/lo words, we can use rldimi to copy the low word into high word of the same register. This optimization caused failure of test case bperm.ll because of not optimal heuristic in function SelectAndParts64. It chooses AND or ROTATE to extract bit groups from a register, and OR them together. This optimization lowers the cost of loading 64bit constant mask used in AND method, and causes different code sequence. But actually ROTATE method is better in this test case. The reason is in ROTATE method the final OR operation can be avoided since rldimi can insert the rotated bits into target register directly. So this patch also enhances SelectAndParts64 to prefer ROTATE method when the two methods have same cost and there are multiple bit groups need to be ORed together. Differential Revision: https://reviews.llvm.org/D25521 llvm-svn: 284276 2016-10-15 04:41:50 +08:00
			`define i64 @foo() {`
			`entry:`
			`ret i64 -3617008641903833651`

			`; CHECK: lis [[REG1:[0-9]+]], -12851`
			`; CHECK: ori [[REG2:[0-9]+]], [[REG1]], 52685`
			`; CHECK: rldimi 3, 3, 32, 0`
			`}`