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llvm-project/llvm/test/CodeGen/X86/stride-reuse.ll

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Trivial change to make the test use Use –mcpu=generic, so that the test will not fail when run on an Intel Atom processor, due to the Atom scheduler producing an instruction sequence that is different from that which is normally expected. llvm-svn: 151832
2012-03-02 03:57:20 +08:00
; RUN: llc < %s -mcpu=generic -march=x86 | FileCheck %s
; RUN: llc < %s -mcpu=generic -mtriple=x86_64-linux | FileCheck %s
; CHECK-NOT: lea
Strength reduction improvements. - Avoid attempting stride-reuse in the case that there are users that aren't addresses. In that case, there will be places where the multiplications won't be folded away, so it's better to try to strength-reduce them. - Several SSE intrinsics have operands that strength-reduction can treat as addresses. The previous item makes this more visible, as any non-address use of an IV can inhibit stride-reuse. - Make ValidStride aware of whether there's likely to be a base register in the address computation. This prevents it from thinking that things like stride 9 are valid on x86 when the base register is already occupied. Also, XFAIL the 2007-08-10-LEA16Use32.ll test; the new logic to avoid stride-reuse elimintes the LEA in the loop, so the test is no longer testing what it was intended to test. llvm-svn: 43231
2007-10-23 04:40:42 +08:00
@B = external global [1000 x float], align 32
@A = external global [1000 x float], align 32
@P = external global [1000 x i32], align 32
Add nounwinds. llvm-svn: 93919
2010-01-20 05:51:51 +08:00
define void @foo(i32 %m) nounwind {
Strength reduction improvements. - Avoid attempting stride-reuse in the case that there are users that aren't addresses. In that case, there will be places where the multiplications won't be folded away, so it's better to try to strength-reduce them. - Several SSE intrinsics have operands that strength-reduction can treat as addresses. The previous item makes this more visible, as any non-address use of an IV can inhibit stride-reuse. - Make ValidStride aware of whether there's likely to be a base register in the address computation. This prevents it from thinking that things like stride 9 are valid on x86 when the base register is already occupied. Also, XFAIL the 2007-08-10-LEA16Use32.ll test; the new logic to avoid stride-reuse elimintes the LEA in the loop, so the test is no longer testing what it was intended to test. llvm-svn: 43231
2007-10-23 04:40:42 +08:00
entry:
%tmp1 = icmp sgt i32 %m, 0
br i1 %tmp1, label %bb, label %return
bb:
%i.019.0 = phi i32 [ %indvar.next, %bb ], [ 0, %entry ]
%tmp2 = getelementptr [1000 x float]* @B, i32 0, i32 %i.019.0
%tmp3 = load float* %tmp2, align 4
Split the Add, Sub, and Mul instruction opcodes into separate integer and floating-point opcodes, introducing FAdd, FSub, and FMul. For now, the AsmParser, BitcodeReader, and IRBuilder all preserve backwards compatability, and the Core LLVM APIs preserve backwards compatibility for IR producers. Most front-ends won't need to change immediately. This implements the first step of the plan outlined here: http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt llvm-svn: 72897
2009-06-05 06:49:04 +08:00
%tmp4 = fmul float %tmp3, 2.000000e+00
Strength reduction improvements. - Avoid attempting stride-reuse in the case that there are users that aren't addresses. In that case, there will be places where the multiplications won't be folded away, so it's better to try to strength-reduce them. - Several SSE intrinsics have operands that strength-reduction can treat as addresses. The previous item makes this more visible, as any non-address use of an IV can inhibit stride-reuse. - Make ValidStride aware of whether there's likely to be a base register in the address computation. This prevents it from thinking that things like stride 9 are valid on x86 when the base register is already occupied. Also, XFAIL the 2007-08-10-LEA16Use32.ll test; the new logic to avoid stride-reuse elimintes the LEA in the loop, so the test is no longer testing what it was intended to test. llvm-svn: 43231
2007-10-23 04:40:42 +08:00
%tmp5 = getelementptr [1000 x float]* @A, i32 0, i32 %i.019.0
store float %tmp4, float* %tmp5, align 4
%tmp8 = shl i32 %i.019.0, 1
%tmp9 = add i32 %tmp8, 64
%tmp10 = getelementptr [1000 x i32]* @P, i32 0, i32 %i.019.0
store i32 %tmp9, i32* %tmp10, align 4
%indvar.next = add i32 %i.019.0, 1
%exitcond = icmp eq i32 %indvar.next, %m
br i1 %exitcond, label %return, label %bb
return:
ret void
}