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llvm-project/llvm/lib/Target/R600/SIISelLowering.h

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Add R600 backend A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX llvm-svn: 169915
2012-12-12 05:25:42 +08:00
//===-- SIISelLowering.h - SI DAG Lowering Interface ------------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
/// \file
/// \brief SI DAG Lowering interface definition
//
//===----------------------------------------------------------------------===//
#ifndef SIISELLOWERING_H
#define SIISELLOWERING_H
#include "AMDGPUISelLowering.h"
#include "SIInstrInfo.h"
namespace llvm {
class SITargetLowering : public AMDGPUTargetLowering {
R600: Fix handling of vector kernel arguments The SelectionDAGBuilder was promoting vector kernel arguments to legal types, but this won't work for R600 and SI since kernel arguments are stored in memory and can't be promoted. In order to handle vector arguments correctly we need to look at the original types from the LLVM IR function. llvm-svn: 193215
2013-10-23 08:44:32 +08:00
SDValue LowerParameter(SelectionDAG &DAG, EVT VT, EVT MemVT, SDLoc DL,
R600: Check if a sextload should be used for parameter loads. Through some oddity where truncate (sextload x) isn't folded into an anyextload for vectors, the sextload remains if the vector isn't immediately scalarized. This keeps the expected zextload instructions in the kernel-args test when small type vectors aren't scalarized. llvm-svn: 206070
2014-04-12 04:59:54 +08:00
SDValue Chain, unsigned Offset, bool Signed) const;
R600/SI: Convert v16i8 resource descriptors to i128 Now that compute support is better on SI, we can't continue using v16i8 for descriptors since this is also a legal type in OpenCL. This patch fixes numerous hangs with the piglit OpenCL test and since we now use a target specific DAG node for LOAD_CONSTANT with the correct MemOperandFlags, this should also fix: https://bugs.freedesktop.org/show_bug.cgi?id=66805 llvm-svn: 188429
2013-08-15 07:24:45 +08:00
SDValue LowerSampleIntrinsic(unsigned Opcode, const SDValue &Op,
SelectionDAG &DAG) const;
R600/SI: Store constant initializer data in constant memory This implements a solution for constant initializers suggested by Vadim Girlin, where we store the data after the shader code and then use the S_GETPC instruction to compute its address. This saves use the trouble of creating a new buffer for constant data and then having to pass the pointer to the kernel via user SGPRs or the input buffer. llvm-svn: 213530
2014-07-21 22:01:14 +08:00
SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
SelectionDAG &DAG) const override;
R600: Move intrinsic lowering to separate functions llvm-svn: 214023
2014-07-26 14:23:37 +08:00
SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
R600/SI: Use scratch memory for large private arrays llvm-svn: 213551
2014-07-21 23:45:01 +08:00
SDValue LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const;
R600/SI: Add support for private address space load/store Private address space is emulated using the register file with MOVRELS and MOVRELD instructions. llvm-svn: 194626
2013-11-14 07:36:50 +08:00
SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
R600/SI: Custom lower i64 ISD::SELECT llvm-svn: 200774
2014-02-05 01:18:40 +08:00
SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
R600/SI: Allow using f32 rcp / rsq when denormals not handled. These are precise enough to use for OpenCL unless denormals are handled. llvm-svn: 213107
2014-07-16 07:50:10 +08:00
SDValue LowerFastFDIV(SDValue Op, SelectionDAG &DAG) const;
R600/SI: Implement less wrong f32 fdiv Assuming single precision denormals and accurate sqrt/div are not reported, this passes the OpenCL conformance test. llvm-svn: 213089
2014-07-16 04:18:31 +08:00
SDValue LowerFDIV32(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerFDIV64(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerFDIV(SDValue Op, SelectionDAG &DAG) const;
R600/SI: Add support for private address space load/store Private address space is emulated using the register file with MOVRELS and MOVRELD instructions. llvm-svn: 194626
2013-11-14 07:36:50 +08:00
SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
R600/SI: implement range reduction for sin/cos These instructions can only take a limited input range, and return the constant value 1 out of range. We should do range reduction to be able to process arbitrary values. Use a FRACT instruction after normalization to achieve this. Also add a test for constant folding with the lowered code with unsafe-fp-math enabled. v2: use DAG lowering instead of intrinsic, adapt test v3: calculate constant, fold pattern into instruction definition v4: misc style fixes, add sin-fold testcase, cosmetics Patch by Grigori Goronzy llvm-svn: 213458
2014-07-20 02:44:39 +08:00
SDValue LowerTrig(SDValue Op, SelectionDAG &DAG) const;
R600: New control flow for SI v2 This patch replaces the control flow handling with a new pass which structurize the graph before transforming it to machine instruction. This has a couple of different advantages and currently fixes 20 piglit tests without a single regression. It is now a general purpose transformation that could be not only be used for SI/R6xx, but also for other hardware implementations that use a form of structurized control flow. v2: further cleanup, fixes and documentation Patch by: Christian König Signed-off-by: Christian König <deathsimple@vodafone.de> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Tested-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 170591
2012-12-20 06:10:31 +08:00
SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
Add R600 backend A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX llvm-svn: 169915
2012-12-12 05:25:42 +08:00
R600/SI: add post ISel folding for SI v2 Include immediate folding and SGPR limit handling for VOP3 instructions. v2: remove leftover hasExtraSrcRegAllocReq Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 176101
2013-02-27 01:52:23 +08:00
bool foldImm(SDValue &Operand, int32_t &Immediate,
bool &ScalarSlotUsed) const;
R600/SI: Add more special cases for opcodes to ensureSRegLimit() Also factor out the register class lookup to its own function. llvm-svn: 187830
2013-08-07 07:08:18 +08:00
const TargetRegisterClass *getRegClassForNode(SelectionDAG &DAG,
const SDValue &Op) const;
R600/SI: Make fitsRegClass() operands const Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 182282
2013-05-20 23:02:01 +08:00
bool fitsRegClass(SelectionDAG &DAG, const SDValue &Op,
unsigned RegClass) const;
Add LLVMContext argument to getSetCCResultType llvm-svn: 182180
2013-05-18 08:21:46 +08:00
void ensureSRegLimit(SelectionDAG &DAG, SDValue &Operand,
R600/SI: add post ISel folding for SI v2 Include immediate folding and SGPR limit handling for VOP3 instructions. v2: remove leftover hasExtraSrcRegAllocReq Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 176101
2013-02-27 01:52:23 +08:00
unsigned RegClass, bool &ScalarSlotUsed) const;
R600/SI: adjust writemask to only the used components Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 179165
2013-04-10 16:39:08 +08:00
SDNode *foldOperands(MachineSDNode *N, SelectionDAG &DAG) const;
void adjustWritemask(MachineSDNode *&N, SelectionDAG &DAG) const;
R600/SI: Adjust some instructions' out register class after ISel This is necessary to avoid generating VGPR to SGPR copies in some cases. llvm-svn: 183135
2013-06-04 01:39:58 +08:00
MachineSDNode *AdjustRegClass(MachineSDNode *N, SelectionDAG &DAG) const;
R600/SI: adjust writemask to only the used components Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 179165
2013-04-10 16:39:08 +08:00
R600/SI: Use v_cvt_f32_ubyte* instructions This eliminates extra extract instructions when loading an i8 vector to a float vector. llvm-svn: 210666
2014-06-12 01:50:44 +08:00
static SDValue performUCharToFloatCombine(SDNode *N,
DAGCombinerInfo &DCI);
Add R600 backend A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX llvm-svn: 169915
2012-12-12 05:25:42 +08:00
public:
SITargetLowering(TargetMachine &tm);
Add alignment value to allowsUnalignedMemoryAccess Rename to allowsMisalignedMemoryAccess. On R600, 8 and 16 byte accesses are mostly OK with 4-byte alignment, and don't need to be split into multiple accesses. Vector loads with an alignment of the element type are not uncommon in OpenCL code. llvm-svn: 214055
2014-07-28 01:46:40 +08:00
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS,
unsigned Align,
bool *IsFast) const override;
[codegen,aarch64] Add a target hook to the code generator to control vector type legalization strategies in a more fine grained manner, and change the legalization of several v1iN types and v1f32 to be widening rather than scalarization on AArch64. This fixes an assertion failure caused by scalarizing nodes like "v1i32 trunc v1i64". As v1i64 is legal it will fail to scalarize v1i32. This also provides a foundation for other targets to have more granular control over how vector types are legalized. Patch by Hao Liu, reviewed by Tim Northover. I'm committing it to allow some work to start taking place on top of this patch as it adds some really important hooks to the backend that I'd like to immediately start using. =] http://reviews.llvm.org/D4322 llvm-svn: 212242
2014-07-03 08:23:43 +08:00
TargetLoweringBase::LegalizeTypeAction
getPreferredVectorAction(EVT VT) const override;
R600/SI: add proper formal parameter handling for SI Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 176623
2013-03-07 17:03:52 +08:00
[C++11] Add 'override' keywords and remove 'virtual'. Additionally add 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. R600 edition llvm-svn: 207503
2014-04-29 15:57:24 +08:00
bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
Type *Ty) const override;
R600/SI: Implement shouldConvertConstantLoadToIntImm llvm-svn: 205244
2014-04-01 03:54:27 +08:00
R600/SI: add proper formal parameter handling for SI Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 176623
2013-03-07 17:03:52 +08:00
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins,
Track IR ordering of SelectionDAG nodes 2/4. Change SelectionDAG::getXXXNode() interfaces as well as call sites of these functions to pass in SDLoc instead of DebugLoc. llvm-svn: 182703
2013-05-25 10:42:55 +08:00
SDLoc DL, SelectionDAG &DAG,
[C++11] Add 'override' keywords and remove 'virtual'. Additionally add 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. R600 edition llvm-svn: 207503
2014-04-29 15:57:24 +08:00
SmallVectorImpl<SDValue> &InVals) const override;
R600/SI: add proper formal parameter handling for SI Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 176623
2013-03-07 17:03:52 +08:00
[C++11] Add 'override' keywords and remove 'virtual'. Additionally add 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. R600 edition llvm-svn: 207503
2014-04-29 15:57:24 +08:00
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr * MI,
MachineBasicBlock * BB) const override;
EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override;
MVT getScalarShiftAmountTy(EVT VT) const override;
bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override;
void AdjustInstrPostInstrSelection(MachineInstr *MI,
SDNode *Node) const override;
R600/SI: add post ISel folding for SI v2 Include immediate folding and SGPR limit handling for VOP3 instructions. v2: remove leftover hasExtraSrcRegAllocReq Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 176101
2013-02-27 01:52:23 +08:00
int32_t analyzeImmediate(const SDNode *N) const;
R600/SI: Add support for work item and work group intrinsics llvm-svn: 183138
2013-06-04 01:40:18 +08:00
SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC,
[C++11] Add 'override' keywords and remove 'virtual'. Additionally add 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. R600 edition llvm-svn: 207503
2014-04-29 15:57:24 +08:00
unsigned Reg, EVT VT) const override;
Add R600 backend A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX llvm-svn: 169915
2012-12-12 05:25:42 +08:00
};
} // End namespace llvm
#endif //SIISELLOWERING_H