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llvm-project/clang/test/CodeGen/builtins-ppc-htm.c

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Add Hardware Transactional Memory (HTM) Support This patch adds Hardware Transaction Memory (HTM) support supported by ISA 2.07 (POWER8). The intrinsic support is based on GCC one [1], with both 'PowerPC HTM Low Level Built-in Functions' and 'PowerPC HTM High Level Inline Functions' implemented. Along with builtins a new driver switch is added to enable/disable HTM instruction support (-mhtm) and a header with common definitions (mostly to parse the TFHAR register value). The HTM switch also sets a preprocessor builtin HTM. The HTM usage requires a recently newer kernel with PPC HTM enabled. Tested on powerpc64 and powerpc64le. This is send along a llvm patch to enabled the builtins and option switch. [1] https://gcc.gnu.org/onlinedocs/gcc/PowerPC-Hardware-Transactional-Memory-Built-in-Functions.html Phabricator Review: http://reviews.llvm.org/D8248 llvm-svn: 233205
2015-03-26 03:41:41 +08:00
// REQUIRES: powerpc-registered-target
Remove the -faltivec alias option and replace it with -maltivec everywhere. The alias was only ever used on darwin and had some issues there, and isn't used in practice much. Also fixes a problem with -mno-altivec not turning off -maltivec. Also add a diagnostic for faltivec/fno-altivec that directs users to use maltivec options and include the altivec.h file explicitly. llvm-svn: 298449
2017-03-22 06:06:18 +08:00
// RUN: %clang_cc1 -target-feature +altivec -target-feature +htm -triple powerpc64-unknown-unknown -emit-llvm %s -o - | FileCheck %s
Add Hardware Transactional Memory (HTM) Support This patch adds Hardware Transaction Memory (HTM) support supported by ISA 2.07 (POWER8). The intrinsic support is based on GCC one [1], with both 'PowerPC HTM Low Level Built-in Functions' and 'PowerPC HTM High Level Inline Functions' implemented. Along with builtins a new driver switch is added to enable/disable HTM instruction support (-mhtm) and a header with common definitions (mostly to parse the TFHAR register value). The HTM switch also sets a preprocessor builtin HTM. The HTM usage requires a recently newer kernel with PPC HTM enabled. Tested on powerpc64 and powerpc64le. This is send along a llvm patch to enabled the builtins and option switch. [1] https://gcc.gnu.org/onlinedocs/gcc/PowerPC-Hardware-Transactional-Memory-Built-in-Functions.html Phabricator Review: http://reviews.llvm.org/D8248 llvm-svn: 233205
2015-03-26 03:41:41 +08:00
void test1(long int *r, int code, long int *a, long int *b) {
Revert "[CodeGenModule] Assume dso_local for -fpic -fno-semantic-interposition" This reverts commit 789a46f2d742e11edaade28cb59a0f4d2a1d770e. Accidentally committed.
2020-02-04 02:09:39 +08:00
// CHECK-LABEL: define void @test1
Add Hardware Transactional Memory (HTM) Support This patch adds Hardware Transaction Memory (HTM) support supported by ISA 2.07 (POWER8). The intrinsic support is based on GCC one [1], with both 'PowerPC HTM Low Level Built-in Functions' and 'PowerPC HTM High Level Inline Functions' implemented. Along with builtins a new driver switch is added to enable/disable HTM instruction support (-mhtm) and a header with common definitions (mostly to parse the TFHAR register value). The HTM switch also sets a preprocessor builtin HTM. The HTM usage requires a recently newer kernel with PPC HTM enabled. Tested on powerpc64 and powerpc64le. This is send along a llvm patch to enabled the builtins and option switch. [1] https://gcc.gnu.org/onlinedocs/gcc/PowerPC-Hardware-Transactional-Memory-Built-in-Functions.html Phabricator Review: http://reviews.llvm.org/D8248 llvm-svn: 233205
2015-03-26 03:41:41 +08:00
r[0] = __builtin_tbegin (0);
// CHECK: @llvm.ppc.tbegin
r[1] = __builtin_tbegin (1);
// CHECK: @llvm.ppc.tbegin
r[2] = __builtin_tend (0);
// CHECK: @llvm.ppc.tend
r[3] = __builtin_tendall ();
// CHECK: @llvm.ppc.tendall
r[4] = __builtin_tabort (code);
// CHECK: @llvm.ppc.tabort
r[5] = __builtin_tabort (0x1);
// CHECK: @llvm.ppc.tabort
r[6] = __builtin_tabortdc (0xf, a[0], b[0]);
// CHECK: @llvm.ppc.tabortdc
r[7] = __builtin_tabortdci (0xf, a[1], 0x1);
// CHECK: @llvm.ppc.tabortdc
r[8] = __builtin_tabortwc (0xf, a[2], b[2]);
// CHECK: @llvm.ppc.tabortwc
r[9] = __builtin_tabortwci (0xf, a[3], 0x1);
// CHECK: @llvm.ppc.tabortwc
r[10] = __builtin_tcheck ();
// CHECK: @llvm.ppc.tcheck
r[11] = __builtin_trechkpt ();
// CHECK: @llvm.ppc.trechkpt
r[12] = __builtin_treclaim (0);
// CHECK: @llvm.ppc.treclaim
r[13] = __builtin_tresume ();
// CHECK: @llvm.ppc.tresume
r[14] = __builtin_tsuspend ();
// CHECK: @llvm.ppc.tsuspend
r[15] = __builtin_tsr (0);
// CHECK: @llvm.ppc.tsr
r[16] = __builtin_ttest ();
// CHECK: @llvm.ppc.ttest
r[17] = __builtin_get_texasr ();
// CHECK: @llvm.ppc.get.texasr
r[18] = __builtin_get_texasru ();
// CHECK: @llvm.ppc.get.texasru
r[19] = __builtin_get_tfhar ();
// CHECK: @llvm.ppc.get.tfhar
r[20] = __builtin_get_tfiar ();
// CHECK: @llvm.ppc.get.tfiar
__builtin_set_texasr (a[21]);
// CHECK: @llvm.ppc.set.texasr
__builtin_set_texasru (a[22]);
// CHECK: @llvm.ppc.set.texasru
__builtin_set_tfhar (a[23]);
// CHECK: @llvm.ppc.set.tfhar
__builtin_set_tfiar (a[24]);
// CHECK: @llvm.ppc.set.tfiar
}