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llvm-project/llvm/test/CodeGen/RISCV/zfh-half-intrinsics.ll

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[RISCV] Fix type in f16 and f64 version of lrint/llrint/lround/llround test cases. NFC Due to a copy/paste mistake we were always testing float. This required splitting up the f16 tests into separate files since we don't have an appropriate libcall to use when the types involved aren't legal.
2021-12-28 06:59:21 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
[RISCV] update zfh and zfhmin extention to v1.0 `zfh` and `zfhmin` have been ratified, with version 1.0. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D117098
2022-01-15 09:11:58 +08:00
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zfh \
[RISCV] Fix type in f16 and f64 version of lrint/llrint/lround/llround test cases. NFC Due to a copy/paste mistake we were always testing float. This required splitting up the f16 tests into separate files since we don't have an appropriate libcall to use when the types involved aren't legal.
2021-12-28 06:59:21 +08:00
; RUN: -verify-machineinstrs -target-abi ilp32f | \
; RUN: FileCheck -check-prefix=RV32IZFH %s
[RISCV] update zfh and zfhmin extention to v1.0 `zfh` and `zfhmin` have been ratified, with version 1.0. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D117098
2022-01-15 09:11:58 +08:00
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zfh \
[RISCV] Fix type in f16 and f64 version of lrint/llrint/lround/llround test cases. NFC Due to a copy/paste mistake we were always testing float. This required splitting up the f16 tests into separate files since we don't have an appropriate libcall to use when the types involved aren't legal.
2021-12-28 06:59:21 +08:00
; RUN: -verify-machineinstrs -target-abi lp64f | \
; RUN: FileCheck -check-prefix=RV64IZFH %s
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+d \
[RISCV] update zfh and zfhmin extention to v1.0 `zfh` and `zfhmin` have been ratified, with version 1.0. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D117098
2022-01-15 09:11:58 +08:00
; RUN: -mattr=+zfh -verify-machineinstrs -target-abi ilp32d | \
[RISCV] Fix type in f16 and f64 version of lrint/llrint/lround/llround test cases. NFC Due to a copy/paste mistake we were always testing float. This required splitting up the f16 tests into separate files since we don't have an appropriate libcall to use when the types involved aren't legal.
2021-12-28 06:59:21 +08:00
; RUN: FileCheck -check-prefix=RV32IDZFH %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+d \
[RISCV] update zfh and zfhmin extention to v1.0 `zfh` and `zfhmin` have been ratified, with version 1.0. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D117098
2022-01-15 09:11:58 +08:00
; RUN: -mattr=+zfh -verify-machineinstrs -target-abi lp64d | \
[RISCV] Fix type in f16 and f64 version of lrint/llrint/lround/llround test cases. NFC Due to a copy/paste mistake we were always testing float. This required splitting up the f16 tests into separate files since we don't have an appropriate libcall to use when the types involved aren't legal.
2021-12-28 06:59:21 +08:00
; RUN: FileCheck -check-prefix=RV64IDZFH %s
; These intrinsics require half to be a legal type.
declare iXLen @llvm.lrint.iXLen.f16(half)
define iXLen @lrint_f16(half %a) nounwind {
; RV32IZFH-LABEL: lrint_f16:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: fcvt.w.h a0, fa0
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: lrint_f16:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fcvt.l.h a0, fa0
; RV64IZFH-NEXT: ret
;
; RV32IDZFH-LABEL: lrint_f16:
; RV32IDZFH: # %bb.0:
; RV32IDZFH-NEXT: fcvt.w.h a0, fa0
; RV32IDZFH-NEXT: ret
;
; RV64IDZFH-LABEL: lrint_f16:
; RV64IDZFH: # %bb.0:
; RV64IDZFH-NEXT: fcvt.l.h a0, fa0
; RV64IDZFH-NEXT: ret
%1 = call iXLen @llvm.lrint.iXLen.f16(half %a)
ret iXLen %1
}
declare iXLen @llvm.lround.iXLen.f16(half)
define iXLen @lround_f16(half %a) nounwind {
; RV32IZFH-LABEL: lround_f16:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rmm
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: lround_f16:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rmm
; RV64IZFH-NEXT: ret
;
; RV32IDZFH-LABEL: lround_f16:
; RV32IDZFH: # %bb.0:
; RV32IDZFH-NEXT: fcvt.w.h a0, fa0, rmm
; RV32IDZFH-NEXT: ret
;
; RV64IDZFH-LABEL: lround_f16:
; RV64IDZFH: # %bb.0:
; RV64IDZFH-NEXT: fcvt.l.h a0, fa0, rmm
; RV64IDZFH-NEXT: ret
%1 = call iXLen @llvm.lround.iXLen.f16(half %a)
ret iXLen %1
}