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llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values.mir

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AMDGPU/GlobalISel: Make some G_MERGE_VALUEs legal llvm-svn: 327267
2018-03-12 21:35:43 +08:00
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
AMDGPU/GlobalISel: Add baseline, failing unmerge tests
2020-08-20 06:13:23 +08:00
# RUN: llc -mtriple=amdgcn-- -O0 -run-pass=legalizer -global-isel-abort=0 -o - %s | FileCheck %s
AMDGPU/GlobalISel: Make some G_MERGE_VALUEs legal llvm-svn: 327267
2018-03-12 21:35:43 +08:00
---
AMDGPU/GlobalISel: Fix some crashs in g_unmerge_values/g_merge_values This was crashing in the predicate function assuming the value is a vector. Copy more of what AArch64 uses. This probably needs more refinement later, but I don't exactly understand what it means in some cases, particularly since any legalization for these seems to be missing. llvm-svn: 351693
2019-01-21 02:40:36 +08:00
name: test_unmerge_s32_s64
AMDGPU/GlobalISel: Make some G_MERGE_VALUEs legal llvm-svn: 327267
2018-03-12 21:35:43 +08:00
body: |
bb.0:
AMDGPU/GlobalISel: Fix some crashs in g_unmerge_values/g_merge_values This was crashing in the predicate function assuming the value is a vector. Copy more of what AArch64 uses. This probably needs more refinement later, but I don't exactly understand what it means in some cases, particularly since any legalization for these seems to be missing. llvm-svn: 351693
2019-01-21 02:40:36 +08:00
; CHECK-LABEL: name: test_unmerge_s32_s64
AMDGPU/GlobalISel: Make some G_MERGE_VALUEs legal llvm-svn: 327267
2018-03-12 21:35:43 +08:00
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
AMDGPU: Regenerate some mir test checks with -NEXT
2021-12-18 23:07:00 +08:00
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C]](s64)
; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32)
; CHECK-NEXT: $vgpr1 = COPY [[UV1]](s32)
AMDGPU/GlobalISel: Make some G_MERGE_VALUEs legal llvm-svn: 327267
2018-03-12 21:35:43 +08:00
%0:_(s64) = G_CONSTANT i64 0
%1:_(s32), %2:_(s32) = G_UNMERGE_VALUES %0:_(s64)
$vgpr0 = COPY %1(s32)
AMDGPU/GlobalISel: Fix some crashs in g_unmerge_values/g_merge_values This was crashing in the predicate function assuming the value is a vector. Copy more of what AArch64 uses. This probably needs more refinement later, but I don't exactly understand what it means in some cases, particularly since any legalization for these seems to be missing. llvm-svn: 351693
2019-01-21 02:40:36 +08:00
$vgpr1 = COPY %2(s32)
...
---
name: test_unmerge_s32_v2s32
body: |
bb.0:
liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: test_unmerge_s32_v2s32
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
AMDGPU: Regenerate some mir test checks with -NEXT
2021-12-18 23:07:00 +08:00
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32)
; CHECK-NEXT: $vgpr21 = COPY [[UV1]](s32)
AMDGPU/GlobalISel: Fix some crashs in g_unmerge_values/g_merge_values This was crashing in the predicate function assuming the value is a vector. Copy more of what AArch64 uses. This probably needs more refinement later, but I don't exactly understand what it means in some cases, particularly since any legalization for these seems to be missing. llvm-svn: 351693
2019-01-21 02:40:36 +08:00
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
%1:_(s32), %2:_(s32) = G_UNMERGE_VALUES %0
$vgpr0 = COPY %1
$vgpr21= COPY %2
...
---
name: test_unmerge_s16_v2s16
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: test_unmerge_s16_v2s16
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
AMDGPU: Regenerate some mir test checks with -NEXT
2021-12-18 23:07:00 +08:00
; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; CHECK-NEXT: $vgpr0 = COPY [[BITCAST]](s32)
; CHECK-NEXT: $vgpr1 = COPY [[LSHR]](s32)
AMDGPU/GlobalISel: Fix some crashs in g_unmerge_values/g_merge_values This was crashing in the predicate function assuming the value is a vector. Copy more of what AArch64 uses. This probably needs more refinement later, but I don't exactly understand what it means in some cases, particularly since any legalization for these seems to be missing. llvm-svn: 351693
2019-01-21 02:40:36 +08:00
%0:_(<2 x s16>) = COPY $vgpr0
%1:_(s16), %2:_(s16) = G_UNMERGE_VALUES %0
%3:_(s32) = G_ANYEXT %1
%4:_(s32) = G_ANYEXT %2
$vgpr0 = COPY %3
$vgpr1 = COPY %4
...
---
name: test_unmerge_s16_v3s16
body: |
bb.0:
; CHECK-LABEL: name: test_unmerge_s16_v3s16
GlobalISel: Implement moreElementsVector for implicit_def llvm-svn: 353754
2019-02-12 06:00:39 +08:00
; CHECK: [[DEF:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
AMDGPU: Regenerate some mir test checks with -NEXT
2021-12-18 23:07:00 +08:00
; CHECK-NEXT: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[DEF]](<4 x s16>)
; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[UV]](<2 x s16>)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; CHECK-NEXT: $vgpr0 = COPY [[BITCAST]](s32)
; CHECK-NEXT: $vgpr1 = COPY [[LSHR]](s32)
; CHECK-NEXT: $vgpr2 = COPY [[BITCAST1]](s32)
AMDGPU/GlobalISel: Fix some crashs in g_unmerge_values/g_merge_values This was crashing in the predicate function assuming the value is a vector. Copy more of what AArch64 uses. This probably needs more refinement later, but I don't exactly understand what it means in some cases, particularly since any legalization for these seems to be missing. llvm-svn: 351693
2019-01-21 02:40:36 +08:00
%0:_(<3 x s16>) = G_IMPLICIT_DEF
%1:_(s16), %2:_(s16), %3:_(s16) = G_UNMERGE_VALUES %0
%4:_(s32) = G_ANYEXT %1
%5:_(s32) = G_ANYEXT %2
%6:_(s32) = G_ANYEXT %3
$vgpr0 = COPY %4
$vgpr1 = COPY %5
$vgpr2 = COPY %6
AMDGPU/GlobalISel: Make some G_MERGE_VALUEs legal llvm-svn: 327267
2018-03-12 21:35:43 +08:00
...
GlobalISel: Implement widenScalar for G_UNMERGE_VALUES For the scalar case only. Also move the similar G_MERGE_VALUES handling to a separate function and cleanup to make them look more similar. llvm-svn: 352979
2019-02-03 08:07:33 +08:00
---
GlobalISel: Lower scalarizing unmerge of a vector to shifts AMDGPU sometimes has legal s16 and <2 x s16> operations, but all registers are really 32-bit. An unmerge destination really should ben widened to a 32-bit register. If widening a scalarizing vector with a target size that matches the vector size, bitcast to integer and extract the relevant bits with shifts. I'm not sure if this is the right place for this. This could arguably be part of widenScalar for the result. I also have a growing feeling that we're missing a bitcast legalize action. llvm-svn: 367604
2019-08-02 03:10:05 +08:00
name: test_unmerge_s16_v4s16
body: |
bb.0:
liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: test_unmerge_s16_v4s16
; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
AMDGPU: Regenerate some mir test checks with -NEXT
2021-12-18 23:07:00 +08:00
; CHECK-NEXT: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[UV]](<2 x s16>)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; CHECK-NEXT: $vgpr0 = COPY [[BITCAST]](s32)
; CHECK-NEXT: $vgpr1 = COPY [[LSHR]](s32)
; CHECK-NEXT: $vgpr2 = COPY [[BITCAST1]](s32)
; CHECK-NEXT: $vgpr3 = COPY [[LSHR1]](s32)
GlobalISel: Lower scalarizing unmerge of a vector to shifts AMDGPU sometimes has legal s16 and <2 x s16> operations, but all registers are really 32-bit. An unmerge destination really should ben widened to a 32-bit register. If widening a scalarizing vector with a target size that matches the vector size, bitcast to integer and extract the relevant bits with shifts. I'm not sure if this is the right place for this. This could arguably be part of widenScalar for the result. I also have a growing feeling that we're missing a bitcast legalize action. llvm-svn: 367604
2019-08-02 03:10:05 +08:00
%0:_(<4 x s16>) = COPY $vgpr0_vgpr1
%1:_(s16), %2:_(s16), %3:_(s16), %4:_(s16) = G_UNMERGE_VALUES %0
%5:_(s32) = G_ANYEXT %1
%6:_(s32) = G_ANYEXT %2
%7:_(s32) = G_ANYEXT %3
%8:_(s32) = G_ANYEXT %4
$vgpr0 = COPY %5
$vgpr1 = COPY %6
$vgpr2 = COPY %7
$vgpr3 = COPY %8
...
---
name: test_unmerge_s16_v6s16
body: |
bb.0:
liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: test_unmerge_s16_v6s16
; CHECK: [[COPY:%[0-9]+]]:_(<6 x s16>) = COPY $vgpr0_vgpr1_vgpr2
AMDGPU: Regenerate some mir test checks with -NEXT
2021-12-18 23:07:00 +08:00
; CHECK-NEXT: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>), [[UV2:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<6 x s16>)
; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[UV]](<2 x s16>)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV2]](<2 x s16>)
; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; CHECK-NEXT: $vgpr0 = COPY [[BITCAST]](s32)
; CHECK-NEXT: $vgpr1 = COPY [[LSHR]](s32)
; CHECK-NEXT: $vgpr2 = COPY [[BITCAST1]](s32)
; CHECK-NEXT: $vgpr3 = COPY [[LSHR1]](s32)
; CHECK-NEXT: $vgpr4 = COPY [[BITCAST2]](s32)
; CHECK-NEXT: $vgpr5 = COPY [[LSHR2]](s32)
GlobalISel: Lower scalarizing unmerge of a vector to shifts AMDGPU sometimes has legal s16 and <2 x s16> operations, but all registers are really 32-bit. An unmerge destination really should ben widened to a 32-bit register. If widening a scalarizing vector with a target size that matches the vector size, bitcast to integer and extract the relevant bits with shifts. I'm not sure if this is the right place for this. This could arguably be part of widenScalar for the result. I also have a growing feeling that we're missing a bitcast legalize action. llvm-svn: 367604
2019-08-02 03:10:05 +08:00
%0:_(<6 x s16>) = COPY $vgpr0_vgpr1_vgpr2
%1:_(s16), %2:_(s16), %3:_(s16), %4:_(s16), %5:_(s16), %6:_(s16) = G_UNMERGE_VALUES %0
%7:_(s32) = G_ANYEXT %1
%8:_(s32) = G_ANYEXT %2
%9:_(s32) = G_ANYEXT %3
%10:_(s32) = G_ANYEXT %4
%11:_(s32) = G_ANYEXT %5
%12:_(s32) = G_ANYEXT %6
$vgpr0 = COPY %7
$vgpr1 = COPY %8
$vgpr2 = COPY %9
$vgpr3 = COPY %10
$vgpr4 = COPY %11
$vgpr5 = COPY %12
...
---
GlobalISel: Implement widenScalar for G_UNMERGE_VALUES For the scalar case only. Also move the similar G_MERGE_VALUES handling to a separate function and cleanup to make them look more similar. llvm-svn: 352979
2019-02-03 08:07:33 +08:00
name: test_unmerge_s8_s16
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: test_unmerge_s8_s16
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
AMDGPU: Regenerate some mir test checks with -NEXT
2021-12-18 23:07:00 +08:00
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
; CHECK-NEXT: $vgpr0 = COPY [[COPY]](s32)
; CHECK-NEXT: $vgpr1 = COPY [[LSHR]](s32)
GlobalISel: Implement widenScalar for G_UNMERGE_VALUES For the scalar case only. Also move the similar G_MERGE_VALUES handling to a separate function and cleanup to make them look more similar. llvm-svn: 352979
2019-02-03 08:07:33 +08:00
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0
%2:_(s8), %3:_(s8) = G_UNMERGE_VALUES %1
%4:_(s32) = G_ANYEXT %2
%5:_(s32) = G_ANYEXT %3
$vgpr0 = COPY %4
$vgpr1 = COPY %5
...
---
name: test_unmerge_s8_s32
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: test_unmerge_s8_s32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
AMDGPU: Regenerate some mir test checks with -NEXT
2021-12-18 23:07:00 +08:00
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C1]](s32)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)
; CHECK-NEXT: $vgpr0 = COPY [[COPY]](s32)
; CHECK-NEXT: $vgpr1 = COPY [[LSHR]](s32)
; CHECK-NEXT: $vgpr2 = COPY [[LSHR1]](s32)
; CHECK-NEXT: $vgpr3 = COPY [[LSHR2]](s32)
GlobalISel: Implement widenScalar for G_UNMERGE_VALUES For the scalar case only. Also move the similar G_MERGE_VALUES handling to a separate function and cleanup to make them look more similar. llvm-svn: 352979
2019-02-03 08:07:33 +08:00
%0:_(s32) = COPY $vgpr0
%1:_(s8), %2:_(s8), %3:_(s8), %4:_(s8) = G_UNMERGE_VALUES %0
%5:_(s32) = G_ANYEXT %1
%6:_(s32) = G_ANYEXT %2
%7:_(s32) = G_ANYEXT %3
%8:_(s32) = G_ANYEXT %4
$vgpr0 = COPY %5
$vgpr1 = COPY %6
$vgpr2 = COPY %7
$vgpr3 = COPY %8
...
AMDGPU/GlobalISel: Add some baseline tests for unmerge legalization
2020-01-21 21:18:39 +08:00
---
name: test_unmerge_s8_s48
body: |
bb.0:
liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: test_unmerge_s8_s48
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
AMDGPU: Regenerate some mir test checks with -NEXT
2021-12-18 23:07:00 +08:00
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C]](s32)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C2]]
; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[COPY1]](s32)
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY2]](s32)
; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C2]]
; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[C1]](s32)
; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32)
; CHECK-NEXT: $vgpr1 = COPY [[LSHR1]](s32)
; CHECK-NEXT: $vgpr2 = COPY [[LSHR]](s32)
; CHECK-NEXT: $vgpr3 = COPY [[LSHR2]](s32)
; CHECK-NEXT: $vgpr4 = COPY [[UV1]](s32)
; CHECK-NEXT: $vgpr5 = COPY [[LSHR3]](s32)
AMDGPU/GlobalISel: Add some baseline tests for unmerge legalization
2020-01-21 21:18:39 +08:00
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s48) = G_TRUNC %0
%2:_(s8), %3:_(s8), %4:_(s8), %5:_(s8), %6:_(s8), %7:_(s8) = G_UNMERGE_VALUES %1
%8:_(s32) = G_ANYEXT %2
%9:_(s32) = G_ANYEXT %3
%10:_(s32) = G_ANYEXT %4
%11:_(s32) = G_ANYEXT %5
%12:_(s32) = G_ANYEXT %6
%13:_(s32) = G_ANYEXT %7
$vgpr0 = COPY %8
$vgpr1 = COPY %9
$vgpr2 = COPY %10
$vgpr3 = COPY %11
$vgpr4 = COPY %12
$vgpr5 = COPY %13
...
---
name: test_unmerge_s16_s48
body: |
bb.0:
liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: test_unmerge_s16_s48
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
AMDGPU: Regenerate some mir test checks with -NEXT
2021-12-18 23:07:00 +08:00
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C]](s32)
; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32)
; CHECK-NEXT: $vgpr1 = COPY [[LSHR]](s32)
; CHECK-NEXT: $vgpr2 = COPY [[UV1]](s32)
AMDGPU/GlobalISel: Add some baseline tests for unmerge legalization
2020-01-21 21:18:39 +08:00
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s48) = G_TRUNC %0
%2:_(s16), %3:_(s16), %4:_(s16) = G_UNMERGE_VALUES %1
%5:_(s32) = G_ANYEXT %2
%6:_(s32) = G_ANYEXT %3
%7:_(s32) = G_ANYEXT %4
$vgpr0 = COPY %5
$vgpr1 = COPY %6
$vgpr2 = COPY %7
...
---
name: test_unmerge_s8_s64
body: |
bb.0:
liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: test_unmerge_s8_s64
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
AMDGPU: Regenerate some mir test checks with -NEXT
2021-12-18 23:07:00 +08:00
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C]](s32)
; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C]](s32)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C2]]
; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[COPY1]](s32)
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY2]](s32)
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C2]]
; CHECK-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[COPY3]](s32)
; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C2]]
; CHECK-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[C1]](s32)
; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32)
; CHECK-NEXT: $vgpr1 = COPY [[LSHR2]](s32)
; CHECK-NEXT: $vgpr2 = COPY [[LSHR]](s32)
; CHECK-NEXT: $vgpr3 = COPY [[LSHR3]](s32)
; CHECK-NEXT: $vgpr4 = COPY [[UV1]](s32)
; CHECK-NEXT: $vgpr5 = COPY [[LSHR4]](s32)
; CHECK-NEXT: $vgpr6 = COPY [[LSHR1]](s32)
; CHECK-NEXT: $vgpr7 = COPY [[LSHR5]](s32)
AMDGPU/GlobalISel: Add some baseline tests for unmerge legalization
2020-01-21 21:18:39 +08:00
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s8), %2:_(s8), %3:_(s8), %4:_(s8), %5:_(s8), %6:_(s8), %7:_(s8), %8:_(s8) = G_UNMERGE_VALUES %0
%10:_(s32) = G_ANYEXT %1
%11:_(s32) = G_ANYEXT %2
%12:_(s32) = G_ANYEXT %3
%13:_(s32) = G_ANYEXT %4
%14:_(s32) = G_ANYEXT %5
%15:_(s32) = G_ANYEXT %6
%16:_(s32) = G_ANYEXT %7
%17:_(s32) = G_ANYEXT %8
$vgpr0 = COPY %10
$vgpr1 = COPY %11
$vgpr2 = COPY %12
$vgpr3 = COPY %13
$vgpr4 = COPY %14
$vgpr5 = COPY %15
$vgpr6 = COPY %16
$vgpr7 = COPY %17
...
---
name: test_unmerge_s8_p1
body: |
bb.0:
liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: test_unmerge_s8_p1
; CHECK: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
AMDGPU: Regenerate some mir test checks with -NEXT
2021-12-18 23:07:00 +08:00
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](p1)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C]](s32)
; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C]](s32)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C2]]
; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[COPY1]](s32)
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY2]](s32)
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C2]]
; CHECK-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[COPY3]](s32)
; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C2]]
; CHECK-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[C1]](s32)
; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32)
; CHECK-NEXT: $vgpr1 = COPY [[LSHR2]](s32)
; CHECK-NEXT: $vgpr2 = COPY [[LSHR]](s32)
; CHECK-NEXT: $vgpr3 = COPY [[LSHR3]](s32)
; CHECK-NEXT: $vgpr4 = COPY [[UV1]](s32)
; CHECK-NEXT: $vgpr5 = COPY [[LSHR4]](s32)
; CHECK-NEXT: $vgpr6 = COPY [[LSHR1]](s32)
; CHECK-NEXT: $vgpr7 = COPY [[LSHR5]](s32)
AMDGPU/GlobalISel: Add some baseline tests for unmerge legalization
2020-01-21 21:18:39 +08:00
%0:_(p1) = COPY $vgpr0_vgpr1
%1:_(s8), %2:_(s8), %3:_(s8), %4:_(s8), %5:_(s8), %6:_(s8), %7:_(s8), %8:_(s8) = G_UNMERGE_VALUES %0
%10:_(s32) = G_ANYEXT %1
%11:_(s32) = G_ANYEXT %2
%12:_(s32) = G_ANYEXT %3
%13:_(s32) = G_ANYEXT %4
%14:_(s32) = G_ANYEXT %5
%15:_(s32) = G_ANYEXT %6
%16:_(s32) = G_ANYEXT %7
%17:_(s32) = G_ANYEXT %8
$vgpr0 = COPY %10
$vgpr1 = COPY %11
$vgpr2 = COPY %12
$vgpr3 = COPY %13
$vgpr4 = COPY %14
$vgpr5 = COPY %15
$vgpr6 = COPY %16
$vgpr7 = COPY %17
...
GlobalISel: Support widening unmerge results with pointer source
2020-01-22 00:12:36 +08:00
---
name: test_unmerge_s4_p1
body: |
bb.0:
liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: test_unmerge_s4_p1
; CHECK: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
AMDGPU: Regenerate some mir test checks with -NEXT
2021-12-18 23:07:00 +08:00
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](p1)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C]](s32)
; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C]](s32)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C2]]
; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[COPY1]](s32)
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C2]]
; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY2]](s32)
; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C2]]
; CHECK-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[COPY3]](s32)
; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
; CHECK-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[COPY4]](s32)
; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
; CHECK-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[AND4]], [[COPY5]](s32)
; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
; CHECK-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[AND5]], [[COPY6]](s32)
; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C2]]
; CHECK-NEXT: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[COPY7]](s32)
; CHECK-NEXT: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; CHECK-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C2]]
; CHECK-NEXT: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[AND7]], [[COPY8]](s32)
; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
; CHECK-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C2]]
; CHECK-NEXT: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[AND8]], [[COPY9]](s32)
; CHECK-NEXT: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C2]]
; CHECK-NEXT: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[AND9]], [[C1]](s32)
; CHECK-NEXT: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C2]]
; CHECK-NEXT: [[LSHR12:%[0-9]+]]:_(s32) = G_LSHR [[AND10]], [[C3]](s32)
; CHECK-NEXT: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C2]]
; CHECK-NEXT: [[LSHR13:%[0-9]+]]:_(s32) = G_LSHR [[AND11]], [[C4]](s32)
; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32)
; CHECK-NEXT: $vgpr1 = COPY [[LSHR2]](s32)
; CHECK-NEXT: $vgpr2 = COPY [[LSHR3]](s32)
; CHECK-NEXT: $vgpr3 = COPY [[LSHR4]](s32)
; CHECK-NEXT: $vgpr4 = COPY [[LSHR]](s32)
; CHECK-NEXT: $vgpr5 = COPY [[LSHR5]](s32)
; CHECK-NEXT: $vgpr6 = COPY [[LSHR6]](s32)
; CHECK-NEXT: $vgpr7 = COPY [[LSHR7]](s32)
; CHECK-NEXT: $vgpr8 = COPY [[UV1]](s32)
; CHECK-NEXT: $vgpr9 = COPY [[LSHR8]](s32)
; CHECK-NEXT: $vgpr10 = COPY [[LSHR9]](s32)
; CHECK-NEXT: $vgpr11 = COPY [[LSHR10]](s32)
; CHECK-NEXT: $vgpr12 = COPY [[LSHR1]](s32)
; CHECK-NEXT: $vgpr13 = COPY [[LSHR11]](s32)
; CHECK-NEXT: $vgpr14 = COPY [[LSHR12]](s32)
; CHECK-NEXT: $vgpr15 = COPY [[LSHR13]](s32)
GlobalISel: Support widening unmerge results with pointer source
2020-01-22 00:12:36 +08:00
%0:_(p1) = COPY $vgpr0_vgpr1
%1:_(s4), %2:_(s4), %3:_(s4), %4:_(s4), %5:_(s4), %6:_(s4), %7:_(s4), %8:_(s4), %9:_(s4), %10:_(s4), %11:_(s4), %12:_(s4), %13:_(s4), %14:_(s4), %15:_(s4), %16:_(s4) = G_UNMERGE_VALUES %0
%17:_(s32) = G_ANYEXT %1
%18:_(s32) = G_ANYEXT %2
%19:_(s32) = G_ANYEXT %3
%20:_(s32) = G_ANYEXT %4
%21:_(s32) = G_ANYEXT %5
%22:_(s32) = G_ANYEXT %6
%23:_(s32) = G_ANYEXT %7
%24:_(s32) = G_ANYEXT %8
%25:_(s32) = G_ANYEXT %9
%26:_(s32) = G_ANYEXT %10
%27:_(s32) = G_ANYEXT %11
%28:_(s32) = G_ANYEXT %12
%29:_(s32) = G_ANYEXT %13
%30:_(s32) = G_ANYEXT %14
%31:_(s32) = G_ANYEXT %15
%32:_(s32) = G_ANYEXT %16
$vgpr0 = COPY %17
$vgpr1 = COPY %18
$vgpr2 = COPY %19
$vgpr3 = COPY %20
$vgpr4 = COPY %21
$vgpr5 = COPY %22
$vgpr6 = COPY %23
$vgpr7 = COPY %24
$vgpr8 = COPY %25
$vgpr9 = COPY %26
$vgpr10 = COPY %27
$vgpr11 = COPY %28
$vgpr12 = COPY %29
$vgpr13 = COPY %30
$vgpr14 = COPY %31
$vgpr15 = COPY %32
...
---
name: test_unmerge_s16_p1
body: |
bb.0:
liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: test_unmerge_s16_p1
; CHECK: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
AMDGPU: Regenerate some mir test checks with -NEXT
2021-12-18 23:07:00 +08:00
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](p1)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C]](s32)
; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C]](s32)
; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32)
; CHECK-NEXT: $vgpr1 = COPY [[LSHR]](s32)
; CHECK-NEXT: $vgpr2 = COPY [[UV1]](s32)
; CHECK-NEXT: $vgpr3 = COPY [[LSHR1]](s32)
GlobalISel: Support widening unmerge results with pointer source
2020-01-22 00:12:36 +08:00
%0:_(p1) = COPY $vgpr0_vgpr1
%1:_(s16), %2:_(s16), %3:_(s16), %4:_(s16) = G_UNMERGE_VALUES %0
%5:_(s32) = G_ANYEXT %1
%6:_(s32) = G_ANYEXT %2
%7:_(s32) = G_ANYEXT %3
%8:_(s32) = G_ANYEXT %4
$vgpr0 = COPY %5
$vgpr1 = COPY %6
$vgpr2 = COPY %7
$vgpr3 = COPY %8
...
---
name: test_unmerge_s32_p1
body: |
bb.0:
liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: test_unmerge_s32_p1
; CHECK: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
AMDGPU: Regenerate some mir test checks with -NEXT
2021-12-18 23:07:00 +08:00
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](p1)
; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32)
; CHECK-NEXT: $vgpr1 = COPY [[UV1]](s32)
GlobalISel: Support widening unmerge results with pointer source
2020-01-22 00:12:36 +08:00
%0:_(p1) = COPY $vgpr0_vgpr1
%1:_(s32), %2:_(s32) = G_UNMERGE_VALUES %0
$vgpr0 = COPY %1
$vgpr1 = COPY %2
...
GlobalISel: Implement widenScalar for G_UNMERGE_VALUES For the scalar case only. Also move the similar G_MERGE_VALUES handling to a separate function and cleanup to make them look more similar. llvm-svn: 352979
2019-02-03 08:07:33 +08:00
---
name: test_unmerge_s16_s32
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: test_unmerge_s16_s32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
AMDGPU: Regenerate some mir test checks with -NEXT
2021-12-18 23:07:00 +08:00
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
; CHECK-NEXT: $vgpr0 = COPY [[COPY]](s32)
; CHECK-NEXT: $vgpr1 = COPY [[LSHR]](s32)
GlobalISel: Implement widenScalar for G_UNMERGE_VALUES For the scalar case only. Also move the similar G_MERGE_VALUES handling to a separate function and cleanup to make them look more similar. llvm-svn: 352979
2019-02-03 08:07:33 +08:00
%0:_(s32) = COPY $vgpr0
%1:_(s16), %2:_(s16) = G_UNMERGE_VALUES %0
GlobalISel: Support widening unmerge results with pointer source
2020-01-22 00:12:36 +08:00
%3:_(s32) = G_ANYEXT %1
%4:_(s32) = G_ANYEXT %2
$vgpr0 = COPY %3
$vgpr1 = COPY %4
...
---
name: test_unmerge_s16_p3
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: test_unmerge_s16_p3
; CHECK: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
AMDGPU: Regenerate some mir test checks with -NEXT
2021-12-18 23:07:00 +08:00
; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[COPY]](p3)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[PTRTOINT]], [[C]](s32)
; CHECK-NEXT: $vgpr0 = COPY [[PTRTOINT]](s32)
; CHECK-NEXT: $vgpr1 = COPY [[LSHR]](s32)
GlobalISel: Support widening unmerge results with pointer source
2020-01-22 00:12:36 +08:00
%0:_(p3) = COPY $vgpr0
%1:_(s16), %2:_(s16) = G_UNMERGE_VALUES %0
GlobalISel: Implement widenScalar for G_UNMERGE_VALUES For the scalar case only. Also move the similar G_MERGE_VALUES handling to a separate function and cleanup to make them look more similar. llvm-svn: 352979
2019-02-03 08:07:33 +08:00
%3:_(s32) = G_ANYEXT %1
%4:_(s32) = G_ANYEXT %2
$vgpr0 = COPY %3
$vgpr1 = COPY %4
...
AMDGPU/GlobalISel: Add a testcase for G_UNMERGE_VALUES legalization I had a note that this doesn't work, but it seems to now.
2020-03-25 09:52:03 +08:00
---
name: test_unmerge_s8_p3
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: test_unmerge_s8_p3
; CHECK: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
AMDGPU: Regenerate some mir test checks with -NEXT
2021-12-18 23:07:00 +08:00
; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[COPY]](p3)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[PTRTOINT]], [[C]](s32)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[PTRTOINT]], [[C1]](s32)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[PTRTOINT]], [[C2]](s32)
; CHECK-NEXT: $vgpr0 = COPY [[PTRTOINT]](s32)
; CHECK-NEXT: $vgpr1 = COPY [[LSHR]](s32)
; CHECK-NEXT: $vgpr2 = COPY [[LSHR1]](s32)
; CHECK-NEXT: $vgpr3 = COPY [[LSHR2]](s32)
AMDGPU/GlobalISel: Add a testcase for G_UNMERGE_VALUES legalization I had a note that this doesn't work, but it seems to now.
2020-03-25 09:52:03 +08:00
%0:_(p3) = COPY $vgpr0
%1:_(s8), %2:_(s8), %3:_(s8), %4:_(s8) = G_UNMERGE_VALUES %0
%5:_(s32) = G_ANYEXT %1
%6:_(s32) = G_ANYEXT %2
%7:_(s32) = G_ANYEXT %3
%8:_(s32) = G_ANYEXT %4
$vgpr0 = COPY %5
$vgpr1 = COPY %6
$vgpr2 = COPY %7
$vgpr3 = COPY %8
...
GlobalISel: Implement widenScalar for G_UNMERGE_VALUES For the scalar case only. Also move the similar G_MERGE_VALUES handling to a separate function and cleanup to make them look more similar. llvm-svn: 352979
2019-02-03 08:07:33 +08:00
---
name: test_unmerge_s16_s64
body: |
bb.0:
liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: test_unmerge_s16_s64
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
AMDGPU: Regenerate some mir test checks with -NEXT
2021-12-18 23:07:00 +08:00
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C]](s32)
; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C]](s32)
; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32)
; CHECK-NEXT: $vgpr1 = COPY [[LSHR]](s32)
; CHECK-NEXT: $vgpr2 = COPY [[UV1]](s32)
; CHECK-NEXT: $vgpr3 = COPY [[LSHR1]](s32)
GlobalISel: Implement widenScalar for G_UNMERGE_VALUES For the scalar case only. Also move the similar G_MERGE_VALUES handling to a separate function and cleanup to make them look more similar. llvm-svn: 352979
2019-02-03 08:07:33 +08:00
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s16), %2:_(s16), %3:_(s16), %4:_(s16) = G_UNMERGE_VALUES %0
%5:_(s32) = G_ANYEXT %1
%6:_(s32) = G_ANYEXT %2
%7:_(s32) = G_ANYEXT %3
%8:_(s32) = G_ANYEXT %4
$vgpr0 = COPY %5
$vgpr1 = COPY %6
$vgpr2 = COPY %7
$vgpr3 = COPY %8
...
---
name: test_unmerge_s1_s3
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: test_unmerge_s1_s3
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
AMDGPU: Regenerate some mir test checks with -NEXT
2021-12-18 23:07:00 +08:00
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C1]](s32)
; CHECK-NEXT: $vgpr0 = COPY [[COPY]](s32)
; CHECK-NEXT: $vgpr1 = COPY [[LSHR]](s32)
; CHECK-NEXT: $vgpr2 = COPY [[LSHR1]](s32)
GlobalISel: Implement widenScalar for G_UNMERGE_VALUES For the scalar case only. Also move the similar G_MERGE_VALUES handling to a separate function and cleanup to make them look more similar. llvm-svn: 352979
2019-02-03 08:07:33 +08:00
%0:_(s32) = COPY $vgpr0
%1:_(s3) = G_TRUNC %0
%2:_(s1), %3:_(s1), %4:_(s1) = G_UNMERGE_VALUES %1
%5:_(s32) = G_ANYEXT %2
%6:_(s32) = G_ANYEXT %3
%7:_(s32) = G_ANYEXT %4
$vgpr0 = COPY %5
$vgpr1 = COPY %6
$vgpr2 = COPY %7
...
---
name: test_unmerge_s1_s8
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: test_unmerge_s1_s8
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
AMDGPU: Regenerate some mir test checks with -NEXT
2021-12-18 23:07:00 +08:00
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C1]](s32)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C3]](s32)
; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
; CHECK-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C4]](s32)
; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 6
; CHECK-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C5]](s32)
; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
; CHECK-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C6]](s32)
; CHECK-NEXT: $vgpr0 = COPY [[COPY]](s32)
; CHECK-NEXT: $vgpr1 = COPY [[LSHR]](s32)
; CHECK-NEXT: $vgpr2 = COPY [[LSHR1]](s32)
; CHECK-NEXT: $vgpr3 = COPY [[LSHR2]](s32)
; CHECK-NEXT: $vgpr4 = COPY [[LSHR3]](s32)
; CHECK-NEXT: $vgpr5 = COPY [[LSHR4]](s32)
; CHECK-NEXT: $vgpr6 = COPY [[LSHR5]](s32)
; CHECK-NEXT: $vgpr7 = COPY [[LSHR6]](s32)
GlobalISel: Implement widenScalar for G_UNMERGE_VALUES For the scalar case only. Also move the similar G_MERGE_VALUES handling to a separate function and cleanup to make them look more similar. llvm-svn: 352979
2019-02-03 08:07:33 +08:00
%0:_(s32) = COPY $vgpr0
%1:_(s8) = G_TRUNC %0
%2:_(s1), %3:_(s1), %4:_(s1), %5:_(s1), %6:_(s1), %7:_(s1), %8:_(s1), %9:_(s1) = G_UNMERGE_VALUES %1
%10:_(s32) = G_ANYEXT %2
%11:_(s32) = G_ANYEXT %3
%12:_(s32) = G_ANYEXT %4
%13:_(s32) = G_ANYEXT %5
%14:_(s32) = G_ANYEXT %6
%15:_(s32) = G_ANYEXT %7
%16:_(s32) = G_ANYEXT %8
%17:_(s32) = G_ANYEXT %9
$vgpr0 = COPY %10
$vgpr1 = COPY %11
$vgpr2 = COPY %12
$vgpr3 = COPY %13
$vgpr4 = COPY %14
$vgpr5 = COPY %15
$vgpr6 = COPY %16
$vgpr7 = COPY %17
...
AMDGPU/GlobalISel: Make some large merges legal We allow up to 1024-bit registers, so we should support merges all the way to the maximum.
2020-03-16 22:42:15 +08:00
---
name: test_unmerge_s128_v2s128
body: |
bb.0:
liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; CHECK-LABEL: name: test_unmerge_s128_v2s128
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s128>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
AMDGPU: Regenerate some mir test checks with -NEXT
2021-12-18 23:07:00 +08:00
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s128), [[UV1:%[0-9]+]]:_(s128) = G_UNMERGE_VALUES [[COPY]](<2 x s128>)
; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[UV]](s128)
; CHECK-NEXT: $vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[UV1]](s128)
AMDGPU/GlobalISel: Make some large merges legal We allow up to 1024-bit registers, so we should support merges all the way to the maximum.
2020-03-16 22:42:15 +08:00
%0:_(<2 x s128>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
%1:_(s128), %2:_(s128) = G_UNMERGE_VALUES %0
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %1
$vgpr4_vgpr5_vgpr6_vgpr7 = COPY %2
...
---
name: test_unmerge_s128_s256
body: |
bb.0:
liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; CHECK-LABEL: name: test_unmerge_s128_s256
; CHECK: [[COPY:%[0-9]+]]:_(s256) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
AMDGPU: Regenerate some mir test checks with -NEXT
2021-12-18 23:07:00 +08:00
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s128), [[UV1:%[0-9]+]]:_(s128) = G_UNMERGE_VALUES [[COPY]](s256)
; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[UV]](s128)
; CHECK-NEXT: $vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[UV1]](s128)
AMDGPU/GlobalISel: Make some large merges legal We allow up to 1024-bit registers, so we should support merges all the way to the maximum.
2020-03-16 22:42:15 +08:00
%0:_(s256) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
%1:_(s128), %2:_(s128) = G_UNMERGE_VALUES %0
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %1
$vgpr4_vgpr5_vgpr6_vgpr7 = COPY %2
...
---
name: test_unmerge_s256_s512
body: |
bb.0:
liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; CHECK-LABEL: name: test_unmerge_s256_s512
; CHECK: [[COPY:%[0-9]+]]:_(s512) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
AMDGPU: Regenerate some mir test checks with -NEXT
2021-12-18 23:07:00 +08:00
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s256), [[UV1:%[0-9]+]]:_(s256) = G_UNMERGE_VALUES [[COPY]](s512)
; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[UV]](s256)
; CHECK-NEXT: $vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY [[UV1]](s256)
AMDGPU/GlobalISel: Make some large merges legal We allow up to 1024-bit registers, so we should support merges all the way to the maximum.
2020-03-16 22:42:15 +08:00
%0:_(s512) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
%1:_(s256), %2:_(s256) = G_UNMERGE_VALUES %0
$vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY %1
$vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY %2
...
---
name: test_unmerge_s256_v2s256
body: |
bb.0:
liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; CHECK-LABEL: name: test_unmerge_s256_v2s256
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s256>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
AMDGPU: Regenerate some mir test checks with -NEXT
2021-12-18 23:07:00 +08:00
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s256), [[UV1:%[0-9]+]]:_(s256) = G_UNMERGE_VALUES [[COPY]](<2 x s256>)
; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[UV]](s256)
; CHECK-NEXT: $vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY [[UV1]](s256)
AMDGPU/GlobalISel: Make some large merges legal We allow up to 1024-bit registers, so we should support merges all the way to the maximum.
2020-03-16 22:42:15 +08:00
%0:_(<2 x s256>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
%1:_(s256), %2:_(s256) = G_UNMERGE_VALUES %0
$vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY %1
$vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY %2
...
---
name: test_unmerge_s512_s1024
body: |
bb.0:
liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; CHECK-LABEL: name: test_unmerge_s512_s1024
; CHECK: [[COPY:%[0-9]+]]:_(s1024) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
AMDGPU: Regenerate some mir test checks with -NEXT
2021-12-18 23:07:00 +08:00
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s512), [[UV1:%[0-9]+]]:_(s512) = G_UNMERGE_VALUES [[COPY]](s1024)
; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY [[UV]](s512)
; CHECK-NEXT: $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 = COPY [[UV1]](s512)
AMDGPU/GlobalISel: Make some large merges legal We allow up to 1024-bit registers, so we should support merges all the way to the maximum.
2020-03-16 22:42:15 +08:00
%0:_(s1024) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
%1:_(s512), %2:_(s512) = G_UNMERGE_VALUES %0
$vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY %1
$vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 = COPY %2
...
---
name: test_unmerge_s512_v2s512
body: |
bb.0:
liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; CHECK-LABEL: name: test_unmerge_s512_v2s512
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s512>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
AMDGPU: Regenerate some mir test checks with -NEXT
2021-12-18 23:07:00 +08:00
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s512), [[UV1:%[0-9]+]]:_(s512) = G_UNMERGE_VALUES [[COPY]](<2 x s512>)
; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY [[UV]](s512)
; CHECK-NEXT: $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 = COPY [[UV1]](s512)
AMDGPU/GlobalISel: Make some large merges legal We allow up to 1024-bit registers, so we should support merges all the way to the maximum.
2020-03-16 22:42:15 +08:00
%0:_(<2 x s512>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
%1:_(s512), %2:_(s512) = G_UNMERGE_VALUES %0
$vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY %1
$vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 = COPY %2
...
GlobalISel: Combine G_UNMERGE_VALUES with G_TRUNC G_BITCAST can be lowered with a pair of G_UNMERGE_VALUES and G_MERGE_VALUES with different types, but G_UNMERGE_VALUES of a vector can also be implemented with a bitcast to a scalar, which introduces the possibility for infinite loops. Try to eliminate an illegal source register type in the artifact combiner to avoid this from happening. Avoids infinite looping in the legalizer in a future patch which allows lowering G_UNMERGE_VALUES of a vector source with a G_BITCAST.
2020-04-05 03:07:28 +08:00
---
name: test_unmerge_v2s1
body: |
bb.0:
; CHECK-LABEL: name: test_unmerge_v2s1
; CHECK: [[DEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
AMDGPU: Regenerate some mir test checks with -NEXT
2021-12-18 23:07:00 +08:00
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](<2 x s32>)
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[UV]](s32)
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s1) = G_TRUNC [[UV1]](s32)
; CHECK-NEXT: S_NOP 0, implicit [[TRUNC]](s1)
; CHECK-NEXT: S_NOP 0, implicit [[TRUNC1]](s1)
GlobalISel: Combine G_UNMERGE_VALUES with G_TRUNC G_BITCAST can be lowered with a pair of G_UNMERGE_VALUES and G_MERGE_VALUES with different types, but G_UNMERGE_VALUES of a vector can also be implemented with a bitcast to a scalar, which introduces the possibility for infinite loops. Try to eliminate an illegal source register type in the artifact combiner to avoid this from happening. Avoids infinite looping in the legalizer in a future patch which allows lowering G_UNMERGE_VALUES of a vector source with a G_BITCAST.
2020-04-05 03:07:28 +08:00
%0:_(<2 x s1>) = G_IMPLICIT_DEF
%1:_(s1), %2:_(s1) = G_UNMERGE_VALUES %0
S_NOP 0, implicit %1
S_NOP 0, implicit %2
...
GlobalISel: Handle more cases in lowerUnmergeValues Handle scalar sources, as well as vectors.
2020-03-30 06:04:53 +08:00
[AMDGPU] Fix inconsistent ---/... in MIR tests and regenerate checks In some cases the lack of --- or ... confused update_mir_test_checks.py into not adding any checks for a function.
2021-04-30 20:42:45 +08:00
---
GlobalISel: Handle more cases in lowerUnmergeValues Handle scalar sources, as well as vectors.
2020-03-30 06:04:53 +08:00
name: test_unmerge_s8_v4s8
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: test_unmerge_s8_v4s8
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
AMDGPU: Regenerate some mir test checks with -NEXT
2021-12-18 23:07:00 +08:00
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C1]](s32)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)
; CHECK-NEXT: $vgpr0 = COPY [[COPY]](s32)
; CHECK-NEXT: $vgpr1 = COPY [[LSHR]](s32)
; CHECK-NEXT: $vgpr2 = COPY [[LSHR1]](s32)
; CHECK-NEXT: $vgpr3 = COPY [[LSHR2]](s32)
GlobalISel: Handle more cases in lowerUnmergeValues Handle scalar sources, as well as vectors.
2020-03-30 06:04:53 +08:00
%0:_(s32) = COPY $vgpr0
%1:_(<4 x s8>) = G_BITCAST %0
%2:_(s8), %3:_(s8), %4:_(s8), %5:_(s8) = G_UNMERGE_VALUES %1
%6:_(s32) = G_ANYEXT %2
%7:_(s32) = G_ANYEXT %3
%8:_(s32) = G_ANYEXT %4
%9:_(s32) = G_ANYEXT %5
$vgpr0 = COPY %6
$vgpr1 = COPY %7
$vgpr2 = COPY %8
$vgpr3 = COPY %9
...
---
name: test_unmerge_s8_v3s8
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: test_unmerge_s8_v3s8
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
AMDGPU: Regenerate some mir test checks with -NEXT
2021-12-18 23:07:00 +08:00
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C1]](s32)
; CHECK-NEXT: $vgpr0 = COPY [[COPY]](s32)
; CHECK-NEXT: $vgpr1 = COPY [[LSHR]](s32)
; CHECK-NEXT: $vgpr2 = COPY [[LSHR1]](s32)
GlobalISel: Handle more cases in lowerUnmergeValues Handle scalar sources, as well as vectors.
2020-03-30 06:04:53 +08:00
%0:_(s32) = COPY $vgpr0
%1:_(s24) = G_TRUNC %0
%2:_(<3 x s8>) = G_BITCAST %1
%3:_(s8), %4:_(s8), %5:_(s8) = G_UNMERGE_VALUES %2
%6:_(s32) = G_ANYEXT %3
%7:_(s32) = G_ANYEXT %4
%8:_(s32) = G_ANYEXT %5
$vgpr0 = COPY %6
$vgpr1 = COPY %7
$vgpr2 = COPY %8
...
---
name: test_unmerge_s8_v2s8
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: test_unmerge_s8_v2s8
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
AMDGPU: Regenerate some mir test checks with -NEXT
2021-12-18 23:07:00 +08:00
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
; CHECK-NEXT: $vgpr0 = COPY [[COPY]](s32)
; CHECK-NEXT: $vgpr1 = COPY [[LSHR]](s32)
GlobalISel: Handle more cases in lowerUnmergeValues Handle scalar sources, as well as vectors.
2020-03-30 06:04:53 +08:00
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0
%2:_(<2 x s8>) = G_BITCAST %1
%3:_(s8), %4:_(s8) = G_UNMERGE_VALUES %2
%5:_(s32) = G_ANYEXT %3
%6:_(s32) = G_ANYEXT %4
$vgpr0 = COPY %5
$vgpr1 = COPY %6
...
AMDGPU/GlobalISel: Ensure subreg is valid when selecting G_UNMERGE_VALUES Fixes verifier error with SGPR unmerges with 96-bit result types.
2020-08-04 21:19:43 +08:00
---
name: test_unmerge_v3s32_v12s32
body: |
bb.0:
liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5, $vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11
; CHECK-LABEL: name: test_unmerge_v3s32_v12s32
; CHECK: [[COPY:%[0-9]+]]:_(<6 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5
AMDGPU: Regenerate some mir test checks with -NEXT
2021-12-18 23:07:00 +08:00
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<6 x s32>) = COPY $vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11
; CHECK-NEXT: [[UV:%[0-9]+]]:_(<3 x s32>), [[UV1:%[0-9]+]]:_(<3 x s32>) = G_UNMERGE_VALUES [[COPY]](<6 x s32>)
; CHECK-NEXT: [[UV2:%[0-9]+]]:_(<3 x s32>), [[UV3:%[0-9]+]]:_(<3 x s32>) = G_UNMERGE_VALUES [[COPY1]](<6 x s32>)
; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[UV]](<3 x s32>)
; CHECK-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[UV1]](<3 x s32>)
; CHECK-NEXT: $vgpr6_vgpr7_vgpr8 = COPY [[UV2]](<3 x s32>)
; CHECK-NEXT: $vgpr9_vgpr10_vgpr11 = COPY [[UV3]](<3 x s32>)
AMDGPU/GlobalISel: Ensure subreg is valid when selecting G_UNMERGE_VALUES Fixes verifier error with SGPR unmerges with 96-bit result types.
2020-08-04 21:19:43 +08:00
%0:_(<6 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5
%1:_(<6 x s32>) = COPY $vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11
%2:_(<12 x s32>) = G_CONCAT_VECTORS %0, %1
%3:_(<3 x s32>), %4:_(<3 x s32>), %5:_(<3 x s32>), %6:_(<3 x s32>) = G_UNMERGE_VALUES %2
$vgpr0_vgpr1_vgpr2 = COPY %3
$vgpr3_vgpr4_vgpr5 = COPY %4
$vgpr6_vgpr7_vgpr8 = COPY %5
$vgpr9_vgpr10_vgpr11 = COPY %6
...
AMDGPU/GlobalISel: Add baseline, failing unmerge tests
2020-08-20 06:13:23 +08:00
---
name: test_unmerge_v3s8_v12s8
body: |
bb.0:
liveins: $vgpr0_vgpr1_vgpr2
; CHECK-LABEL: name: test_unmerge_v3s8_v12s8
; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
AMDGPU: Regenerate some mir test checks with -NEXT
2021-12-18 23:07:00 +08:00
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C]](s32)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C1]](s32)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C2]](s32)
; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C]](s32)
; CHECK-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C1]](s32)
; CHECK-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C2]](s32)
; CHECK-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C]](s32)
; CHECK-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C1]](s32)
; CHECK-NEXT: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C2]](s32)
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[LSHR]](s32), [[LSHR1]](s32)
; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[LSHR2]](s32), [[UV1]](s32), [[LSHR3]](s32)
; CHECK-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[LSHR4]](s32), [[LSHR5]](s32), [[UV2]](s32)
; CHECK-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[LSHR6]](s32), [[LSHR7]](s32), [[LSHR8]](s32)
; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
; CHECK-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[BUILD_VECTOR1]](<3 x s32>)
; CHECK-NEXT: $vgpr6_vgpr7_vgpr8 = COPY [[BUILD_VECTOR2]](<3 x s32>)
; CHECK-NEXT: $vgpr9_vgpr10_vgpr11 = COPY [[BUILD_VECTOR3]](<3 x s32>)
AMDGPU/GlobalISel: Add baseline, failing unmerge tests
2020-08-20 06:13:23 +08:00
%0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
%1:_(<12 x s8>) = G_BITCAST %0
%2:_(<3 x s8>), %3:_(<3 x s8>), %4:_(<3 x s8>), %5:_(<3 x s8>) = G_UNMERGE_VALUES %1
%6:_(<3 x s32>) = G_ANYEXT %2
%7:_(<3 x s32>) = G_ANYEXT %3
%8:_(<3 x s32>) = G_ANYEXT %4
%9:_(<3 x s32>) = G_ANYEXT %5
$vgpr0_vgpr1_vgpr2 = COPY %6
$vgpr3_vgpr4_vgpr5 = COPY %7
$vgpr6_vgpr7_vgpr8 = COPY %8
$vgpr9_vgpr10_vgpr11 = COPY %9
...
---
name: test_unmerge_v3s16_v12s16
body: |
bb.0:
liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5
; CHECK-LABEL: name: test_unmerge_v3s16_v12s16
; CHECK: [[COPY:%[0-9]+]]:_(<12 x s16>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5
AMDGPU: Regenerate some mir test checks with -NEXT
2021-12-18 23:07:00 +08:00
; CHECK-NEXT: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>), [[UV2:%[0-9]+]]:_(<2 x s16>), [[UV3:%[0-9]+]]:_(<2 x s16>), [[UV4:%[0-9]+]]:_(<2 x s16>), [[UV5:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<12 x s16>)
; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[UV]](<2 x s16>)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[BITCAST]](s32), [[LSHR]](s32), [[BITCAST1]](s32)
; CHECK-NEXT: [[UV6:%[0-9]+]]:_(<2 x s16>), [[UV7:%[0-9]+]]:_(<2 x s16>), [[UV8:%[0-9]+]]:_(<2 x s16>), [[UV9:%[0-9]+]]:_(<2 x s16>), [[UV10:%[0-9]+]]:_(<2 x s16>), [[UV11:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<12 x s16>)
; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV7]](<2 x s16>)
; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; CHECK-NEXT: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV8]](<2 x s16>)
; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[LSHR1]](s32), [[BITCAST3]](s32), [[LSHR2]](s32)
; CHECK-NEXT: [[UV12:%[0-9]+]]:_(<2 x s16>), [[UV13:%[0-9]+]]:_(<2 x s16>), [[UV14:%[0-9]+]]:_(<2 x s16>), [[UV15:%[0-9]+]]:_(<2 x s16>), [[UV16:%[0-9]+]]:_(<2 x s16>), [[UV17:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<12 x s16>)
; CHECK-NEXT: [[BITCAST4:%[0-9]+]]:_(s32) = G_BITCAST [[UV15]](<2 x s16>)
; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST4]], [[C]](s32)
; CHECK-NEXT: [[BITCAST5:%[0-9]+]]:_(s32) = G_BITCAST [[UV16]](<2 x s16>)
; CHECK-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[BITCAST4]](s32), [[LSHR3]](s32), [[BITCAST5]](s32)
; CHECK-NEXT: [[UV18:%[0-9]+]]:_(<2 x s16>), [[UV19:%[0-9]+]]:_(<2 x s16>), [[UV20:%[0-9]+]]:_(<2 x s16>), [[UV21:%[0-9]+]]:_(<2 x s16>), [[UV22:%[0-9]+]]:_(<2 x s16>), [[UV23:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<12 x s16>)
; CHECK-NEXT: [[BITCAST6:%[0-9]+]]:_(s32) = G_BITCAST [[UV22]](<2 x s16>)
; CHECK-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST6]], [[C]](s32)
; CHECK-NEXT: [[BITCAST7:%[0-9]+]]:_(s32) = G_BITCAST [[UV23]](<2 x s16>)
; CHECK-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST7]], [[C]](s32)
; CHECK-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[LSHR4]](s32), [[BITCAST7]](s32), [[LSHR5]](s32)
; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
; CHECK-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[BUILD_VECTOR1]](<3 x s32>)
; CHECK-NEXT: $vgpr6_vgpr7_vgpr8 = COPY [[BUILD_VECTOR2]](<3 x s32>)
; CHECK-NEXT: $vgpr9_vgpr10_vgpr11 = COPY [[BUILD_VECTOR3]](<3 x s32>)
AMDGPU/GlobalISel: Add baseline, failing unmerge tests
2020-08-20 06:13:23 +08:00
%0:_(<12 x s16>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5
%1:_(<3 x s16>), %2:_(<3 x s16>), %3:_(<3 x s16>), %4:_(<3 x s16>) = G_UNMERGE_VALUES %0
%5:_(<3 x s32>) = G_ANYEXT %1
%6:_(<3 x s32>) = G_ANYEXT %2
%7:_(<3 x s32>) = G_ANYEXT %3
%8:_(<3 x s32>) = G_ANYEXT %4
$vgpr0_vgpr1_vgpr2 = COPY %5
$vgpr3_vgpr4_vgpr5 = COPY %6
$vgpr6_vgpr7_vgpr8 = COPY %7
$vgpr9_vgpr10_vgpr11 = COPY %8
...