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llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir

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Canonicalize a large number of mir tests using update_mir_test_checks This converts a large and somewhat arbitrary set of tests to use update_mir_test_checks. I ran the script on all of the tests I expect to need to modify for an upcoming mir syntax change and kept the ones that obviously didn't change the tests in ways that might make it harder to understand. llvm-svn: 316137
2017-10-19 07:18:12 +08:00
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
AMDGPU/GlobalISel: Make s16 G_ICMP legal llvm-svn: 365486
2019-07-09 22:10:43 +08:00
# RUN: llc -O0 -march=amdgcn -mcpu=hawaii -run-pass=legalizer -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX7 %s
# RUN: llc -O0 -march=amdgcn -mcpu=fiji -run-pass=legalizer -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX8 %s
# RUN: llc -O0 -march=amdgcn -mcpu=gfx900 -run-pass=legalizer -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s
[AMDGPU] Extend gfx10 test coverage. NFC. Differential Revision: https://reviews.llvm.org/D99267
2021-03-29 17:12:46 +08:00
# RUN: llc -O0 -march=amdgcn -mcpu=gfx1010 -run-pass=legalizer -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s
AMDGPU/GlobalISel: Mark 32-bit G_ICMP as legal Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, igorb, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D33890 llvm-svn: 304797
2017-06-06 22:16:50 +08:00
---
GlobalISel: Support fewerElementsVector for icmp/fcmp Also legalize 64-bit compares for AMDGPU llvm-svn: 352157
2019-01-25 10:59:34 +08:00
name: test_icmp_s32
AMDGPU/GlobalISel: Mark 32-bit G_ICMP as legal Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, igorb, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D33890 llvm-svn: 304797
2017-06-06 22:16:50 +08:00
body: |
AMDGPU/GlobalISel: Make s16 G_ICMP legal llvm-svn: 365486
2019-07-09 22:10:43 +08:00
bb.0:
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
liveins: $vgpr0
AMDGPU/GlobalISel: Make s16 G_ICMP legal llvm-svn: 365486
2019-07-09 22:10:43 +08:00
; GFX7-LABEL: name: test_icmp_s32
; GFX7: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX7: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX7: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[C]](s32), [[COPY]]
; GFX7: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[C]], [[COPY]]
; GFX7: $vgpr0 = COPY [[SELECT]](s32)
; GFX8-LABEL: name: test_icmp_s32
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[C]](s32), [[COPY]]
; GFX8: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[C]], [[COPY]]
; GFX8: $vgpr0 = COPY [[SELECT]](s32)
; GFX9-LABEL: name: test_icmp_s32
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[C]](s32), [[COPY]]
; GFX9: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[C]], [[COPY]]
; GFX9: $vgpr0 = COPY [[SELECT]](s32)
AMDGPU/GlobalISel: Test cleanups Remove IR and registers sections llvm-svn: 349011
2018-12-13 16:11:45 +08:00
%0:_(s32) = G_CONSTANT i32 0
%1:_(s32) = COPY $vgpr0
%2:_(s1) = G_ICMP intpred(ne), %0, %1
GlobalISel: Support fewerElementsVector for icmp/fcmp Also legalize 64-bit compares for AMDGPU llvm-svn: 352157
2019-01-25 10:59:34 +08:00
%3:_(s32) = G_SELECT %2, %0, %1
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
$vgpr0 = COPY %3
AMDGPU/GlobalISel: Mark 32-bit G_ICMP as legal Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, igorb, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D33890 llvm-svn: 304797
2017-06-06 22:16:50 +08:00
...
GlobalISel: Support fewerElementsVector for icmp/fcmp Also legalize 64-bit compares for AMDGPU llvm-svn: 352157
2019-01-25 10:59:34 +08:00
---
name: test_icmp_s64
body: |
AMDGPU/GlobalISel: Make s16 G_ICMP legal llvm-svn: 365486
2019-07-09 22:10:43 +08:00
bb.0:
GlobalISel: Support fewerElementsVector for icmp/fcmp Also legalize 64-bit compares for AMDGPU llvm-svn: 352157
2019-01-25 10:59:34 +08:00
liveins: $vgpr0_vgpr1
AMDGPU/GlobalISel: Make s16 G_ICMP legal llvm-svn: 365486
2019-07-09 22:10:43 +08:00
; GFX7-LABEL: name: test_icmp_s64
; GFX7: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; GFX7: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX7: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[C]](s64), [[COPY]]
; GFX7: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[C]], [[COPY]]
; GFX7: $vgpr0_vgpr1 = COPY [[SELECT]](s64)
; GFX8-LABEL: name: test_icmp_s64
; GFX8: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; GFX8: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX8: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[C]](s64), [[COPY]]
; GFX8: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[C]], [[COPY]]
; GFX8: $vgpr0_vgpr1 = COPY [[SELECT]](s64)
; GFX9-LABEL: name: test_icmp_s64
; GFX9: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; GFX9: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX9: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[C]](s64), [[COPY]]
; GFX9: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[C]], [[COPY]]
; GFX9: $vgpr0_vgpr1 = COPY [[SELECT]](s64)
GlobalISel: Support fewerElementsVector for icmp/fcmp Also legalize 64-bit compares for AMDGPU llvm-svn: 352157
2019-01-25 10:59:34 +08:00
%0:_(s64) = G_CONSTANT i64 0
%1:_(s64) = COPY $vgpr0_vgpr1
%2:_(s1) = G_ICMP intpred(ne), %0, %1
%3:_(s64) = G_SELECT %2, %0, %1
$vgpr0_vgpr1 = COPY %3
...
---
name: test_icmp_s16
body: |
AMDGPU/GlobalISel: Make s16 G_ICMP legal llvm-svn: 365486
2019-07-09 22:10:43 +08:00
bb.0:
GlobalISel: Support fewerElementsVector for icmp/fcmp Also legalize 64-bit compares for AMDGPU llvm-svn: 352157
2019-01-25 10:59:34 +08:00
liveins: $vgpr0
AMDGPU/GlobalISel: Make s16 G_ICMP legal llvm-svn: 365486
2019-07-09 22:10:43 +08:00
; GFX7-LABEL: name: test_icmp_s16
AMDGPU/GlobalISel: Make 16-bit constants legal This is mostly for the benefit of patterns which use 16-bit constants. llvm-svn: 370921
2019-09-05 00:19:45 +08:00
; GFX7: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
AMDGPU/GlobalISel: Make s16 G_ICMP legal llvm-svn: 365486
2019-07-09 22:10:43 +08:00
; GFX7: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
AMDGPU/GlobalISel: Make 16-bit constants legal This is mostly for the benefit of patterns which use 16-bit constants. llvm-svn: 370921
2019-09-05 00:19:45 +08:00
; GFX7: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX7: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX7: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
[GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner When Src and Dst used in buildAnyExtOrTrunc or buildSExtOrTrunc have the same type (creates COPY) use Src register directly or use replaceRegOrBuildCopy instead. Differential Revision: https://reviews.llvm.org/D108306
2021-08-24 17:09:37 +08:00
; GFX7: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C2]]
AMDGPU/GlobalISel: Make 16-bit constants legal This is mostly for the benefit of patterns which use 16-bit constants. llvm-svn: 370921
2019-09-05 00:19:45 +08:00
; GFX7: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[C1]](s32), [[AND]]
; GFX7: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[C]], [[TRUNC]]
AMDGPU/GlobalISel: Make s16 G_ICMP legal llvm-svn: 365486
2019-07-09 22:10:43 +08:00
; GFX7: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT]](s16)
; GFX7: $vgpr0 = COPY [[ANYEXT]](s32)
; GFX8-LABEL: name: test_icmp_s16
AMDGPU/GlobalISel: Make 16-bit constants legal This is mostly for the benefit of patterns which use 16-bit constants. llvm-svn: 370921
2019-09-05 00:19:45 +08:00
; GFX8: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
AMDGPU/GlobalISel: Make s16 G_ICMP legal llvm-svn: 365486
2019-07-09 22:10:43 +08:00
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
AMDGPU/GlobalISel: Make 16-bit constants legal This is mostly for the benefit of patterns which use 16-bit constants. llvm-svn: 370921
2019-09-05 00:19:45 +08:00
; GFX8: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX8: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[C]](s16), [[TRUNC]]
; GFX8: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[C]], [[TRUNC]]
AMDGPU/GlobalISel: Make s16 G_ICMP legal llvm-svn: 365486
2019-07-09 22:10:43 +08:00
; GFX8: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT]](s16)
; GFX8: $vgpr0 = COPY [[ANYEXT]](s32)
; GFX9-LABEL: name: test_icmp_s16
AMDGPU/GlobalISel: Make 16-bit constants legal This is mostly for the benefit of patterns which use 16-bit constants. llvm-svn: 370921
2019-09-05 00:19:45 +08:00
; GFX9: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
AMDGPU/GlobalISel: Make s16 G_ICMP legal llvm-svn: 365486
2019-07-09 22:10:43 +08:00
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
AMDGPU/GlobalISel: Make 16-bit constants legal This is mostly for the benefit of patterns which use 16-bit constants. llvm-svn: 370921
2019-09-05 00:19:45 +08:00
; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX9: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[C]](s16), [[TRUNC]]
; GFX9: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[C]], [[TRUNC]]
AMDGPU/GlobalISel: Make s16 G_ICMP legal llvm-svn: 365486
2019-07-09 22:10:43 +08:00
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT]](s16)
; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)
GlobalISel: Support fewerElementsVector for icmp/fcmp Also legalize 64-bit compares for AMDGPU llvm-svn: 352157
2019-01-25 10:59:34 +08:00
%0:_(s16) = G_CONSTANT i16 0
%1:_(s32) = COPY $vgpr0
%2:_(s16) = G_TRUNC %1
%3:_(s1) = G_ICMP intpred(ne), %0, %2
%4:_(s16) = G_SELECT %3, %0, %2
%5:_(s32) = G_ANYEXT %4
$vgpr0 = COPY %5
...
---
name: test_icmp_s8
body: |
AMDGPU/GlobalISel: Make s16 G_ICMP legal llvm-svn: 365486
2019-07-09 22:10:43 +08:00
bb.0:
GlobalISel: Support fewerElementsVector for icmp/fcmp Also legalize 64-bit compares for AMDGPU llvm-svn: 352157
2019-01-25 10:59:34 +08:00
liveins: $vgpr0
AMDGPU/GlobalISel: Make s16 G_ICMP legal llvm-svn: 365486
2019-07-09 22:10:43 +08:00
; GFX7-LABEL: name: test_icmp_s8
; GFX7: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX7: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX7: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; GFX7: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
[GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner When Src and Dst used in buildAnyExtOrTrunc or buildSExtOrTrunc have the same type (creates COPY) use Src register directly or use replaceRegOrBuildCopy instead. Differential Revision: https://reviews.llvm.org/D108306
2021-08-24 17:09:37 +08:00
; GFX7: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
; GFX7: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[AND]]
[GlobalISel][AArch64][AMDGPU][X86] Teach LegalizationArtifactCombiner to combine trunc(g_constant). This allows X86 to properly form shift by immediate instructions since we require an 8-bit constant to match the imported SelectionDAG patterns.
2019-10-25 03:08:02 +08:00
; GFX7: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
; GFX7: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX7: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[C2]], [[TRUNC]]
AMDGPU/GlobalISel: Make s16 G_ICMP legal llvm-svn: 365486
2019-07-09 22:10:43 +08:00
; GFX7: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT]](s16)
; GFX7: $vgpr0 = COPY [[ANYEXT]](s32)
; GFX8-LABEL: name: test_icmp_s8
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
[GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner When Src and Dst used in buildAnyExtOrTrunc or buildSExtOrTrunc have the same type (creates COPY) use Src register directly or use replaceRegOrBuildCopy instead. Differential Revision: https://reviews.llvm.org/D108306
2021-08-24 17:09:37 +08:00
; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
; GFX8: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[AND]]
[GlobalISel][AArch64][AMDGPU][X86] Teach LegalizationArtifactCombiner to combine trunc(g_constant). This allows X86 to properly form shift by immediate instructions since we require an 8-bit constant to match the imported SelectionDAG patterns.
2019-10-25 03:08:02 +08:00
; GFX8: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
; GFX8: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX8: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[C2]], [[TRUNC]]
AMDGPU/GlobalISel: Make s16 G_ICMP legal llvm-svn: 365486
2019-07-09 22:10:43 +08:00
; GFX8: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT]](s16)
; GFX8: $vgpr0 = COPY [[ANYEXT]](s32)
; GFX9-LABEL: name: test_icmp_s8
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
[GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner When Src and Dst used in buildAnyExtOrTrunc or buildSExtOrTrunc have the same type (creates COPY) use Src register directly or use replaceRegOrBuildCopy instead. Differential Revision: https://reviews.llvm.org/D108306
2021-08-24 17:09:37 +08:00
; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
; GFX9: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[AND]]
[GlobalISel][AArch64][AMDGPU][X86] Teach LegalizationArtifactCombiner to combine trunc(g_constant). This allows X86 to properly form shift by immediate instructions since we require an 8-bit constant to match the imported SelectionDAG patterns.
2019-10-25 03:08:02 +08:00
; GFX9: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX9: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[C2]], [[TRUNC]]
AMDGPU/GlobalISel: Make s16 G_ICMP legal llvm-svn: 365486
2019-07-09 22:10:43 +08:00
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT]](s16)
; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)
GlobalISel: Enforce operand types for constants A number of of tests were using imm operands, not cimm. Since CSE relies on the exact ConstantInt* pointer used, and implicit conversions are generally evil, also enforce the bitsize of the types. llvm-svn: 353113
2019-02-05 07:29:31 +08:00
%0:_(s8) = G_CONSTANT i8 0
GlobalISel: Support fewerElementsVector for icmp/fcmp Also legalize 64-bit compares for AMDGPU llvm-svn: 352157
2019-01-25 10:59:34 +08:00
%1:_(s32) = COPY $vgpr0
%2:_(s8) = G_TRUNC %1
%3:_(s1) = G_ICMP intpred(ne), %0, %2
%4:_(s8) = G_SELECT %3, %0, %2
%5:_(s32) = G_ANYEXT %4
$vgpr0 = COPY %5
...
AMDGPU/GlobalISel: Add some missing tests for non-power-of-2 cases
2020-02-16 11:13:29 +08:00
---
name: test_icmp_s24
body: |
bb.0:
liveins: $vgpr0
; GFX7-LABEL: name: test_icmp_s24
; GFX7: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX7: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX7: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
; GFX7: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
[GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner When Src and Dst used in buildAnyExtOrTrunc or buildSExtOrTrunc have the same type (creates COPY) use Src register directly or use replaceRegOrBuildCopy instead. Differential Revision: https://reviews.llvm.org/D108306
2021-08-24 17:09:37 +08:00
; GFX7: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
; GFX7: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[AND]]
; GFX7: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[C]], [[COPY]]
; GFX7: $vgpr0 = COPY [[SELECT]](s32)
AMDGPU/GlobalISel: Add some missing tests for non-power-of-2 cases
2020-02-16 11:13:29 +08:00
; GFX8-LABEL: name: test_icmp_s24
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
[GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner When Src and Dst used in buildAnyExtOrTrunc or buildSExtOrTrunc have the same type (creates COPY) use Src register directly or use replaceRegOrBuildCopy instead. Differential Revision: https://reviews.llvm.org/D108306
2021-08-24 17:09:37 +08:00
; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
; GFX8: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[AND]]
; GFX8: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[C]], [[COPY]]
; GFX8: $vgpr0 = COPY [[SELECT]](s32)
AMDGPU/GlobalISel: Add some missing tests for non-power-of-2 cases
2020-02-16 11:13:29 +08:00
; GFX9-LABEL: name: test_icmp_s24
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
[GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner When Src and Dst used in buildAnyExtOrTrunc or buildSExtOrTrunc have the same type (creates COPY) use Src register directly or use replaceRegOrBuildCopy instead. Differential Revision: https://reviews.llvm.org/D108306
2021-08-24 17:09:37 +08:00
; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
; GFX9: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[AND]]
; GFX9: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[C]], [[COPY]]
; GFX9: $vgpr0 = COPY [[SELECT]](s32)
AMDGPU/GlobalISel: Add some missing tests for non-power-of-2 cases
2020-02-16 11:13:29 +08:00
%0:_(s24) = G_CONSTANT i24 0
%1:_(s32) = COPY $vgpr0
%2:_(s24) = G_TRUNC %1
%3:_(s1) = G_ICMP intpred(ne), %0, %2
%4:_(s24) = G_SELECT %3, %0, %2
%5:_(s32) = G_ANYEXT %4
$vgpr0 = COPY %5
...
GlobalISel: Support fewerElementsVector for icmp/fcmp Also legalize 64-bit compares for AMDGPU llvm-svn: 352157
2019-01-25 10:59:34 +08:00
---
name: test_icmp_v2s32
body: |
AMDGPU/GlobalISel: Make s16 G_ICMP legal llvm-svn: 365486
2019-07-09 22:10:43 +08:00
bb.0:
GlobalISel: Support fewerElementsVector for icmp/fcmp Also legalize 64-bit compares for AMDGPU llvm-svn: 352157
2019-01-25 10:59:34 +08:00
liveins: $vgpr0_vgpr1
AMDGPU/GlobalISel: Make s16 G_ICMP legal llvm-svn: 365486
2019-07-09 22:10:43 +08:00
; GFX7-LABEL: name: test_icmp_v2s32
; GFX7: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX7: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; GFX7: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; GFX7: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[C]](s32), [[UV]]
; GFX7: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[C]](s32), [[UV1]]
AMDGPU/GlobalISel: Fix legality for G_BUILD_VECTOR llvm-svn: 365575
2019-07-10 06:48:04 +08:00
; GFX7: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1)
; GFX7: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP1]](s1)
; GFX7: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
[GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner When Src and Dst used in buildAnyExtOrTrunc or buildSExtOrTrunc have the same type (creates COPY) use Src register directly or use replaceRegOrBuildCopy instead. Differential Revision: https://reviews.llvm.org/D108306
2021-08-24 17:09:37 +08:00
; GFX7: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C1]]
; GFX7: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C1]]
AMDGPU/GlobalISel: Fix legality for G_BUILD_VECTOR llvm-svn: 365575
2019-07-10 06:48:04 +08:00
; GFX7: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[AND]](s32), [[AND1]](s32)
; GFX7: S_NOP 0, implicit [[BUILD_VECTOR]](<2 x s32>)
AMDGPU/GlobalISel: Make s16 G_ICMP legal llvm-svn: 365486
2019-07-09 22:10:43 +08:00
; GFX8-LABEL: name: test_icmp_v2s32
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX8: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; GFX8: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; GFX8: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[C]](s32), [[UV]]
; GFX8: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[C]](s32), [[UV1]]
AMDGPU/GlobalISel: Fix legality for G_BUILD_VECTOR llvm-svn: 365575
2019-07-10 06:48:04 +08:00
; GFX8: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1)
; GFX8: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP1]](s1)
; GFX8: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
[GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner When Src and Dst used in buildAnyExtOrTrunc or buildSExtOrTrunc have the same type (creates COPY) use Src register directly or use replaceRegOrBuildCopy instead. Differential Revision: https://reviews.llvm.org/D108306
2021-08-24 17:09:37 +08:00
; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C1]]
; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C1]]
AMDGPU/GlobalISel: Fix legality for G_BUILD_VECTOR llvm-svn: 365575
2019-07-10 06:48:04 +08:00
; GFX8: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[AND]](s32), [[AND1]](s32)
; GFX8: S_NOP 0, implicit [[BUILD_VECTOR]](<2 x s32>)
AMDGPU/GlobalISel: Make s16 G_ICMP legal llvm-svn: 365486
2019-07-09 22:10:43 +08:00
; GFX9-LABEL: name: test_icmp_v2s32
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX9: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; GFX9: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[C]](s32), [[UV]]
; GFX9: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[C]](s32), [[UV1]]
AMDGPU/GlobalISel: Don't use legal v2s16 G_BUILD_VECTOR If we have s_pack_* instructions, legalize this to G_BUILD_VECTOR_TRUNC from s32 elements. This is closer to how how the s_pack_* instructions really behave. If we don't have s_pack_ instructions, expand this by creating a merge to s32 and bitcasting. This expands to the expected bit operations. I think this eventually should go in a new bitcast legalize action type in LegalizerHelper. We already directly emit the shift operations in RegBankSelect for the vector case. This could possibly be cleaned up, but I also may want to defer doing this expansion to selection anyway. I'll see about that when I try to actually match VOP3P instructions. This breaks the selection of the build_vector since tablegen doesn't know how to match G_BUILD_VECTOR_TRUNC yet, so just xfail it for now.
2020-01-05 04:35:26 +08:00
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
AMDGPU/GlobalISel: Fix legality for G_BUILD_VECTOR llvm-svn: 365575
2019-07-10 06:48:04 +08:00
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1)
AMDGPU/GlobalISel: Don't use legal v2s16 G_BUILD_VECTOR If we have s_pack_* instructions, legalize this to G_BUILD_VECTOR_TRUNC from s32 elements. This is closer to how how the s_pack_* instructions really behave. If we don't have s_pack_ instructions, expand this by creating a merge to s32 and bitcasting. This expands to the expected bit operations. I think this eventually should go in a new bitcast legalize action type in LegalizerHelper. We already directly emit the shift operations in RegBankSelect for the vector case. This could possibly be cleaned up, but I also may want to defer doing this expansion to selection anyway. I'll see about that when I try to actually match VOP3P instructions. This breaks the selection of the build_vector since tablegen doesn't know how to match G_BUILD_VECTOR_TRUNC yet, so just xfail it for now.
2020-01-05 04:35:26 +08:00
; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C1]]
AMDGPU/GlobalISel: Fix legality for G_BUILD_VECTOR llvm-svn: 365575
2019-07-10 06:48:04 +08:00
; GFX9: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP1]](s1)
AMDGPU/GlobalISel: Don't use legal v2s16 G_BUILD_VECTOR If we have s_pack_* instructions, legalize this to G_BUILD_VECTOR_TRUNC from s32 elements. This is closer to how how the s_pack_* instructions really behave. If we don't have s_pack_ instructions, expand this by creating a merge to s32 and bitcasting. This expands to the expected bit operations. I think this eventually should go in a new bitcast legalize action type in LegalizerHelper. We already directly emit the shift operations in RegBankSelect for the vector case. This could possibly be cleaned up, but I also may want to defer doing this expansion to selection anyway. I'll see about that when I try to actually match VOP3P instructions. This breaks the selection of the build_vector since tablegen doesn't know how to match G_BUILD_VECTOR_TRUNC yet, so just xfail it for now.
2020-01-05 04:35:26 +08:00
; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C1]]
AMDGPU/GlobalISel: Fix legality for G_BUILD_VECTOR llvm-svn: 365575
2019-07-10 06:48:04 +08:00
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[AND]](s32), [[AND1]](s32)
; GFX9: S_NOP 0, implicit [[BUILD_VECTOR]](<2 x s32>)
GlobalISel: Support fewerElementsVector for icmp/fcmp Also legalize 64-bit compares for AMDGPU llvm-svn: 352157
2019-01-25 10:59:34 +08:00
%0:_(s32) = G_CONSTANT i32 0
%1:_(<2 x s32>) = G_BUILD_VECTOR %0, %0
%2:_(<2 x s32>) = COPY $vgpr0_vgpr1
%3:_(<2 x s1>) = G_ICMP intpred(ne), %1, %2
AMDGPU/GlobalISel: Fix legality for G_BUILD_VECTOR llvm-svn: 365575
2019-07-10 06:48:04 +08:00
%4:_(<2 x s32>) = G_ZEXT %3
S_NOP 0, implicit %4
GlobalISel: Support fewerElementsVector for icmp/fcmp Also legalize 64-bit compares for AMDGPU llvm-svn: 352157
2019-01-25 10:59:34 +08:00
...
---
name: test_icmp_v3s32
body: |
AMDGPU/GlobalISel: Make s16 G_ICMP legal llvm-svn: 365486
2019-07-09 22:10:43 +08:00
bb.0:
GlobalISel: Support fewerElementsVector for icmp/fcmp Also legalize 64-bit compares for AMDGPU llvm-svn: 352157
2019-01-25 10:59:34 +08:00
liveins: $vgpr0_vgpr1_vgpr2
AMDGPU/GlobalISel: Make s16 G_ICMP legal llvm-svn: 365486
2019-07-09 22:10:43 +08:00
; GFX7-LABEL: name: test_icmp_v3s32
; GFX7: [[DEF:%[0-9]+]]:_(<3 x s32>) = G_IMPLICIT_DEF
; GFX7: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
; GFX7: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](<3 x s32>)
; GFX7: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
; GFX7: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV]](s32), [[UV3]]
; GFX7: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV1]](s32), [[UV4]]
; GFX7: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV2]](s32), [[UV5]]
AMDGPU/GlobalISel: Fix legality for G_BUILD_VECTOR llvm-svn: 365575
2019-07-10 06:48:04 +08:00
; GFX7: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1)
; GFX7: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP1]](s1)
; GFX7: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP2]](s1)
; GFX7: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
[GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner When Src and Dst used in buildAnyExtOrTrunc or buildSExtOrTrunc have the same type (creates COPY) use Src register directly or use replaceRegOrBuildCopy instead. Differential Revision: https://reviews.llvm.org/D108306
2021-08-24 17:09:37 +08:00
; GFX7: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C]]
; GFX7: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C]]
; GFX7: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ANYEXT2]], [[C]]
AMDGPU/GlobalISel: Fix legality for G_BUILD_VECTOR llvm-svn: 365575
2019-07-10 06:48:04 +08:00
; GFX7: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[AND]](s32), [[AND1]](s32), [[AND2]](s32)
; GFX7: S_NOP 0, implicit [[BUILD_VECTOR]](<3 x s32>)
AMDGPU/GlobalISel: Make s16 G_ICMP legal llvm-svn: 365486
2019-07-09 22:10:43 +08:00
; GFX8-LABEL: name: test_icmp_v3s32
; GFX8: [[DEF:%[0-9]+]]:_(<3 x s32>) = G_IMPLICIT_DEF
; GFX8: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
; GFX8: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](<3 x s32>)
; GFX8: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
; GFX8: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV]](s32), [[UV3]]
; GFX8: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV1]](s32), [[UV4]]
; GFX8: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV2]](s32), [[UV5]]
AMDGPU/GlobalISel: Fix legality for G_BUILD_VECTOR llvm-svn: 365575
2019-07-10 06:48:04 +08:00
; GFX8: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1)
; GFX8: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP1]](s1)
; GFX8: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP2]](s1)
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
[GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner When Src and Dst used in buildAnyExtOrTrunc or buildSExtOrTrunc have the same type (creates COPY) use Src register directly or use replaceRegOrBuildCopy instead. Differential Revision: https://reviews.llvm.org/D108306
2021-08-24 17:09:37 +08:00
; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C]]
; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C]]
; GFX8: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ANYEXT2]], [[C]]
AMDGPU/GlobalISel: Fix legality for G_BUILD_VECTOR llvm-svn: 365575
2019-07-10 06:48:04 +08:00
; GFX8: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[AND]](s32), [[AND1]](s32), [[AND2]](s32)
; GFX8: S_NOP 0, implicit [[BUILD_VECTOR]](<3 x s32>)
AMDGPU/GlobalISel: Make s16 G_ICMP legal llvm-svn: 365486
2019-07-09 22:10:43 +08:00
; GFX9-LABEL: name: test_icmp_v3s32
; GFX9: [[DEF:%[0-9]+]]:_(<3 x s32>) = G_IMPLICIT_DEF
; GFX9: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](<3 x s32>)
; GFX9: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
; GFX9: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV]](s32), [[UV3]]
; GFX9: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV1]](s32), [[UV4]]
; GFX9: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV2]](s32), [[UV5]]
AMDGPU/GlobalISel: Don't use legal v2s16 G_BUILD_VECTOR If we have s_pack_* instructions, legalize this to G_BUILD_VECTOR_TRUNC from s32 elements. This is closer to how how the s_pack_* instructions really behave. If we don't have s_pack_ instructions, expand this by creating a merge to s32 and bitcasting. This expands to the expected bit operations. I think this eventually should go in a new bitcast legalize action type in LegalizerHelper. We already directly emit the shift operations in RegBankSelect for the vector case. This could possibly be cleaned up, but I also may want to defer doing this expansion to selection anyway. I'll see about that when I try to actually match VOP3P instructions. This breaks the selection of the build_vector since tablegen doesn't know how to match G_BUILD_VECTOR_TRUNC yet, so just xfail it for now.
2020-01-05 04:35:26 +08:00
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
AMDGPU/GlobalISel: Fix legality for G_BUILD_VECTOR llvm-svn: 365575
2019-07-10 06:48:04 +08:00
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1)
AMDGPU/GlobalISel: Don't use legal v2s16 G_BUILD_VECTOR If we have s_pack_* instructions, legalize this to G_BUILD_VECTOR_TRUNC from s32 elements. This is closer to how how the s_pack_* instructions really behave. If we don't have s_pack_ instructions, expand this by creating a merge to s32 and bitcasting. This expands to the expected bit operations. I think this eventually should go in a new bitcast legalize action type in LegalizerHelper. We already directly emit the shift operations in RegBankSelect for the vector case. This could possibly be cleaned up, but I also may want to defer doing this expansion to selection anyway. I'll see about that when I try to actually match VOP3P instructions. This breaks the selection of the build_vector since tablegen doesn't know how to match G_BUILD_VECTOR_TRUNC yet, so just xfail it for now.
2020-01-05 04:35:26 +08:00
; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C]]
AMDGPU/GlobalISel: Fix legality for G_BUILD_VECTOR llvm-svn: 365575
2019-07-10 06:48:04 +08:00
; GFX9: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP1]](s1)
AMDGPU/GlobalISel: Don't use legal v2s16 G_BUILD_VECTOR If we have s_pack_* instructions, legalize this to G_BUILD_VECTOR_TRUNC from s32 elements. This is closer to how how the s_pack_* instructions really behave. If we don't have s_pack_ instructions, expand this by creating a merge to s32 and bitcasting. This expands to the expected bit operations. I think this eventually should go in a new bitcast legalize action type in LegalizerHelper. We already directly emit the shift operations in RegBankSelect for the vector case. This could possibly be cleaned up, but I also may want to defer doing this expansion to selection anyway. I'll see about that when I try to actually match VOP3P instructions. This breaks the selection of the build_vector since tablegen doesn't know how to match G_BUILD_VECTOR_TRUNC yet, so just xfail it for now.
2020-01-05 04:35:26 +08:00
; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C]]
AMDGPU/GlobalISel: Fix legality for G_BUILD_VECTOR llvm-svn: 365575
2019-07-10 06:48:04 +08:00
; GFX9: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP2]](s1)
AMDGPU/GlobalISel: Don't use legal v2s16 G_BUILD_VECTOR If we have s_pack_* instructions, legalize this to G_BUILD_VECTOR_TRUNC from s32 elements. This is closer to how how the s_pack_* instructions really behave. If we don't have s_pack_ instructions, expand this by creating a merge to s32 and bitcasting. This expands to the expected bit operations. I think this eventually should go in a new bitcast legalize action type in LegalizerHelper. We already directly emit the shift operations in RegBankSelect for the vector case. This could possibly be cleaned up, but I also may want to defer doing this expansion to selection anyway. I'll see about that when I try to actually match VOP3P instructions. This breaks the selection of the build_vector since tablegen doesn't know how to match G_BUILD_VECTOR_TRUNC yet, so just xfail it for now.
2020-01-05 04:35:26 +08:00
; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ANYEXT2]], [[C]]
AMDGPU/GlobalISel: Fix legality for G_BUILD_VECTOR llvm-svn: 365575
2019-07-10 06:48:04 +08:00
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[AND]](s32), [[AND1]](s32), [[AND2]](s32)
; GFX9: S_NOP 0, implicit [[BUILD_VECTOR]](<3 x s32>)
GlobalISel: Support fewerElementsVector for icmp/fcmp Also legalize 64-bit compares for AMDGPU llvm-svn: 352157
2019-01-25 10:59:34 +08:00
%0:_(<3 x s32>) = G_IMPLICIT_DEF
%1:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
%2:_(<3 x s1>) = G_ICMP intpred(ne), %0, %1
AMDGPU/GlobalISel: Fix legality for G_BUILD_VECTOR llvm-svn: 365575
2019-07-10 06:48:04 +08:00
%3:_(<3 x s32>) = G_ZEXT %2
S_NOP 0, implicit %3
GlobalISel: Support fewerElementsVector for icmp/fcmp Also legalize 64-bit compares for AMDGPU llvm-svn: 352157
2019-01-25 10:59:34 +08:00
...
---
name: test_icmp_v4s32
body: |
AMDGPU/GlobalISel: Make s16 G_ICMP legal llvm-svn: 365486
2019-07-09 22:10:43 +08:00
bb.0:
GlobalISel: Support fewerElementsVector for icmp/fcmp Also legalize 64-bit compares for AMDGPU llvm-svn: 352157
2019-01-25 10:59:34 +08:00
liveins: $vgpr0_vgpr1_vgpr2_vgpr3
AMDGPU/GlobalISel: Make s16 G_ICMP legal llvm-svn: 365486
2019-07-09 22:10:43 +08:00
; GFX7-LABEL: name: test_icmp_v4s32
; GFX7: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
CodeGen: Print/parse LLTs in MachineMemOperands This will currently accept the old number of bytes syntax, and convert it to a scalar. This should be removed in the near future (I think I converted all of the tests already, but likely missed a few). Not sure what the exact syntax and policy should be. We can continue printing the number of bytes for non-generic instructions to avoid test churn and only allow non-scalar types for generic instructions. This will currently print the LLT in parentheses, but accept parsing the existing integers and implicitly converting to scalar. The parentheses are a bit ugly, but the parser logic seems unable to deal without either parentheses or some keyword to indicate the start of a type.
2021-05-20 10:25:51 +08:00
; GFX7: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[DEF]](p1) :: (volatile load (<4 x s32>))
AMDGPU/GlobalISel: Make s16 G_ICMP legal llvm-svn: 365486
2019-07-09 22:10:43 +08:00
; GFX7: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; GFX7: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](<4 x s32>)
; GFX7: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<4 x s32>)
; GFX7: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV]](s32), [[UV4]]
; GFX7: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV1]](s32), [[UV5]]
; GFX7: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV2]](s32), [[UV6]]
; GFX7: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV3]](s32), [[UV7]]
AMDGPU/GlobalISel: Fix legality for G_BUILD_VECTOR llvm-svn: 365575
2019-07-10 06:48:04 +08:00
; GFX7: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1)
; GFX7: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP1]](s1)
; GFX7: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP2]](s1)
; GFX7: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP3]](s1)
; GFX7: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
[GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner When Src and Dst used in buildAnyExtOrTrunc or buildSExtOrTrunc have the same type (creates COPY) use Src register directly or use replaceRegOrBuildCopy instead. Differential Revision: https://reviews.llvm.org/D108306
2021-08-24 17:09:37 +08:00
; GFX7: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C]]
; GFX7: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C]]
; GFX7: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ANYEXT2]], [[C]]
; GFX7: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ANYEXT3]], [[C]]
AMDGPU/GlobalISel: Fix legality for G_BUILD_VECTOR llvm-svn: 365575
2019-07-10 06:48:04 +08:00
; GFX7: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[AND]](s32), [[AND1]](s32), [[AND2]](s32), [[AND3]](s32)
; GFX7: S_NOP 0, implicit [[BUILD_VECTOR]](<4 x s32>)
AMDGPU/GlobalISel: Make s16 G_ICMP legal llvm-svn: 365486
2019-07-09 22:10:43 +08:00
; GFX8-LABEL: name: test_icmp_v4s32
; GFX8: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
CodeGen: Print/parse LLTs in MachineMemOperands This will currently accept the old number of bytes syntax, and convert it to a scalar. This should be removed in the near future (I think I converted all of the tests already, but likely missed a few). Not sure what the exact syntax and policy should be. We can continue printing the number of bytes for non-generic instructions to avoid test churn and only allow non-scalar types for generic instructions. This will currently print the LLT in parentheses, but accept parsing the existing integers and implicitly converting to scalar. The parentheses are a bit ugly, but the parser logic seems unable to deal without either parentheses or some keyword to indicate the start of a type.
2021-05-20 10:25:51 +08:00
; GFX8: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[DEF]](p1) :: (volatile load (<4 x s32>))
AMDGPU/GlobalISel: Make s16 G_ICMP legal llvm-svn: 365486
2019-07-09 22:10:43 +08:00
; GFX8: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; GFX8: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](<4 x s32>)
; GFX8: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<4 x s32>)
; GFX8: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV]](s32), [[UV4]]
; GFX8: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV1]](s32), [[UV5]]
; GFX8: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV2]](s32), [[UV6]]
; GFX8: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV3]](s32), [[UV7]]
AMDGPU/GlobalISel: Fix legality for G_BUILD_VECTOR llvm-svn: 365575
2019-07-10 06:48:04 +08:00
; GFX8: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1)
; GFX8: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP1]](s1)
; GFX8: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP2]](s1)
; GFX8: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP3]](s1)
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
[GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner When Src and Dst used in buildAnyExtOrTrunc or buildSExtOrTrunc have the same type (creates COPY) use Src register directly or use replaceRegOrBuildCopy instead. Differential Revision: https://reviews.llvm.org/D108306
2021-08-24 17:09:37 +08:00
; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C]]
; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C]]
; GFX8: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ANYEXT2]], [[C]]
; GFX8: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ANYEXT3]], [[C]]
AMDGPU/GlobalISel: Fix legality for G_BUILD_VECTOR llvm-svn: 365575
2019-07-10 06:48:04 +08:00
; GFX8: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[AND]](s32), [[AND1]](s32), [[AND2]](s32), [[AND3]](s32)
; GFX8: S_NOP 0, implicit [[BUILD_VECTOR]](<4 x s32>)
AMDGPU/GlobalISel: Make s16 G_ICMP legal llvm-svn: 365486
2019-07-09 22:10:43 +08:00
; GFX9-LABEL: name: test_icmp_v4s32
; GFX9: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
CodeGen: Print/parse LLTs in MachineMemOperands This will currently accept the old number of bytes syntax, and convert it to a scalar. This should be removed in the near future (I think I converted all of the tests already, but likely missed a few). Not sure what the exact syntax and policy should be. We can continue printing the number of bytes for non-generic instructions to avoid test churn and only allow non-scalar types for generic instructions. This will currently print the LLT in parentheses, but accept parsing the existing integers and implicitly converting to scalar. The parentheses are a bit ugly, but the parser logic seems unable to deal without either parentheses or some keyword to indicate the start of a type.
2021-05-20 10:25:51 +08:00
; GFX9: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[DEF]](p1) :: (volatile load (<4 x s32>))
AMDGPU/GlobalISel: Make s16 G_ICMP legal llvm-svn: 365486
2019-07-09 22:10:43 +08:00
; GFX9: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](<4 x s32>)
; GFX9: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<4 x s32>)
; GFX9: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV]](s32), [[UV4]]
; GFX9: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV1]](s32), [[UV5]]
; GFX9: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV2]](s32), [[UV6]]
; GFX9: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV3]](s32), [[UV7]]
AMDGPU/GlobalISel: Don't use legal v2s16 G_BUILD_VECTOR If we have s_pack_* instructions, legalize this to G_BUILD_VECTOR_TRUNC from s32 elements. This is closer to how how the s_pack_* instructions really behave. If we don't have s_pack_ instructions, expand this by creating a merge to s32 and bitcasting. This expands to the expected bit operations. I think this eventually should go in a new bitcast legalize action type in LegalizerHelper. We already directly emit the shift operations in RegBankSelect for the vector case. This could possibly be cleaned up, but I also may want to defer doing this expansion to selection anyway. I'll see about that when I try to actually match VOP3P instructions. This breaks the selection of the build_vector since tablegen doesn't know how to match G_BUILD_VECTOR_TRUNC yet, so just xfail it for now.
2020-01-05 04:35:26 +08:00
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
AMDGPU/GlobalISel: Fix legality for G_BUILD_VECTOR llvm-svn: 365575
2019-07-10 06:48:04 +08:00
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1)
AMDGPU/GlobalISel: Don't use legal v2s16 G_BUILD_VECTOR If we have s_pack_* instructions, legalize this to G_BUILD_VECTOR_TRUNC from s32 elements. This is closer to how how the s_pack_* instructions really behave. If we don't have s_pack_ instructions, expand this by creating a merge to s32 and bitcasting. This expands to the expected bit operations. I think this eventually should go in a new bitcast legalize action type in LegalizerHelper. We already directly emit the shift operations in RegBankSelect for the vector case. This could possibly be cleaned up, but I also may want to defer doing this expansion to selection anyway. I'll see about that when I try to actually match VOP3P instructions. This breaks the selection of the build_vector since tablegen doesn't know how to match G_BUILD_VECTOR_TRUNC yet, so just xfail it for now.
2020-01-05 04:35:26 +08:00
; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C]]
AMDGPU/GlobalISel: Fix legality for G_BUILD_VECTOR llvm-svn: 365575
2019-07-10 06:48:04 +08:00
; GFX9: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP1]](s1)
AMDGPU/GlobalISel: Don't use legal v2s16 G_BUILD_VECTOR If we have s_pack_* instructions, legalize this to G_BUILD_VECTOR_TRUNC from s32 elements. This is closer to how how the s_pack_* instructions really behave. If we don't have s_pack_ instructions, expand this by creating a merge to s32 and bitcasting. This expands to the expected bit operations. I think this eventually should go in a new bitcast legalize action type in LegalizerHelper. We already directly emit the shift operations in RegBankSelect for the vector case. This could possibly be cleaned up, but I also may want to defer doing this expansion to selection anyway. I'll see about that when I try to actually match VOP3P instructions. This breaks the selection of the build_vector since tablegen doesn't know how to match G_BUILD_VECTOR_TRUNC yet, so just xfail it for now.
2020-01-05 04:35:26 +08:00
; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C]]
AMDGPU/GlobalISel: Fix legality for G_BUILD_VECTOR llvm-svn: 365575
2019-07-10 06:48:04 +08:00
; GFX9: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP2]](s1)
AMDGPU/GlobalISel: Don't use legal v2s16 G_BUILD_VECTOR If we have s_pack_* instructions, legalize this to G_BUILD_VECTOR_TRUNC from s32 elements. This is closer to how how the s_pack_* instructions really behave. If we don't have s_pack_ instructions, expand this by creating a merge to s32 and bitcasting. This expands to the expected bit operations. I think this eventually should go in a new bitcast legalize action type in LegalizerHelper. We already directly emit the shift operations in RegBankSelect for the vector case. This could possibly be cleaned up, but I also may want to defer doing this expansion to selection anyway. I'll see about that when I try to actually match VOP3P instructions. This breaks the selection of the build_vector since tablegen doesn't know how to match G_BUILD_VECTOR_TRUNC yet, so just xfail it for now.
2020-01-05 04:35:26 +08:00
; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ANYEXT2]], [[C]]
AMDGPU/GlobalISel: Fix legality for G_BUILD_VECTOR llvm-svn: 365575
2019-07-10 06:48:04 +08:00
; GFX9: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP3]](s1)
AMDGPU/GlobalISel: Don't use legal v2s16 G_BUILD_VECTOR If we have s_pack_* instructions, legalize this to G_BUILD_VECTOR_TRUNC from s32 elements. This is closer to how how the s_pack_* instructions really behave. If we don't have s_pack_ instructions, expand this by creating a merge to s32 and bitcasting. This expands to the expected bit operations. I think this eventually should go in a new bitcast legalize action type in LegalizerHelper. We already directly emit the shift operations in RegBankSelect for the vector case. This could possibly be cleaned up, but I also may want to defer doing this expansion to selection anyway. I'll see about that when I try to actually match VOP3P instructions. This breaks the selection of the build_vector since tablegen doesn't know how to match G_BUILD_VECTOR_TRUNC yet, so just xfail it for now.
2020-01-05 04:35:26 +08:00
; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ANYEXT3]], [[C]]
AMDGPU/GlobalISel: Fix legality for G_BUILD_VECTOR llvm-svn: 365575
2019-07-10 06:48:04 +08:00
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[AND]](s32), [[AND1]](s32), [[AND2]](s32), [[AND3]](s32)
; GFX9: S_NOP 0, implicit [[BUILD_VECTOR]](<4 x s32>)
GlobalISel: Support fewerElementsVector for icmp/fcmp Also legalize 64-bit compares for AMDGPU llvm-svn: 352157
2019-01-25 10:59:34 +08:00
%0:_(p1) = G_IMPLICIT_DEF
CodeGen: Print/parse LLTs in MachineMemOperands This will currently accept the old number of bytes syntax, and convert it to a scalar. This should be removed in the near future (I think I converted all of the tests already, but likely missed a few). Not sure what the exact syntax and policy should be. We can continue printing the number of bytes for non-generic instructions to avoid test churn and only allow non-scalar types for generic instructions. This will currently print the LLT in parentheses, but accept parsing the existing integers and implicitly converting to scalar. The parentheses are a bit ugly, but the parser logic seems unable to deal without either parentheses or some keyword to indicate the start of a type.
2021-05-20 10:25:51 +08:00
%1:_(<4 x s32>) = G_LOAD %0 :: (volatile load (<4 x s32>))
GlobalISel: Support fewerElementsVector for icmp/fcmp Also legalize 64-bit compares for AMDGPU llvm-svn: 352157
2019-01-25 10:59:34 +08:00
%2:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%3:_(<4 x s1>) = G_ICMP intpred(ne), %1, %2
AMDGPU/GlobalISel: Fix legality for G_BUILD_VECTOR llvm-svn: 365575
2019-07-10 06:48:04 +08:00
%4:_(<4 x s32>) = G_ZEXT %3
S_NOP 0, implicit %4
GlobalISel: Support fewerElementsVector for icmp/fcmp Also legalize 64-bit compares for AMDGPU llvm-svn: 352157
2019-01-25 10:59:34 +08:00
...
AMDGPU/GlobalISel: Legalize icmp for pointer types llvm-svn: 352976
2019-02-03 07:35:15 +08:00
---
name: test_icmp_p0
body: |
AMDGPU/GlobalISel: Make s16 G_ICMP legal llvm-svn: 365486
2019-07-09 22:10:43 +08:00
bb.0:
AMDGPU/GlobalISel: Legalize icmp for pointer types llvm-svn: 352976
2019-02-03 07:35:15 +08:00
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
AMDGPU/GlobalISel: Make s16 G_ICMP legal llvm-svn: 365486
2019-07-09 22:10:43 +08:00
; GFX7-LABEL: name: test_icmp_p0
; GFX7: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; GFX7: [[COPY1:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; GFX7: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](p0), [[COPY1]]
; GFX7: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
; GFX7: $vgpr0 = COPY [[SEXT]](s32)
; GFX8-LABEL: name: test_icmp_p0
; GFX8: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; GFX8: [[COPY1:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; GFX8: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](p0), [[COPY1]]
; GFX8: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
; GFX8: $vgpr0 = COPY [[SEXT]](s32)
; GFX9-LABEL: name: test_icmp_p0
; GFX9: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; GFX9: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](p0), [[COPY1]]
; GFX9: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
; GFX9: $vgpr0 = COPY [[SEXT]](s32)
AMDGPU/GlobalISel: Legalize icmp for pointer types llvm-svn: 352976
2019-02-03 07:35:15 +08:00
%0:_(p0) = COPY $vgpr0_vgpr1
%1:_(p0) = COPY $vgpr0_vgpr1
%2:_(s1) = G_ICMP intpred(ne), %0, %1
%3:_(s32) = G_SEXT %2
$vgpr0 = COPY %3
...
---
name: test_icmp_p1
body: |
AMDGPU/GlobalISel: Make s16 G_ICMP legal llvm-svn: 365486
2019-07-09 22:10:43 +08:00
bb.0:
AMDGPU/GlobalISel: Legalize icmp for pointer types llvm-svn: 352976
2019-02-03 07:35:15 +08:00
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
AMDGPU/GlobalISel: Make s16 G_ICMP legal llvm-svn: 365486
2019-07-09 22:10:43 +08:00
; GFX7-LABEL: name: test_icmp_p1
; GFX7: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX7: [[COPY1:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX7: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](p1), [[COPY1]]
; GFX7: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
; GFX7: $vgpr0 = COPY [[SEXT]](s32)
; GFX8-LABEL: name: test_icmp_p1
; GFX8: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX8: [[COPY1:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX8: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](p1), [[COPY1]]
; GFX8: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
; GFX8: $vgpr0 = COPY [[SEXT]](s32)
; GFX9-LABEL: name: test_icmp_p1
; GFX9: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](p1), [[COPY1]]
; GFX9: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
; GFX9: $vgpr0 = COPY [[SEXT]](s32)
AMDGPU/GlobalISel: Legalize icmp for pointer types llvm-svn: 352976
2019-02-03 07:35:15 +08:00
%0:_(p1) = COPY $vgpr0_vgpr1
%1:_(p1) = COPY $vgpr0_vgpr1
%2:_(s1) = G_ICMP intpred(ne), %0, %1
%3:_(s32) = G_SEXT %2
$vgpr0 = COPY %3
...
---
name: test_icmp_p2
body: |
AMDGPU/GlobalISel: Make s16 G_ICMP legal llvm-svn: 365486
2019-07-09 22:10:43 +08:00
bb.0:
AMDGPU/GlobalISel: Legalize icmp for pointer types llvm-svn: 352976
2019-02-03 07:35:15 +08:00
liveins: $vgpr0, $vgpr1
AMDGPU/GlobalISel: Make s16 G_ICMP legal llvm-svn: 365486
2019-07-09 22:10:43 +08:00
; GFX7-LABEL: name: test_icmp_p2
; GFX7: [[COPY:%[0-9]+]]:_(p2) = COPY $vgpr0
; GFX7: [[COPY1:%[0-9]+]]:_(p2) = COPY $vgpr1
; GFX7: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](p2), [[COPY1]]
; GFX7: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
; GFX7: $vgpr0 = COPY [[SEXT]](s32)
; GFX8-LABEL: name: test_icmp_p2
; GFX8: [[COPY:%[0-9]+]]:_(p2) = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:_(p2) = COPY $vgpr1
; GFX8: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](p2), [[COPY1]]
; GFX8: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
; GFX8: $vgpr0 = COPY [[SEXT]](s32)
; GFX9-LABEL: name: test_icmp_p2
; GFX9: [[COPY:%[0-9]+]]:_(p2) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(p2) = COPY $vgpr1
; GFX9: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](p2), [[COPY1]]
; GFX9: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
; GFX9: $vgpr0 = COPY [[SEXT]](s32)
AMDGPU/GlobalISel: Legalize icmp for pointer types llvm-svn: 352976
2019-02-03 07:35:15 +08:00
%0:_(p2) = COPY $vgpr0
%1:_(p2) = COPY $vgpr1
%2:_(s1) = G_ICMP intpred(ne), %0, %1
%3:_(s32) = G_SEXT %2
$vgpr0 = COPY %3
...
---
name: test_icmp_p3
body: |
AMDGPU/GlobalISel: Make s16 G_ICMP legal llvm-svn: 365486
2019-07-09 22:10:43 +08:00
bb.0:
AMDGPU/GlobalISel: Legalize icmp for pointer types llvm-svn: 352976
2019-02-03 07:35:15 +08:00
liveins: $vgpr0, $vgpr1
AMDGPU/GlobalISel: Make s16 G_ICMP legal llvm-svn: 365486
2019-07-09 22:10:43 +08:00
; GFX7-LABEL: name: test_icmp_p3
; GFX7: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX7: [[COPY1:%[0-9]+]]:_(p3) = COPY $vgpr1
; GFX7: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](p3), [[COPY1]]
; GFX7: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
; GFX7: $vgpr0 = COPY [[SEXT]](s32)
; GFX8-LABEL: name: test_icmp_p3
; GFX8: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:_(p3) = COPY $vgpr1
; GFX8: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](p3), [[COPY1]]
; GFX8: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
; GFX8: $vgpr0 = COPY [[SEXT]](s32)
; GFX9-LABEL: name: test_icmp_p3
; GFX9: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(p3) = COPY $vgpr1
; GFX9: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](p3), [[COPY1]]
; GFX9: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
; GFX9: $vgpr0 = COPY [[SEXT]](s32)
AMDGPU/GlobalISel: Legalize icmp for pointer types llvm-svn: 352976
2019-02-03 07:35:15 +08:00
%0:_(p3) = COPY $vgpr0
%1:_(p3) = COPY $vgpr1
%2:_(s1) = G_ICMP intpred(ne), %0, %1
%3:_(s32) = G_SEXT %2
$vgpr0 = COPY %3
...
---
name: test_icmp_p4
body: |
AMDGPU/GlobalISel: Make s16 G_ICMP legal llvm-svn: 365486
2019-07-09 22:10:43 +08:00
bb.0:
AMDGPU/GlobalISel: Legalize icmp for pointer types llvm-svn: 352976
2019-02-03 07:35:15 +08:00
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
AMDGPU/GlobalISel: Make s16 G_ICMP legal llvm-svn: 365486
2019-07-09 22:10:43 +08:00
; GFX7-LABEL: name: test_icmp_p4
; GFX7: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; GFX7: [[COPY1:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; GFX7: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](p4), [[COPY1]]
; GFX7: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
; GFX7: $vgpr0 = COPY [[SEXT]](s32)
; GFX8-LABEL: name: test_icmp_p4
; GFX8: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; GFX8: [[COPY1:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; GFX8: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](p4), [[COPY1]]
; GFX8: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
; GFX8: $vgpr0 = COPY [[SEXT]](s32)
; GFX9-LABEL: name: test_icmp_p4
; GFX9: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; GFX9: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](p4), [[COPY1]]
; GFX9: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
; GFX9: $vgpr0 = COPY [[SEXT]](s32)
AMDGPU/GlobalISel: Legalize icmp for pointer types llvm-svn: 352976
2019-02-03 07:35:15 +08:00
%0:_(p4) = COPY $vgpr0_vgpr1
%1:_(p4) = COPY $vgpr0_vgpr1
%2:_(s1) = G_ICMP intpred(ne), %0, %1
%3:_(s32) = G_SEXT %2
$vgpr0 = COPY %3
...
---
name: test_icmp_p5
body: |
AMDGPU/GlobalISel: Make s16 G_ICMP legal llvm-svn: 365486
2019-07-09 22:10:43 +08:00
bb.0:
AMDGPU/GlobalISel: Legalize icmp for pointer types llvm-svn: 352976
2019-02-03 07:35:15 +08:00
liveins: $vgpr0, $vgpr1
AMDGPU/GlobalISel: Make s16 G_ICMP legal llvm-svn: 365486
2019-07-09 22:10:43 +08:00
; GFX7-LABEL: name: test_icmp_p5
; GFX7: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; GFX7: [[COPY1:%[0-9]+]]:_(p5) = COPY $vgpr1
; GFX7: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](p5), [[COPY1]]
; GFX7: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
; GFX7: $vgpr0 = COPY [[SEXT]](s32)
; GFX8-LABEL: name: test_icmp_p5
; GFX8: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:_(p5) = COPY $vgpr1
; GFX8: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](p5), [[COPY1]]
; GFX8: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
; GFX8: $vgpr0 = COPY [[SEXT]](s32)
; GFX9-LABEL: name: test_icmp_p5
; GFX9: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(p5) = COPY $vgpr1
; GFX9: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](p5), [[COPY1]]
; GFX9: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
; GFX9: $vgpr0 = COPY [[SEXT]](s32)
AMDGPU/GlobalISel: Legalize icmp for pointer types llvm-svn: 352976
2019-02-03 07:35:15 +08:00
%0:_(p5) = COPY $vgpr0
%1:_(p5) = COPY $vgpr1
%2:_(s1) = G_ICMP intpred(ne), %0, %1
%3:_(s32) = G_SEXT %2
$vgpr0 = COPY %3
...
---
name: test_icmp_p999
body: |
AMDGPU/GlobalISel: Make s16 G_ICMP legal llvm-svn: 365486
2019-07-09 22:10:43 +08:00
bb.0:
AMDGPU/GlobalISel: Legalize icmp for pointer types llvm-svn: 352976
2019-02-03 07:35:15 +08:00
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
AMDGPU/GlobalISel: Make s16 G_ICMP legal llvm-svn: 365486
2019-07-09 22:10:43 +08:00
; GFX7-LABEL: name: test_icmp_p999
; GFX7: [[COPY:%[0-9]+]]:_(p999) = COPY $vgpr0_vgpr1
; GFX7: [[COPY1:%[0-9]+]]:_(p999) = COPY $vgpr0_vgpr1
; GFX7: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](p999), [[COPY1]]
; GFX7: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
; GFX7: $vgpr0 = COPY [[SEXT]](s32)
; GFX8-LABEL: name: test_icmp_p999
; GFX8: [[COPY:%[0-9]+]]:_(p999) = COPY $vgpr0_vgpr1
; GFX8: [[COPY1:%[0-9]+]]:_(p999) = COPY $vgpr0_vgpr1
; GFX8: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](p999), [[COPY1]]
; GFX8: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
; GFX8: $vgpr0 = COPY [[SEXT]](s32)
; GFX9-LABEL: name: test_icmp_p999
; GFX9: [[COPY:%[0-9]+]]:_(p999) = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:_(p999) = COPY $vgpr0_vgpr1
; GFX9: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](p999), [[COPY1]]
; GFX9: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
; GFX9: $vgpr0 = COPY [[SEXT]](s32)
AMDGPU/GlobalISel: Legalize icmp for pointer types llvm-svn: 352976
2019-02-03 07:35:15 +08:00
%0:_(p999) = COPY $vgpr0_vgpr1
%1:_(p999) = COPY $vgpr0_vgpr1
%2:_(s1) = G_ICMP intpred(ne), %0, %1
%3:_(s32) = G_SEXT %2
$vgpr0 = COPY %3
...
---
name: test_icmp_v2p3
body: |
AMDGPU/GlobalISel: Make s16 G_ICMP legal llvm-svn: 365486
2019-07-09 22:10:43 +08:00
bb.0:
AMDGPU/GlobalISel: Legalize icmp for pointer types llvm-svn: 352976
2019-02-03 07:35:15 +08:00
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
AMDGPU/GlobalISel: Make s16 G_ICMP legal llvm-svn: 365486
2019-07-09 22:10:43 +08:00
; GFX7-LABEL: name: test_icmp_v2p3
; GFX7: [[COPY:%[0-9]+]]:_(<2 x p3>) = COPY $vgpr0_vgpr1
; GFX7: [[COPY1:%[0-9]+]]:_(<2 x p3>) = COPY $vgpr0_vgpr1
; GFX7: [[UV:%[0-9]+]]:_(p3), [[UV1:%[0-9]+]]:_(p3) = G_UNMERGE_VALUES [[COPY]](<2 x p3>)
; GFX7: [[UV2:%[0-9]+]]:_(p3), [[UV3:%[0-9]+]]:_(p3) = G_UNMERGE_VALUES [[COPY1]](<2 x p3>)
; GFX7: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV]](p3), [[UV2]]
; GFX7: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV1]](p3), [[UV3]]
AMDGPU/GlobalISel: Fix legality for G_BUILD_VECTOR llvm-svn: 365575
2019-07-10 06:48:04 +08:00
; GFX7: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1)
; GFX7: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP1]](s1)
[GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner When Src and Dst used in buildAnyExtOrTrunc or buildSExtOrTrunc have the same type (creates COPY) use Src register directly or use replaceRegOrBuildCopy instead. Differential Revision: https://reviews.llvm.org/D108306
2021-08-24 17:09:37 +08:00
; GFX7: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ANYEXT]], 1
; GFX7: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ANYEXT1]], 1
AMDGPU/GlobalISel: Legalize G_SEXT_INREG Split the VALU 64-bit case in RegBankSelect.
2020-02-05 05:06:34 +08:00
; GFX7: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32)
AMDGPU/GlobalISel: Make s16 G_ICMP legal llvm-svn: 365486
2019-07-09 22:10:43 +08:00
; GFX7: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
; GFX8-LABEL: name: test_icmp_v2p3
; GFX8: [[COPY:%[0-9]+]]:_(<2 x p3>) = COPY $vgpr0_vgpr1
; GFX8: [[COPY1:%[0-9]+]]:_(<2 x p3>) = COPY $vgpr0_vgpr1
; GFX8: [[UV:%[0-9]+]]:_(p3), [[UV1:%[0-9]+]]:_(p3) = G_UNMERGE_VALUES [[COPY]](<2 x p3>)
; GFX8: [[UV2:%[0-9]+]]:_(p3), [[UV3:%[0-9]+]]:_(p3) = G_UNMERGE_VALUES [[COPY1]](<2 x p3>)
; GFX8: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV]](p3), [[UV2]]
; GFX8: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV1]](p3), [[UV3]]
AMDGPU/GlobalISel: Fix legality for G_BUILD_VECTOR llvm-svn: 365575
2019-07-10 06:48:04 +08:00
; GFX8: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1)
; GFX8: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP1]](s1)
[GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner When Src and Dst used in buildAnyExtOrTrunc or buildSExtOrTrunc have the same type (creates COPY) use Src register directly or use replaceRegOrBuildCopy instead. Differential Revision: https://reviews.llvm.org/D108306
2021-08-24 17:09:37 +08:00
; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ANYEXT]], 1
; GFX8: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ANYEXT1]], 1
AMDGPU/GlobalISel: Legalize G_SEXT_INREG Split the VALU 64-bit case in RegBankSelect.
2020-02-05 05:06:34 +08:00
; GFX8: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32)
AMDGPU/GlobalISel: Make s16 G_ICMP legal llvm-svn: 365486
2019-07-09 22:10:43 +08:00
; GFX8: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
; GFX9-LABEL: name: test_icmp_v2p3
; GFX9: [[COPY:%[0-9]+]]:_(<2 x p3>) = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:_(<2 x p3>) = COPY $vgpr0_vgpr1
; GFX9: [[UV:%[0-9]+]]:_(p3), [[UV1:%[0-9]+]]:_(p3) = G_UNMERGE_VALUES [[COPY]](<2 x p3>)
; GFX9: [[UV2:%[0-9]+]]:_(p3), [[UV3:%[0-9]+]]:_(p3) = G_UNMERGE_VALUES [[COPY1]](<2 x p3>)
; GFX9: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV]](p3), [[UV2]]
; GFX9: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV1]](p3), [[UV3]]
AMDGPU/GlobalISel: Fix legality for G_BUILD_VECTOR llvm-svn: 365575
2019-07-10 06:48:04 +08:00
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1)
AMDGPU/GlobalISel: Don't use legal v2s16 G_BUILD_VECTOR If we have s_pack_* instructions, legalize this to G_BUILD_VECTOR_TRUNC from s32 elements. This is closer to how how the s_pack_* instructions really behave. If we don't have s_pack_ instructions, expand this by creating a merge to s32 and bitcasting. This expands to the expected bit operations. I think this eventually should go in a new bitcast legalize action type in LegalizerHelper. We already directly emit the shift operations in RegBankSelect for the vector case. This could possibly be cleaned up, but I also may want to defer doing this expansion to selection anyway. I'll see about that when I try to actually match VOP3P instructions. This breaks the selection of the build_vector since tablegen doesn't know how to match G_BUILD_VECTOR_TRUNC yet, so just xfail it for now.
2020-01-05 04:35:26 +08:00
; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ANYEXT]], 1
AMDGPU/GlobalISel: Fix legality for G_BUILD_VECTOR llvm-svn: 365575
2019-07-10 06:48:04 +08:00
; GFX9: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP1]](s1)
AMDGPU/GlobalISel: Don't use legal v2s16 G_BUILD_VECTOR If we have s_pack_* instructions, legalize this to G_BUILD_VECTOR_TRUNC from s32 elements. This is closer to how how the s_pack_* instructions really behave. If we don't have s_pack_ instructions, expand this by creating a merge to s32 and bitcasting. This expands to the expected bit operations. I think this eventually should go in a new bitcast legalize action type in LegalizerHelper. We already directly emit the shift operations in RegBankSelect for the vector case. This could possibly be cleaned up, but I also may want to defer doing this expansion to selection anyway. I'll see about that when I try to actually match VOP3P instructions. This breaks the selection of the build_vector since tablegen doesn't know how to match G_BUILD_VECTOR_TRUNC yet, so just xfail it for now.
2020-01-05 04:35:26 +08:00
; GFX9: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ANYEXT1]], 1
AMDGPU/GlobalISel: Legalize G_SEXT_INREG Split the VALU 64-bit case in RegBankSelect.
2020-02-05 05:06:34 +08:00
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32)
AMDGPU/GlobalISel: Make s16 G_ICMP legal llvm-svn: 365486
2019-07-09 22:10:43 +08:00
; GFX9: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
AMDGPU/GlobalISel: Legalize icmp for pointer types llvm-svn: 352976
2019-02-03 07:35:15 +08:00
%0:_(<2 x p3>) = COPY $vgpr0_vgpr1
%1:_(<2 x p3>) = COPY $vgpr0_vgpr1
%2:_(<2 x s1>) = G_ICMP intpred(ne), %0, %1
%3:_(<2 x s32>) = G_SEXT %2
$vgpr0_vgpr1 = COPY %3
...
---
name: test_icmp_v2p999
body: |
AMDGPU/GlobalISel: Make s16 G_ICMP legal llvm-svn: 365486
2019-07-09 22:10:43 +08:00
bb.0:
AMDGPU/GlobalISel: Legalize icmp for pointer types llvm-svn: 352976
2019-02-03 07:35:15 +08:00
liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7
AMDGPU/GlobalISel: Make s16 G_ICMP legal llvm-svn: 365486
2019-07-09 22:10:43 +08:00
; GFX7-LABEL: name: test_icmp_v2p999
; GFX7: [[COPY:%[0-9]+]]:_(<2 x p999>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; GFX7: [[COPY1:%[0-9]+]]:_(<2 x p999>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
; GFX7: [[UV:%[0-9]+]]:_(p999), [[UV1:%[0-9]+]]:_(p999) = G_UNMERGE_VALUES [[COPY]](<2 x p999>)
; GFX7: [[UV2:%[0-9]+]]:_(p999), [[UV3:%[0-9]+]]:_(p999) = G_UNMERGE_VALUES [[COPY1]](<2 x p999>)
; GFX7: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV]](p999), [[UV2]]
; GFX7: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV1]](p999), [[UV3]]
AMDGPU/GlobalISel: Fix legality for G_BUILD_VECTOR llvm-svn: 365575
2019-07-10 06:48:04 +08:00
; GFX7: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1)
; GFX7: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP1]](s1)
[GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner When Src and Dst used in buildAnyExtOrTrunc or buildSExtOrTrunc have the same type (creates COPY) use Src register directly or use replaceRegOrBuildCopy instead. Differential Revision: https://reviews.llvm.org/D108306
2021-08-24 17:09:37 +08:00
; GFX7: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ANYEXT]], 1
; GFX7: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ANYEXT1]], 1
AMDGPU/GlobalISel: Legalize G_SEXT_INREG Split the VALU 64-bit case in RegBankSelect.
2020-02-05 05:06:34 +08:00
; GFX7: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32)
AMDGPU/GlobalISel: Make s16 G_ICMP legal llvm-svn: 365486
2019-07-09 22:10:43 +08:00
; GFX7: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
; GFX8-LABEL: name: test_icmp_v2p999
; GFX8: [[COPY:%[0-9]+]]:_(<2 x p999>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; GFX8: [[COPY1:%[0-9]+]]:_(<2 x p999>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
; GFX8: [[UV:%[0-9]+]]:_(p999), [[UV1:%[0-9]+]]:_(p999) = G_UNMERGE_VALUES [[COPY]](<2 x p999>)
; GFX8: [[UV2:%[0-9]+]]:_(p999), [[UV3:%[0-9]+]]:_(p999) = G_UNMERGE_VALUES [[COPY1]](<2 x p999>)
; GFX8: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV]](p999), [[UV2]]
; GFX8: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV1]](p999), [[UV3]]
AMDGPU/GlobalISel: Fix legality for G_BUILD_VECTOR llvm-svn: 365575
2019-07-10 06:48:04 +08:00
; GFX8: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1)
; GFX8: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP1]](s1)
[GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner When Src and Dst used in buildAnyExtOrTrunc or buildSExtOrTrunc have the same type (creates COPY) use Src register directly or use replaceRegOrBuildCopy instead. Differential Revision: https://reviews.llvm.org/D108306
2021-08-24 17:09:37 +08:00
; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ANYEXT]], 1
; GFX8: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ANYEXT1]], 1
AMDGPU/GlobalISel: Legalize G_SEXT_INREG Split the VALU 64-bit case in RegBankSelect.
2020-02-05 05:06:34 +08:00
; GFX8: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32)
AMDGPU/GlobalISel: Make s16 G_ICMP legal llvm-svn: 365486
2019-07-09 22:10:43 +08:00
; GFX8: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
; GFX9-LABEL: name: test_icmp_v2p999
; GFX9: [[COPY:%[0-9]+]]:_(<2 x p999>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; GFX9: [[COPY1:%[0-9]+]]:_(<2 x p999>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
; GFX9: [[UV:%[0-9]+]]:_(p999), [[UV1:%[0-9]+]]:_(p999) = G_UNMERGE_VALUES [[COPY]](<2 x p999>)
; GFX9: [[UV2:%[0-9]+]]:_(p999), [[UV3:%[0-9]+]]:_(p999) = G_UNMERGE_VALUES [[COPY1]](<2 x p999>)
; GFX9: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV]](p999), [[UV2]]
; GFX9: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV1]](p999), [[UV3]]
AMDGPU/GlobalISel: Fix legality for G_BUILD_VECTOR llvm-svn: 365575
2019-07-10 06:48:04 +08:00
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1)
AMDGPU/GlobalISel: Don't use legal v2s16 G_BUILD_VECTOR If we have s_pack_* instructions, legalize this to G_BUILD_VECTOR_TRUNC from s32 elements. This is closer to how how the s_pack_* instructions really behave. If we don't have s_pack_ instructions, expand this by creating a merge to s32 and bitcasting. This expands to the expected bit operations. I think this eventually should go in a new bitcast legalize action type in LegalizerHelper. We already directly emit the shift operations in RegBankSelect for the vector case. This could possibly be cleaned up, but I also may want to defer doing this expansion to selection anyway. I'll see about that when I try to actually match VOP3P instructions. This breaks the selection of the build_vector since tablegen doesn't know how to match G_BUILD_VECTOR_TRUNC yet, so just xfail it for now.
2020-01-05 04:35:26 +08:00
; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ANYEXT]], 1
AMDGPU/GlobalISel: Fix legality for G_BUILD_VECTOR llvm-svn: 365575
2019-07-10 06:48:04 +08:00
; GFX9: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP1]](s1)
AMDGPU/GlobalISel: Don't use legal v2s16 G_BUILD_VECTOR If we have s_pack_* instructions, legalize this to G_BUILD_VECTOR_TRUNC from s32 elements. This is closer to how how the s_pack_* instructions really behave. If we don't have s_pack_ instructions, expand this by creating a merge to s32 and bitcasting. This expands to the expected bit operations. I think this eventually should go in a new bitcast legalize action type in LegalizerHelper. We already directly emit the shift operations in RegBankSelect for the vector case. This could possibly be cleaned up, but I also may want to defer doing this expansion to selection anyway. I'll see about that when I try to actually match VOP3P instructions. This breaks the selection of the build_vector since tablegen doesn't know how to match G_BUILD_VECTOR_TRUNC yet, so just xfail it for now.
2020-01-05 04:35:26 +08:00
; GFX9: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ANYEXT1]], 1
AMDGPU/GlobalISel: Legalize G_SEXT_INREG Split the VALU 64-bit case in RegBankSelect.
2020-02-05 05:06:34 +08:00
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32)
AMDGPU/GlobalISel: Make s16 G_ICMP legal llvm-svn: 365486
2019-07-09 22:10:43 +08:00
; GFX9: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
AMDGPU/GlobalISel: Legalize icmp for pointer types llvm-svn: 352976
2019-02-03 07:35:15 +08:00
%0:_(<2 x p999>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(<2 x p999>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
%2:_(<2 x s1>) = G_ICMP intpred(ne), %0, %1
%3:_(<2 x s32>) = G_SEXT %2
$vgpr0_vgpr1 = COPY %3
...
AMDGPU/GlobalISel: Make s16 G_ICMP legal llvm-svn: 365486
2019-07-09 22:10:43 +08:00
---
name: test_icmp_v2s16
body: |
bb.0:
liveins: $vgpr0, $vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
; GFX7-LABEL: name: test_icmp_v2s16
; GFX7: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
; GFX7: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
; GFX7: [[COPY2:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
; GFX7: [[COPY3:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr4_vgpr5
GlobalISel: Lower scalarizing unmerge of a vector to shifts AMDGPU sometimes has legal s16 and <2 x s16> operations, but all registers are really 32-bit. An unmerge destination really should ben widened to a 32-bit register. If widening a scalarizing vector with a target size that matches the vector size, bitcast to integer and extract the relevant bits with shifts. I'm not sure if this is the right place for this. This could arguably be part of widenScalar for the result. I also have a growing feeling that we're missing a bitcast legalize action. llvm-svn: 367604
2019-08-02 03:10:05 +08:00
; GFX7: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; GFX7: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX7: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; GFX7: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
; GFX7: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; GFX7: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
[GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner When Src and Dst used in buildAnyExtOrTrunc or buildSExtOrTrunc have the same type (creates COPY) use Src register directly or use replaceRegOrBuildCopy instead. Differential Revision: https://reviews.llvm.org/D108306
2021-08-24 17:09:37 +08:00
; GFX7: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
; GFX7: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
GlobalISel: Lower scalarizing unmerge of a vector to shifts AMDGPU sometimes has legal s16 and <2 x s16> operations, but all registers are really 32-bit. An unmerge destination really should ben widened to a 32-bit register. If widening a scalarizing vector with a target size that matches the vector size, bitcast to integer and extract the relevant bits with shifts. I'm not sure if this is the right place for this. This could arguably be part of widenScalar for the result. I also have a growing feeling that we're missing a bitcast legalize action. llvm-svn: 367604
2019-08-02 03:10:05 +08:00
; GFX7: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[AND]](s32), [[AND1]]
[GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner When Src and Dst used in buildAnyExtOrTrunc or buildSExtOrTrunc have the same type (creates COPY) use Src register directly or use replaceRegOrBuildCopy instead. Differential Revision: https://reviews.llvm.org/D108306
2021-08-24 17:09:37 +08:00
; GFX7: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
; GFX7: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
GlobalISel: Lower scalarizing unmerge of a vector to shifts AMDGPU sometimes has legal s16 and <2 x s16> operations, but all registers are really 32-bit. An unmerge destination really should ben widened to a 32-bit register. If widening a scalarizing vector with a target size that matches the vector size, bitcast to integer and extract the relevant bits with shifts. I'm not sure if this is the right place for this. This could arguably be part of widenScalar for the result. I also have a growing feeling that we're missing a bitcast legalize action. llvm-svn: 367604
2019-08-02 03:10:05 +08:00
; GFX7: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[AND2]](s32), [[AND3]]
; GFX7: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY2]](<2 x s32>)
; GFX7: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY3]](<2 x s32>)
; GFX7: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[UV]], [[UV2]]
; GFX7: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[UV1]], [[UV3]]
AMDGPU/GlobalISel: Make s16 G_ICMP legal llvm-svn: 365486
2019-07-09 22:10:43 +08:00
; GFX7: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SELECT]](s32), [[SELECT1]](s32)
; GFX7: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
; GFX8-LABEL: name: test_icmp_v2s16
; GFX8: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
; GFX8: [[COPY2:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
; GFX8: [[COPY3:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr4_vgpr5
GlobalISel: Lower scalarizing unmerge of a vector to shifts AMDGPU sometimes has legal s16 and <2 x s16> operations, but all registers are really 32-bit. An unmerge destination really should ben widened to a 32-bit register. If widening a scalarizing vector with a target size that matches the vector size, bitcast to integer and extract the relevant bits with shifts. I'm not sure if this is the right place for this. This could arguably be part of widenScalar for the result. I also have a growing feeling that we're missing a bitcast legalize action. llvm-svn: 367604
2019-08-02 03:10:05 +08:00
; GFX8: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; GFX8: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX8: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; GFX8: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; GFX8: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
; GFX8: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST1]](s32)
; GFX8: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; GFX8: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](s32)
; GFX8: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[TRUNC]](s16), [[TRUNC2]]
; GFX8: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[TRUNC1]](s16), [[TRUNC3]]
; GFX8: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY2]](<2 x s32>)
; GFX8: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY3]](<2 x s32>)
; GFX8: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[UV]], [[UV2]]
; GFX8: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[UV1]], [[UV3]]
AMDGPU/GlobalISel: Make s16 G_ICMP legal llvm-svn: 365486
2019-07-09 22:10:43 +08:00
; GFX8: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SELECT]](s32), [[SELECT1]](s32)
; GFX8: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
; GFX9-LABEL: name: test_icmp_v2s16
; GFX9: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
; GFX9: [[COPY2:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
; GFX9: [[COPY3:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr4_vgpr5
GlobalISel: Lower scalarizing unmerge of a vector to shifts AMDGPU sometimes has legal s16 and <2 x s16> operations, but all registers are really 32-bit. An unmerge destination really should ben widened to a 32-bit register. If widening a scalarizing vector with a target size that matches the vector size, bitcast to integer and extract the relevant bits with shifts. I'm not sure if this is the right place for this. This could arguably be part of widenScalar for the result. I also have a growing feeling that we're missing a bitcast legalize action. llvm-svn: 367604
2019-08-02 03:10:05 +08:00
; GFX9: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; GFX9: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
; GFX9: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST1]](s32)
; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; GFX9: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](s32)
; GFX9: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[TRUNC]](s16), [[TRUNC2]]
; GFX9: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[TRUNC1]](s16), [[TRUNC3]]
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY2]](<2 x s32>)
; GFX9: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY3]](<2 x s32>)
; GFX9: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[UV]], [[UV2]]
; GFX9: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[UV1]], [[UV3]]
AMDGPU/GlobalISel: Make s16 G_ICMP legal llvm-svn: 365486
2019-07-09 22:10:43 +08:00
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SELECT]](s32), [[SELECT1]](s32)
; GFX9: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
%0:_(<2 x s16>) = COPY $vgpr0
%1:_(<2 x s16>) = COPY $vgpr1
%2:_(<2 x s32>) = COPY $vgpr2_vgpr3
%3:_(<2 x s32>) = COPY $vgpr4_vgpr5
%4:_(<2 x s1>) = G_ICMP intpred(ne), %0, %1
%5:_(<2 x s32>) = G_SELECT %4, %2, %3
$vgpr0_vgpr1 = COPY %5
...
AMDGPU/GlobalISel: Add some missing tests for non-power-of-2 cases
2020-02-16 11:13:29 +08:00
---
name: test_icmp_s33
body: |
bb.0:
liveins: $vgpr0_vgpr1
; GFX7-LABEL: name: test_icmp_s33
; GFX7: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
[GlobalISel] Improve elimination of dead instructions in legalizer Add eraseInstr(s) utility functions. Before deleting an instruction collects its use instructions. After deletion deletes use instructions that became trivially dead. This patch clears all dead instructions in existing legalizer mir tests. Differential Revision: https://reviews.llvm.org/D109154
2021-09-20 19:00:13 +08:00
; GFX7: [[COPY:%[0-9]+]]:_(s64) = COPY [[C]](s64)
AMDGPU/GlobalISel: Add some missing tests for non-power-of-2 cases
2020-02-16 11:13:29 +08:00
; GFX7: [[COPY1:%[0-9]+]]:_(s64) = COPY [[C]](s64)
[GlobalISel] Improve elimination of dead instructions in legalizer Add eraseInstr(s) utility functions. Before deleting an instruction collects its use instructions. After deletion deletes use instructions that became trivially dead. This patch clears all dead instructions in existing legalizer mir tests. Differential Revision: https://reviews.llvm.org/D109154
2021-09-20 19:00:13 +08:00
; GFX7: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](s64), [[COPY1]]
AMDGPU/GlobalISel: Add some missing tests for non-power-of-2 cases
2020-02-16 11:13:29 +08:00
; GFX7: S_ENDPGM 0, implicit [[ICMP]](s1)
; GFX8-LABEL: name: test_icmp_s33
; GFX8: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
[GlobalISel] Improve elimination of dead instructions in legalizer Add eraseInstr(s) utility functions. Before deleting an instruction collects its use instructions. After deletion deletes use instructions that became trivially dead. This patch clears all dead instructions in existing legalizer mir tests. Differential Revision: https://reviews.llvm.org/D109154
2021-09-20 19:00:13 +08:00
; GFX8: [[COPY:%[0-9]+]]:_(s64) = COPY [[C]](s64)
AMDGPU/GlobalISel: Add some missing tests for non-power-of-2 cases
2020-02-16 11:13:29 +08:00
; GFX8: [[COPY1:%[0-9]+]]:_(s64) = COPY [[C]](s64)
[GlobalISel] Improve elimination of dead instructions in legalizer Add eraseInstr(s) utility functions. Before deleting an instruction collects its use instructions. After deletion deletes use instructions that became trivially dead. This patch clears all dead instructions in existing legalizer mir tests. Differential Revision: https://reviews.llvm.org/D109154
2021-09-20 19:00:13 +08:00
; GFX8: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](s64), [[COPY1]]
AMDGPU/GlobalISel: Add some missing tests for non-power-of-2 cases
2020-02-16 11:13:29 +08:00
; GFX8: S_ENDPGM 0, implicit [[ICMP]](s1)
; GFX9-LABEL: name: test_icmp_s33
; GFX9: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
[GlobalISel] Improve elimination of dead instructions in legalizer Add eraseInstr(s) utility functions. Before deleting an instruction collects its use instructions. After deletion deletes use instructions that became trivially dead. This patch clears all dead instructions in existing legalizer mir tests. Differential Revision: https://reviews.llvm.org/D109154
2021-09-20 19:00:13 +08:00
; GFX9: [[COPY:%[0-9]+]]:_(s64) = COPY [[C]](s64)
AMDGPU/GlobalISel: Add some missing tests for non-power-of-2 cases
2020-02-16 11:13:29 +08:00
; GFX9: [[COPY1:%[0-9]+]]:_(s64) = COPY [[C]](s64)
[GlobalISel] Improve elimination of dead instructions in legalizer Add eraseInstr(s) utility functions. Before deleting an instruction collects its use instructions. After deletion deletes use instructions that became trivially dead. This patch clears all dead instructions in existing legalizer mir tests. Differential Revision: https://reviews.llvm.org/D109154
2021-09-20 19:00:13 +08:00
; GFX9: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](s64), [[COPY1]]
AMDGPU/GlobalISel: Add some missing tests for non-power-of-2 cases
2020-02-16 11:13:29 +08:00
; GFX9: S_ENDPGM 0, implicit [[ICMP]](s1)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s33) = G_TRUNC %0
%2:_(s33) = G_CONSTANT i33 0
%3:_(s1) = G_ICMP intpred(ne), %2, %2
S_ENDPGM 0, implicit %3
...