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llvm-project/llvm/lib/Target/PowerPC/PPCScheduleG5.td

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Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. llvm-svn: 150878
2012-02-18 20:03:15 +08:00
//===-- PPCScheduleG5.td - PPC G5 Scheduling Definitions ---*- tablegen -*-===//
//
Checking in first round of scheduling tablegen files. Not tied in as yet. llvm-svn: 23786
2005-10-19 00:23:40 +08:00
// The LLVM Compiler Infrastructure
//
Remove attribution from file headers, per discussion on llvmdev. llvm-svn: 45418
2007-12-30 04:36:04 +08:00
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. llvm-svn: 150878
2012-02-18 20:03:15 +08:00
//
Checking in first round of scheduling tablegen files. Not tied in as yet. llvm-svn: 23786
2005-10-19 00:23:40 +08:00
//===----------------------------------------------------------------------===//
//
// This file defines the itinerary class data for the G5 (970) processor.
//
//===----------------------------------------------------------------------===//
Don't share functional units among the PPC itineraries Instead of sharing functional unit names between the various PPC itineraries, give each core its own unit names prefixed with the core name. This follows the convention used by other backends (such as ARM), and removes a non-obvious ordering dependency between the various PPCSchedule*.td files. No functionality change intended. llvm-svn: 195908
2013-11-28 14:05:59 +08:00
def G5_BPU : FuncUnit; // Branch unit
def G5_SLU : FuncUnit; // Store/load unit
def G5_SRU : FuncUnit; // special register unit
def G5_IU1 : FuncUnit; // integer unit 1 (simple)
def G5_IU2 : FuncUnit; // integer unit 2 (complex)
def G5_FPU1 : FuncUnit; // floating point unit 1
def G5_FPU2 : FuncUnit; // floating point unit 2
def G5_VPU : FuncUnit; // vector permutation unit
def G5_VIU1 : FuncUnit; // vector integer unit 1 (simple)
def G5_VIU2 : FuncUnit; // vector integer unit 2 (complex)
def G5_VFPU : FuncUnit; // vector floating point unit
Make processor FUs unique for given itinerary. This extends the limit of 32 FU per CPU arch to 32 per intinerary allowing precise modelling of quite complex pipelines in the future. llvm-svn: 101754
2010-04-19 04:31:01 +08:00
def G5Itineraries : ProcessorItineraries<
Don't share functional units among the PPC itineraries Instead of sharing functional unit names between the various PPC itineraries, give each core its own unit names prefixed with the core name. This follows the convention used by other backends (such as ARM), and removes a non-obvious ordering dependency between the various PPCSchedule*.td files. No functionality change intended. llvm-svn: 195908
2013-11-28 14:05:59 +08:00
[G5_IU1, G5_IU2, G5_SLU, G5_BPU, G5_FPU1, G5_FPU2,
G5_VFPU, G5_VIU1, G5_VIU2, G5_VPU], [], [
InstrItinData<IIC_IntSimple , [InstrStage<2, [G5_IU1, G5_IU2]>]>,
InstrItinData<IIC_IntGeneral , [InstrStage<2, [G5_IU1, G5_IU2]>]>,
InstrItinData<IIC_IntCompare , [InstrStage<3, [G5_IU1, G5_IU2]>]>,
InstrItinData<IIC_IntDivD , [InstrStage<68, [G5_IU1]>]>,
InstrItinData<IIC_IntDivW , [InstrStage<36, [G5_IU1]>]>,
InstrItinData<IIC_IntMFFS , [InstrStage<6, [G5_IU2]>]>,
InstrItinData<IIC_IntMFVSCR , [InstrStage<1, [G5_VFPU]>]>,
InstrItinData<IIC_IntMTFSB0 , [InstrStage<6, [G5_FPU1, G5_FPU2]>]>,
InstrItinData<IIC_IntMulHD , [InstrStage<7, [G5_IU1, G5_IU2]>]>,
InstrItinData<IIC_IntMulHW , [InstrStage<5, [G5_IU1, G5_IU2]>]>,
InstrItinData<IIC_IntMulHWU , [InstrStage<5, [G5_IU1, G5_IU2]>]>,
InstrItinData<IIC_IntMulLI , [InstrStage<4, [G5_IU1, G5_IU2]>]>,
InstrItinData<IIC_IntRFID , [InstrStage<1, [G5_IU2]>]>,
InstrItinData<IIC_IntRotateD , [InstrStage<2, [G5_IU1, G5_IU2]>]>,
Minor code cleanups. NFC. llvm-svn: 267375
2016-04-25 09:40:54 +08:00
InstrItinData<IIC_IntRotateDI , [InstrStage<2, [G5_IU1, G5_IU2]>]>,
Don't share functional units among the PPC itineraries Instead of sharing functional unit names between the various PPC itineraries, give each core its own unit names prefixed with the core name. This follows the convention used by other backends (such as ARM), and removes a non-obvious ordering dependency between the various PPCSchedule*.td files. No functionality change intended. llvm-svn: 195908
2013-11-28 14:05:59 +08:00
InstrItinData<IIC_IntRotate , [InstrStage<4, [G5_IU1, G5_IU2]>]>,
InstrItinData<IIC_IntShift , [InstrStage<2, [G5_IU1, G5_IU2]>]>,
InstrItinData<IIC_IntTrapD , [InstrStage<1, [G5_IU1, G5_IU2]>]>,
InstrItinData<IIC_IntTrapW , [InstrStage<1, [G5_IU1, G5_IU2]>]>,
InstrItinData<IIC_BrB , [InstrStage<1, [G5_BPU]>]>,
InstrItinData<IIC_BrCR , [InstrStage<4, [G5_BPU]>]>,
InstrItinData<IIC_BrMCR , [InstrStage<2, [G5_BPU]>]>,
InstrItinData<IIC_BrMCRX , [InstrStage<3, [G5_BPU]>]>,
InstrItinData<IIC_LdStDCBF , [InstrStage<3, [G5_SLU]>]>,
InstrItinData<IIC_LdStLoad , [InstrStage<3, [G5_SLU]>]>,
Minor code cleanups. NFC. llvm-svn: 267375
2016-04-25 09:40:54 +08:00
InstrItinData<IIC_LdStLoadUpd , [InstrStage<3, [G5_SLU]>]>,
InstrItinData<IIC_LdStLoadUpdX, [InstrStage<3, [G5_SLU]>]>,
Don't share functional units among the PPC itineraries Instead of sharing functional unit names between the various PPC itineraries, give each core its own unit names prefixed with the core name. This follows the convention used by other backends (such as ARM), and removes a non-obvious ordering dependency between the various PPCSchedule*.td files. No functionality change intended. llvm-svn: 195908
2013-11-28 14:05:59 +08:00
InstrItinData<IIC_LdStStore , [InstrStage<3, [G5_SLU]>]>,
Minor code cleanups. NFC. llvm-svn: 267375
2016-04-25 09:40:54 +08:00
InstrItinData<IIC_LdStStoreUpd, [InstrStage<3, [G5_SLU]>]>,
Don't share functional units among the PPC itineraries Instead of sharing functional unit names between the various PPC itineraries, give each core its own unit names prefixed with the core name. This follows the convention used by other backends (such as ARM), and removes a non-obvious ordering dependency between the various PPCSchedule*.td files. No functionality change intended. llvm-svn: 195908
2013-11-28 14:05:59 +08:00
InstrItinData<IIC_LdStDSS , [InstrStage<10, [G5_SLU]>]>,
InstrItinData<IIC_LdStICBI , [InstrStage<40, [G5_SLU]>]>,
InstrItinData<IIC_LdStSTFD , [InstrStage<4, [G5_SLU]>]>,
Minor code cleanups. NFC. llvm-svn: 267375
2016-04-25 09:40:54 +08:00
InstrItinData<IIC_LdStSTFDU , [InstrStage<4, [G5_SLU]>]>,
Don't share functional units among the PPC itineraries Instead of sharing functional unit names between the various PPC itineraries, give each core its own unit names prefixed with the core name. This follows the convention used by other backends (such as ARM), and removes a non-obvious ordering dependency between the various PPCSchedule*.td files. No functionality change intended. llvm-svn: 195908
2013-11-28 14:05:59 +08:00
InstrItinData<IIC_LdStLD , [InstrStage<3, [G5_SLU]>]>,
InstrItinData<IIC_LdStLDU , [InstrStage<3, [G5_SLU]>]>,
Split some PPC itinerary classes In preparation for adding scheduling definitions for the POWER7, split some PPC itinerary classes so that the P7's latencies and hazards can be better described. For the most part, this means differentiating indexed from non-index pre-increment loads and stores. Also, differentiate single from double-precision sqrt. No functionality change intended (except for a more-specific latency for single-precision sqrt on the A2). llvm-svn: 195980
2013-12-01 04:41:13 +08:00
InstrItinData<IIC_LdStLDUX , [InstrStage<3, [G5_SLU]>]>,
Don't share functional units among the PPC itineraries Instead of sharing functional unit names between the various PPC itineraries, give each core its own unit names prefixed with the core name. This follows the convention used by other backends (such as ARM), and removes a non-obvious ordering dependency between the various PPCSchedule*.td files. No functionality change intended. llvm-svn: 195908
2013-11-28 14:05:59 +08:00
InstrItinData<IIC_LdStLDARX , [InstrStage<11, [G5_SLU]>]>,
InstrItinData<IIC_LdStLFD , [InstrStage<3, [G5_SLU]>]>,
InstrItinData<IIC_LdStLFDU , [InstrStage<5, [G5_SLU]>]>,
Split some PPC itinerary classes In preparation for adding scheduling definitions for the POWER7, split some PPC itinerary classes so that the P7's latencies and hazards can be better described. For the most part, this means differentiating indexed from non-index pre-increment loads and stores. Also, differentiate single from double-precision sqrt. No functionality change intended (except for a more-specific latency for single-precision sqrt on the A2). llvm-svn: 195980
2013-12-01 04:41:13 +08:00
InstrItinData<IIC_LdStLFDUX , [InstrStage<5, [G5_SLU]>]>,
Don't share functional units among the PPC itineraries Instead of sharing functional unit names between the various PPC itineraries, give each core its own unit names prefixed with the core name. This follows the convention used by other backends (such as ARM), and removes a non-obvious ordering dependency between the various PPCSchedule*.td files. No functionality change intended. llvm-svn: 195908
2013-11-28 14:05:59 +08:00
InstrItinData<IIC_LdStLHA , [InstrStage<5, [G5_SLU]>]>,
Minor code cleanups. NFC. llvm-svn: 267375
2016-04-25 09:40:54 +08:00
InstrItinData<IIC_LdStLHAU , [InstrStage<5, [G5_SLU]>]>,
InstrItinData<IIC_LdStLHAUX , [InstrStage<5, [G5_SLU]>]>,
Don't share functional units among the PPC itineraries Instead of sharing functional unit names between the various PPC itineraries, give each core its own unit names prefixed with the core name. This follows the convention used by other backends (such as ARM), and removes a non-obvious ordering dependency between the various PPCSchedule*.td files. No functionality change intended. llvm-svn: 195908
2013-11-28 14:05:59 +08:00
InstrItinData<IIC_LdStLMW , [InstrStage<64, [G5_SLU]>]>,
InstrItinData<IIC_LdStLVecX , [InstrStage<3, [G5_SLU]>]>,
InstrItinData<IIC_LdStLWA , [InstrStage<5, [G5_SLU]>]>,
InstrItinData<IIC_LdStLWARX , [InstrStage<11, [G5_SLU]>]>,
InstrItinData<IIC_LdStSLBIA , [InstrStage<40, [G5_SLU]>]>, // needs work
InstrItinData<IIC_LdStSLBIE , [InstrStage<2, [G5_SLU]>]>,
InstrItinData<IIC_LdStSTD , [InstrStage<3, [G5_SLU]>]>,
InstrItinData<IIC_LdStSTDU , [InstrStage<3, [G5_SLU]>]>,
Split some PPC itinerary classes In preparation for adding scheduling definitions for the POWER7, split some PPC itinerary classes so that the P7's latencies and hazards can be better described. For the most part, this means differentiating indexed from non-index pre-increment loads and stores. Also, differentiate single from double-precision sqrt. No functionality change intended (except for a more-specific latency for single-precision sqrt on the A2). llvm-svn: 195980
2013-12-01 04:41:13 +08:00
InstrItinData<IIC_LdStSTDUX , [InstrStage<3, [G5_SLU]>]>,
Don't share functional units among the PPC itineraries Instead of sharing functional unit names between the various PPC itineraries, give each core its own unit names prefixed with the core name. This follows the convention used by other backends (such as ARM), and removes a non-obvious ordering dependency between the various PPCSchedule*.td files. No functionality change intended. llvm-svn: 195908
2013-11-28 14:05:59 +08:00
InstrItinData<IIC_LdStSTDCX , [InstrStage<11, [G5_SLU]>]>,
InstrItinData<IIC_LdStSTVEBX , [InstrStage<5, [G5_SLU]>]>,
InstrItinData<IIC_LdStSTWCX , [InstrStage<11, [G5_SLU]>]>,
InstrItinData<IIC_LdStSync , [InstrStage<35, [G5_SLU]>]>,
InstrItinData<IIC_SprISYNC , [InstrStage<40, [G5_SLU]>]>, // needs work
InstrItinData<IIC_SprMFSR , [InstrStage<3, [G5_SLU]>]>,
InstrItinData<IIC_SprMTMSR , [InstrStage<3, [G5_SLU]>]>,
InstrItinData<IIC_SprMTSR , [InstrStage<3, [G5_SLU]>]>,
InstrItinData<IIC_SprTLBSYNC , [InstrStage<3, [G5_SLU]>]>,
InstrItinData<IIC_SprMFCR , [InstrStage<2, [G5_IU2]>]>,
Split some PPC itinerary classes In preparation for adding scheduling definitions for the POWER7, split some PPC itinerary classes so that the P7's latencies and hazards can be better described. For the most part, this means differentiating indexed from non-index pre-increment loads and stores. Also, differentiate single from double-precision sqrt. No functionality change intended (except for a more-specific latency for single-precision sqrt on the A2). llvm-svn: 195980
2013-12-01 04:41:13 +08:00
InstrItinData<IIC_SprMFCRF , [InstrStage<2, [G5_IU2]>]>,
Don't share functional units among the PPC itineraries Instead of sharing functional unit names between the various PPC itineraries, give each core its own unit names prefixed with the core name. This follows the convention used by other backends (such as ARM), and removes a non-obvious ordering dependency between the various PPCSchedule*.td files. No functionality change intended. llvm-svn: 195908
2013-11-28 14:05:59 +08:00
InstrItinData<IIC_SprMFMSR , [InstrStage<3, [G5_IU2]>]>,
InstrItinData<IIC_SprMFSPR , [InstrStage<3, [G5_IU2]>]>,
InstrItinData<IIC_SprMFTB , [InstrStage<10, [G5_IU2]>]>,
InstrItinData<IIC_SprMTSPR , [InstrStage<8, [G5_IU2]>]>,
InstrItinData<IIC_SprSC , [InstrStage<1, [G5_IU2]>]>,
InstrItinData<IIC_FPGeneral , [InstrStage<6, [G5_FPU1, G5_FPU2]>]>,
InstrItinData<IIC_FPAddSub , [InstrStage<6, [G5_FPU1, G5_FPU2]>]>,
InstrItinData<IIC_FPCompare , [InstrStage<8, [G5_FPU1, G5_FPU2]>]>,
InstrItinData<IIC_FPDivD , [InstrStage<33, [G5_FPU1, G5_FPU2]>]>,
InstrItinData<IIC_FPDivS , [InstrStage<33, [G5_FPU1, G5_FPU2]>]>,
InstrItinData<IIC_FPFused , [InstrStage<6, [G5_FPU1, G5_FPU2]>]>,
InstrItinData<IIC_FPRes , [InstrStage<6, [G5_FPU1, G5_FPU2]>]>,
Split some PPC itinerary classes In preparation for adding scheduling definitions for the POWER7, split some PPC itinerary classes so that the P7's latencies and hazards can be better described. For the most part, this means differentiating indexed from non-index pre-increment loads and stores. Also, differentiate single from double-precision sqrt. No functionality change intended (except for a more-specific latency for single-precision sqrt on the A2). llvm-svn: 195980
2013-12-01 04:41:13 +08:00
InstrItinData<IIC_FPSqrtD , [InstrStage<40, [G5_FPU1, G5_FPU2]>]>,
InstrItinData<IIC_FPSqrtS , [InstrStage<40, [G5_FPU1, G5_FPU2]>]>,
Don't share functional units among the PPC itineraries Instead of sharing functional unit names between the various PPC itineraries, give each core its own unit names prefixed with the core name. This follows the convention used by other backends (such as ARM), and removes a non-obvious ordering dependency between the various PPCSchedule*.td files. No functionality change intended. llvm-svn: 195908
2013-11-28 14:05:59 +08:00
InstrItinData<IIC_VecGeneral , [InstrStage<2, [G5_VIU1]>]>,
InstrItinData<IIC_VecFP , [InstrStage<8, [G5_VFPU]>]>,
InstrItinData<IIC_VecFPCompare, [InstrStage<2, [G5_VFPU]>]>,
InstrItinData<IIC_VecComplex , [InstrStage<5, [G5_VIU2]>]>,
InstrItinData<IIC_VecPerm , [InstrStage<3, [G5_VPU]>]>,
InstrItinData<IIC_VecFPRound , [InstrStage<8, [G5_VFPU]>]>,
InstrItinData<IIC_VecVSL , [InstrStage<2, [G5_VIU1]>]>,
InstrItinData<IIC_VecVSR , [InstrStage<3, [G5_VPU]>]>
Checking in first round of scheduling tablegen files. Not tied in as yet. llvm-svn: 23786
2005-10-19 00:23:40 +08:00
]>;
Add a SchedMachineModel for the PPC G5 llvm-svn: 178850
2013-04-05 13:49:18 +08:00
// ===---------------------------------------------------------------------===//
Don't share functional units among the PPC itineraries Instead of sharing functional unit names between the various PPC itineraries, give each core its own unit names prefixed with the core name. This follows the convention used by other backends (such as ARM), and removes a non-obvious ordering dependency between the various PPCSchedule*.td files. No functionality change intended. llvm-svn: 195908
2013-11-28 14:05:59 +08:00
// G5 machine model for scheduling and other instruction cost heuristics.
Add a SchedMachineModel for the PPC G5 llvm-svn: 178850
2013-04-05 13:49:18 +08:00
def G5Model : SchedMachineModel {
let IssueWidth = 4; // 4 (non-branch) instructions are dispatched per cycle.
let LoadLatency = 3; // Optimistic load latency assuming bypass.
// This is overriden by OperandCycles if the
// Itineraries are queried instead.
let MispredictPenalty = 16;
TableGen: Check scheduling models for completeness TableGen checks at compiletime that for scheduling models with "CompleteModel = 1" one of the following holds: - Is marked with the hasNoSchedulingInfo flag - The instruction is a subclass of Sched - There are InstRW definitions in the scheduling model Typical steps necessary to complete a model: - Ensure all pseudo instructions that are expanded before machine scheduling (usually everything handled with EmitYYY() functions in XXXTargetLowering). - If a CPU does not support some instructions mark the corresponding resource unsupported: "WriteRes<WriteXXX, []> { let Unsupported = 1; }". - Add missing scheduling information. Differential Revision: http://reviews.llvm.org/D17747 llvm-svn: 262384
2016-03-02 04:03:21 +08:00
let CompleteModel = 0;
Add a SchedMachineModel for the PPC G5 llvm-svn: 178850
2013-04-05 13:49:18 +08:00
let Itineraries = G5Itineraries;
}