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llvm-project/llvm/test/CodeGen/RISCV/zext-with-load-is-free.ll

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[RISCV] Add test case showing suboptimal codegen when loading unsigned char/short Implementing isZextFree will allow lbu or lhu to be selected rather than lb+mask and lh+mask. llvm-svn: 330942
2018-04-26 22:00:35 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32I
; TODO: lbu and lhu should be selected to avoid the unnecessary masking.
@bytes = global [5 x i8] zeroinitializer, align 1
[RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV r360897 was incomplete, must have applied an old/wip patch. This is in preparation for emitting CFI directives. llvm-svn: 361493
2019-05-23 20:43:13 +08:00
define i32 @test_zext_i8() nounwind {
[RISCV] Add test case showing suboptimal codegen when loading unsigned char/short Implementing isZextFree will allow lbu or lhu to be selected rather than lb+mask and lh+mask. llvm-svn: 330942
2018-04-26 22:00:35 +08:00
; RV32I-LABEL: test_zext_i8:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: lui a0, %hi(bytes)
[RISCV] Separate base from offset in lowerGlobalAddress Summary: When lowering global address, lower the base as a TargetGlobal first then create an SDNode for the offset separately and chain it to the address calculation This optimization will create a DAG where the base address of a global access will be reused between different access. The offset can later be folded into the immediate part of the memory access instruction. With this optimization we generate: lui a0, %hi(s) addi a0, a0, %lo(s) ; shared base address. addi a1, zero, 20 ; 2 instructions per access. sw a1, 44(a0) addi a1, zero, 10 sw a1, 8(a0) addi a1, zero, 30 sw a1, 80(a0) Instead of: lui a0, %hi(s+44) ; 3 instructions per access. addi a1, zero, 20 sw a1, %lo(s+44)(a0) lui a0, %hi(s+8) addi a1, zero, 10 sw a1, %lo(s+8)(a0) lui a0, %hi(s+80) addi a1, zero, 30 sw a1, %lo(s+80)(a0) Which will save one instruction per access. Reviewers: asb, apazos Reviewed By: asb Subscribers: rbar, johnrusso, simoncook, jordy.potman.lists, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, mgrang, apazos, asb, llvm-commits Differential Revision: https://reviews.llvm.org/D46989 llvm-svn: 332641
2018-05-18 02:14:53 +08:00
; RV32I-NEXT: lbu a1, %lo(bytes)(a0)
; RV32I-NEXT: addi a0, a0, %lo(bytes)
; RV32I-NEXT: lbu a0, 1(a0)
[RISCV] Implement Hooks to avoid chaining SELECT Summary: This implements two hooks that attempt to avoid control flow for RISC-V. RISC-V will lower SELECTs into control flow, which is not a great idea. The hook `hasMultipleConditionRegisters()` turns off the following DAGCombiner folds: select(C0|C1, x, y) <=> select(C0, x, select(C1, x, y)) select(C0&C1, x, y) <=> select(C0, select(C1, x, y), y) The second hook `setJumpIsExpensive` controls a flag that has a similar purpose and is used in CodeGenPrepare and the SelectionDAGBuilder. Both of these have the effect of ensuring more logic is done before fewer jumps. Note: with the `B` extension, we may be able to lower select into a conditional move instruction, so at some point these hooks will need to be guarded based on enabled extensions. Reviewed By: luismarques Differential Revision: https://reviews.llvm.org/D79268
2020-07-01 18:55:07 +08:00
; RV32I-NEXT: xori a1, a1, 136
; RV32I-NEXT: xori a0, a0, 7
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: bnez a0, .LBB0_2
; RV32I-NEXT: # %bb.1: # %if.end
[RISCV] Add test case showing suboptimal codegen when loading unsigned char/short Implementing isZextFree will allow lbu or lhu to be selected rather than lb+mask and lh+mask. llvm-svn: 330942
2018-04-26 22:00:35 +08:00
; RV32I-NEXT: mv a0, zero
; RV32I-NEXT: ret
[RISCV] Implement Hooks to avoid chaining SELECT Summary: This implements two hooks that attempt to avoid control flow for RISC-V. RISC-V will lower SELECTs into control flow, which is not a great idea. The hook `hasMultipleConditionRegisters()` turns off the following DAGCombiner folds: select(C0|C1, x, y) <=> select(C0, x, select(C1, x, y)) select(C0&C1, x, y) <=> select(C0, select(C1, x, y), y) The second hook `setJumpIsExpensive` controls a flag that has a similar purpose and is used in CodeGenPrepare and the SelectionDAGBuilder. Both of these have the effect of ensuring more logic is done before fewer jumps. Note: with the `B` extension, we may be able to lower select into a conditional move instruction, so at some point these hooks will need to be guarded based on enabled extensions. Reviewed By: luismarques Differential Revision: https://reviews.llvm.org/D79268
2020-07-01 18:55:07 +08:00
; RV32I-NEXT: .LBB0_2: # %if.then
[RISCV] Add test case showing suboptimal codegen when loading unsigned char/short Implementing isZextFree will allow lbu or lhu to be selected rather than lb+mask and lh+mask. llvm-svn: 330942
2018-04-26 22:00:35 +08:00
; RV32I-NEXT: addi a0, zero, 1
; RV32I-NEXT: ret
entry:
%0 = load i8, i8* getelementptr inbounds ([5 x i8], [5 x i8]* @bytes, i32 0, i32 0), align 1
%cmp = icmp eq i8 %0, -120
%1 = load i8, i8* getelementptr inbounds ([5 x i8], [5 x i8]* @bytes, i32 0, i32 1), align 1
%cmp3 = icmp eq i8 %1, 7
%or.cond = and i1 %cmp, %cmp3
br i1 %or.cond, label %if.end, label %if.then
if.then:
ret i32 1
if.end:
ret i32 0
}
@shorts = global [5 x i16] zeroinitializer, align 2
[RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV r360897 was incomplete, must have applied an old/wip patch. This is in preparation for emitting CFI directives. llvm-svn: 361493
2019-05-23 20:43:13 +08:00
define i32 @test_zext_i16() nounwind {
[RISCV] Add test case showing suboptimal codegen when loading unsigned char/short Implementing isZextFree will allow lbu or lhu to be selected rather than lb+mask and lh+mask. llvm-svn: 330942
2018-04-26 22:00:35 +08:00
; RV32I-LABEL: test_zext_i16:
; RV32I: # %bb.0: # %entry
[RISCV] Separate base from offset in lowerGlobalAddress Summary: When lowering global address, lower the base as a TargetGlobal first then create an SDNode for the offset separately and chain it to the address calculation This optimization will create a DAG where the base address of a global access will be reused between different access. The offset can later be folded into the immediate part of the memory access instruction. With this optimization we generate: lui a0, %hi(s) addi a0, a0, %lo(s) ; shared base address. addi a1, zero, 20 ; 2 instructions per access. sw a1, 44(a0) addi a1, zero, 10 sw a1, 8(a0) addi a1, zero, 30 sw a1, 80(a0) Instead of: lui a0, %hi(s+44) ; 3 instructions per access. addi a1, zero, 20 sw a1, %lo(s+44)(a0) lui a0, %hi(s+8) addi a1, zero, 10 sw a1, %lo(s+8)(a0) lui a0, %hi(s+80) addi a1, zero, 30 sw a1, %lo(s+80)(a0) Which will save one instruction per access. Reviewers: asb, apazos Reviewed By: asb Subscribers: rbar, johnrusso, simoncook, jordy.potman.lists, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, mgrang, apazos, asb, llvm-commits Differential Revision: https://reviews.llvm.org/D46989 llvm-svn: 332641
2018-05-18 02:14:53 +08:00
; RV32I-NEXT: lui a0, %hi(shorts)
[RISCV] Switch to the Machine Scheduler Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
2019-09-17 19:15:35 +08:00
; RV32I-NEXT: lhu a1, %lo(shorts)(a0)
[RISCV] Separate base from offset in lowerGlobalAddress Summary: When lowering global address, lower the base as a TargetGlobal first then create an SDNode for the offset separately and chain it to the address calculation This optimization will create a DAG where the base address of a global access will be reused between different access. The offset can later be folded into the immediate part of the memory access instruction. With this optimization we generate: lui a0, %hi(s) addi a0, a0, %lo(s) ; shared base address. addi a1, zero, 20 ; 2 instructions per access. sw a1, 44(a0) addi a1, zero, 10 sw a1, 8(a0) addi a1, zero, 30 sw a1, 80(a0) Instead of: lui a0, %hi(s+44) ; 3 instructions per access. addi a1, zero, 20 sw a1, %lo(s+44)(a0) lui a0, %hi(s+8) addi a1, zero, 10 sw a1, %lo(s+8)(a0) lui a0, %hi(s+80) addi a1, zero, 30 sw a1, %lo(s+80)(a0) Which will save one instruction per access. Reviewers: asb, apazos Reviewed By: asb Subscribers: rbar, johnrusso, simoncook, jordy.potman.lists, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, mgrang, apazos, asb, llvm-commits Differential Revision: https://reviews.llvm.org/D46989 llvm-svn: 332641
2018-05-18 02:14:53 +08:00
; RV32I-NEXT: addi a0, a0, %lo(shorts)
; RV32I-NEXT: lhu a0, 2(a0)
[RISCV] Implement Hooks to avoid chaining SELECT Summary: This implements two hooks that attempt to avoid control flow for RISC-V. RISC-V will lower SELECTs into control flow, which is not a great idea. The hook `hasMultipleConditionRegisters()` turns off the following DAGCombiner folds: select(C0|C1, x, y) <=> select(C0, x, select(C1, x, y)) select(C0&C1, x, y) <=> select(C0, select(C1, x, y), y) The second hook `setJumpIsExpensive` controls a flag that has a similar purpose and is used in CodeGenPrepare and the SelectionDAGBuilder. Both of these have the effect of ensuring more logic is done before fewer jumps. Note: with the `B` extension, we may be able to lower select into a conditional move instruction, so at some point these hooks will need to be guarded based on enabled extensions. Reviewed By: luismarques Differential Revision: https://reviews.llvm.org/D79268
2020-07-01 18:55:07 +08:00
; RV32I-NEXT: lui a2, 16
; RV32I-NEXT: addi a2, a2, -120
; RV32I-NEXT: xor a1, a1, a2
; RV32I-NEXT: xori a0, a0, 7
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: bnez a0, .LBB1_2
; RV32I-NEXT: # %bb.1: # %if.end
[RISCV] Add test case showing suboptimal codegen when loading unsigned char/short Implementing isZextFree will allow lbu or lhu to be selected rather than lb+mask and lh+mask. llvm-svn: 330942
2018-04-26 22:00:35 +08:00
; RV32I-NEXT: mv a0, zero
; RV32I-NEXT: ret
[RISCV] Implement Hooks to avoid chaining SELECT Summary: This implements two hooks that attempt to avoid control flow for RISC-V. RISC-V will lower SELECTs into control flow, which is not a great idea. The hook `hasMultipleConditionRegisters()` turns off the following DAGCombiner folds: select(C0|C1, x, y) <=> select(C0, x, select(C1, x, y)) select(C0&C1, x, y) <=> select(C0, select(C1, x, y), y) The second hook `setJumpIsExpensive` controls a flag that has a similar purpose and is used in CodeGenPrepare and the SelectionDAGBuilder. Both of these have the effect of ensuring more logic is done before fewer jumps. Note: with the `B` extension, we may be able to lower select into a conditional move instruction, so at some point these hooks will need to be guarded based on enabled extensions. Reviewed By: luismarques Differential Revision: https://reviews.llvm.org/D79268
2020-07-01 18:55:07 +08:00
; RV32I-NEXT: .LBB1_2: # %if.then
[RISCV] Add test case showing suboptimal codegen when loading unsigned char/short Implementing isZextFree will allow lbu or lhu to be selected rather than lb+mask and lh+mask. llvm-svn: 330942
2018-04-26 22:00:35 +08:00
; RV32I-NEXT: addi a0, zero, 1
; RV32I-NEXT: ret
entry:
%0 = load i16, i16* getelementptr inbounds ([5 x i16], [5 x i16]* @shorts, i32 0, i32 0), align 2
%cmp = icmp eq i16 %0, -120
%1 = load i16, i16* getelementptr inbounds ([5 x i16], [5 x i16]* @shorts, i32 0, i32 1), align 2
%cmp3 = icmp eq i16 %1, 7
%or.cond = and i1 %cmp, %cmp3
br i1 %or.cond, label %if.end, label %if.then
if.then:
ret i32 1
if.end:
ret i32 0
}