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llvm-project/llvm/test/CodeGen/RISCV/shifts.ll

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[RISCV] Support and tests for a variety of additional LLVM IR constructs Previous patches primarily ensured that codegen was possible for the standard RISC-V instructions. However, there are a number of IR inputs that wouldn't be appropriately lowered. This patch both adds test cases and supports lowering for a number of these cases: * Improved sext/zext/trunc support * Support for setcc variants that don't map directly to RISC-V instructions * Lowering mul, and hence support for external symbols * addc, adde, subc, sube * mulhs, srem, mulhu, urem, udiv, sdiv * {srl,sra,shl}_parts * brind * br_jt * bswap, ctlz, cttz, ctpop * rotl, rotr * BlockAddress operands Differential Revision: https://reviews.llvm.org/D29938 llvm-svn: 318737
2017-11-21 16:11:03 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32I
[RISCV] Custom lower SHL_PARTS, SRA_PARTS, SRL_PARTS When not optimizing for minimum size (-Oz) we custom lower wide shifts (SHL_PARTS, SRA_PARTS, SRL_PARTS) instead of expanding to a libcall. Differential Revision: https://reviews.llvm.org/D59477 llvm-svn: 358498
2019-04-16 22:38:32 +08:00
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64I
[RISCV] Support and tests for a variety of additional LLVM IR constructs Previous patches primarily ensured that codegen was possible for the standard RISC-V instructions. However, there are a number of IR inputs that wouldn't be appropriately lowered. This patch both adds test cases and supports lowering for a number of these cases: * Improved sext/zext/trunc support * Support for setcc variants that don't map directly to RISC-V instructions * Lowering mul, and hence support for external symbols * addc, adde, subc, sube * mulhs, srem, mulhu, urem, udiv, sdiv * {srl,sra,shl}_parts * brind * br_jt * bswap, ctlz, cttz, ctpop * rotl, rotr * BlockAddress operands Differential Revision: https://reviews.llvm.org/D29938 llvm-svn: 318737
2017-11-21 16:11:03 +08:00
; Basic shift support is tested as part of ALU.ll. This file ensures that
; shifts which may not be supported natively are lowered properly.
define i64 @lshr64(i64 %a, i64 %b) nounwind {
; RV32I-LABEL: lshr64:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; RV32I: # %bb.0:
[RISCV] Custom lower SHL_PARTS, SRA_PARTS, SRL_PARTS When not optimizing for minimum size (-Oz) we custom lower wide shifts (SHL_PARTS, SRA_PARTS, SRL_PARTS) instead of expanding to a libcall. Differential Revision: https://reviews.llvm.org/D59477 llvm-svn: 358498
2019-04-16 22:38:32 +08:00
; RV32I-NEXT: addi a3, a2, -32
; RV32I-NEXT: bltz a3, .LBB0_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: srl a0, a1, a3
; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: ret
; RV32I-NEXT: .LBB0_2:
[RISCV] Switch to the Machine Scheduler Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
2019-09-17 19:15:35 +08:00
; RV32I-NEXT: srl a0, a0, a2
[RISCV] Custom lower SHL_PARTS, SRA_PARTS, SRL_PARTS When not optimizing for minimum size (-Oz) we custom lower wide shifts (SHL_PARTS, SRA_PARTS, SRL_PARTS) instead of expanding to a libcall. Differential Revision: https://reviews.llvm.org/D59477 llvm-svn: 358498
2019-04-16 22:38:32 +08:00
; RV32I-NEXT: addi a3, zero, 31
; RV32I-NEXT: sub a3, a3, a2
; RV32I-NEXT: slli a4, a1, 1
; RV32I-NEXT: sll a3, a4, a3
; RV32I-NEXT: or a0, a0, a3
Reland [MachineCopyPropagation] Extend MCP to do trivial copy backward propagation. Fix assertion error ``` bool llvm::MachineOperand::isRenamable() const: Assertion `Register::isPhysicalRegister(getReg()) && "isRenamable should only be checked on physical registers"' failed. ``` by checking if the register is 0 before invoking `isRenamable`.
2019-12-05 14:01:00 +08:00
; RV32I-NEXT: srl a1, a1, a2
[RISCV] Custom lower SHL_PARTS, SRA_PARTS, SRL_PARTS When not optimizing for minimum size (-Oz) we custom lower wide shifts (SHL_PARTS, SRA_PARTS, SRL_PARTS) instead of expanding to a libcall. Differential Revision: https://reviews.llvm.org/D59477 llvm-svn: 358498
2019-04-16 22:38:32 +08:00
; RV32I-NEXT: ret
;
; RV64I-LABEL: lshr64:
; RV64I: # %bb.0:
; RV64I-NEXT: srl a0, a0, a1
; RV64I-NEXT: ret
%1 = lshr i64 %a, %b
ret i64 %1
}
define i64 @lshr64_minsize(i64 %a, i64 %b) minsize nounwind {
; RV32I-LABEL: lshr64_minsize:
; RV32I: # %bb.0:
[RISCV] Implement prolog and epilog insertion As frame pointer elimination isn't implemented until a later patch and we make extensive use of update_llc_test_checks.py, this changes touches a lot of the RISC-V tests. Differential Revision: https://reviews.llvm.org/D39849 llvm-svn: 320357
2017-12-11 20:34:11 +08:00
; RV32I-NEXT: addi sp, sp, -16
[RISCV] Support lowering FrameIndex Introduces the AddrFI "addressing mode", which is necessary simply because it's not possible to write a pattern that directly matches a frameindex. Ensure callee-saved registers are accessed relative to the stackpointer. This is necessary as callee-saved register spills are performed before the frame pointer is set. Move HexagonDAGToDAGISel::isOrEquivalentToAdd to SelectionDAGISel, so we can make use of it in the RISC-V backend. Differential Revision: https://reviews.llvm.org/D39848 llvm-svn: 320353
2017-12-11 19:53:54 +08:00
; RV32I-NEXT: sw ra, 12(sp)
[RISCV] Expand function call to "call" pseudoinstruction To do this: 1. Change GlobalAddress SDNode to TargetGlobalAddress to avoid legalizer split the symbol. 2. Change ExternalSymbol SDNode to TargetExternalSymbol to avoid legalizer split the symbol. 3. Let PseudoCALL match direct call with target operand TargetGlobalAddress and TargetExternalSymbol. Differential Revision: https://reviews.llvm.org/D44885 llvm-svn: 330827
2018-04-25 22:19:12 +08:00
; RV32I-NEXT: call __lshrdi3
[RISCV] Support lowering FrameIndex Introduces the AddrFI "addressing mode", which is necessary simply because it's not possible to write a pattern that directly matches a frameindex. Ensure callee-saved registers are accessed relative to the stackpointer. This is necessary as callee-saved register spills are performed before the frame pointer is set. Move HexagonDAGToDAGISel::isOrEquivalentToAdd to SelectionDAGISel, so we can make use of it in the RISC-V backend. Differential Revision: https://reviews.llvm.org/D39848 llvm-svn: 320353
2017-12-11 19:53:54 +08:00
; RV32I-NEXT: lw ra, 12(sp)
[RISCV] Implement prolog and epilog insertion As frame pointer elimination isn't implemented until a later patch and we make extensive use of update_llc_test_checks.py, this changes touches a lot of the RISC-V tests. Differential Revision: https://reviews.llvm.org/D39849 llvm-svn: 320357
2017-12-11 20:34:11 +08:00
; RV32I-NEXT: addi sp, sp, 16
[RISCV] Enable emission of alias instructions by default This patch switches the default for -riscv-no-aliases to false and updates all affected MC and CodeGen tests. As recommended in D41071, MC tests use the canonical instructions and the CodeGen tests use the aliases. Additionally, for the f and d instructions with rounding mode, the tests for the aliased versions are moved and tightened such that they can actually detect if alias emission is enabled. (see D40902 for context) Differential Revision: https://reviews.llvm.org/D41225 Patch by Mario Werner. llvm-svn: 320797
2017-12-15 17:47:01 +08:00
; RV32I-NEXT: ret
[RISCV] Custom lower SHL_PARTS, SRA_PARTS, SRL_PARTS When not optimizing for minimum size (-Oz) we custom lower wide shifts (SHL_PARTS, SRA_PARTS, SRL_PARTS) instead of expanding to a libcall. Differential Revision: https://reviews.llvm.org/D59477 llvm-svn: 358498
2019-04-16 22:38:32 +08:00
;
; RV64I-LABEL: lshr64_minsize:
; RV64I: # %bb.0:
; RV64I-NEXT: srl a0, a0, a1
; RV64I-NEXT: ret
[RISCV] Support and tests for a variety of additional LLVM IR constructs Previous patches primarily ensured that codegen was possible for the standard RISC-V instructions. However, there are a number of IR inputs that wouldn't be appropriately lowered. This patch both adds test cases and supports lowering for a number of these cases: * Improved sext/zext/trunc support * Support for setcc variants that don't map directly to RISC-V instructions * Lowering mul, and hence support for external symbols * addc, adde, subc, sube * mulhs, srem, mulhu, urem, udiv, sdiv * {srl,sra,shl}_parts * brind * br_jt * bswap, ctlz, cttz, ctpop * rotl, rotr * BlockAddress operands Differential Revision: https://reviews.llvm.org/D29938 llvm-svn: 318737
2017-11-21 16:11:03 +08:00
%1 = lshr i64 %a, %b
ret i64 %1
}
define i64 @ashr64(i64 %a, i64 %b) nounwind {
; RV32I-LABEL: ashr64:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; RV32I: # %bb.0:
[RISCV] Custom lower SHL_PARTS, SRA_PARTS, SRL_PARTS When not optimizing for minimum size (-Oz) we custom lower wide shifts (SHL_PARTS, SRA_PARTS, SRL_PARTS) instead of expanding to a libcall. Differential Revision: https://reviews.llvm.org/D59477 llvm-svn: 358498
2019-04-16 22:38:32 +08:00
; RV32I-NEXT: addi a3, a2, -32
; RV32I-NEXT: bltz a3, .LBB2_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: sra a0, a1, a3
; RV32I-NEXT: srai a1, a1, 31
; RV32I-NEXT: ret
; RV32I-NEXT: .LBB2_2:
[RISCV] Switch to the Machine Scheduler Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
2019-09-17 19:15:35 +08:00
; RV32I-NEXT: srl a0, a0, a2
[RISCV] Custom lower SHL_PARTS, SRA_PARTS, SRL_PARTS When not optimizing for minimum size (-Oz) we custom lower wide shifts (SHL_PARTS, SRA_PARTS, SRL_PARTS) instead of expanding to a libcall. Differential Revision: https://reviews.llvm.org/D59477 llvm-svn: 358498
2019-04-16 22:38:32 +08:00
; RV32I-NEXT: addi a3, zero, 31
; RV32I-NEXT: sub a3, a3, a2
; RV32I-NEXT: slli a4, a1, 1
; RV32I-NEXT: sll a3, a4, a3
; RV32I-NEXT: or a0, a0, a3
; RV32I-NEXT: sra a1, a1, a2
; RV32I-NEXT: ret
;
; RV64I-LABEL: ashr64:
; RV64I: # %bb.0:
; RV64I-NEXT: sra a0, a0, a1
; RV64I-NEXT: ret
%1 = ashr i64 %a, %b
ret i64 %1
}
define i64 @ashr64_minsize(i64 %a, i64 %b) minsize nounwind {
; RV32I-LABEL: ashr64_minsize:
; RV32I: # %bb.0:
[RISCV] Implement prolog and epilog insertion As frame pointer elimination isn't implemented until a later patch and we make extensive use of update_llc_test_checks.py, this changes touches a lot of the RISC-V tests. Differential Revision: https://reviews.llvm.org/D39849 llvm-svn: 320357
2017-12-11 20:34:11 +08:00
; RV32I-NEXT: addi sp, sp, -16
[RISCV] Support lowering FrameIndex Introduces the AddrFI "addressing mode", which is necessary simply because it's not possible to write a pattern that directly matches a frameindex. Ensure callee-saved registers are accessed relative to the stackpointer. This is necessary as callee-saved register spills are performed before the frame pointer is set. Move HexagonDAGToDAGISel::isOrEquivalentToAdd to SelectionDAGISel, so we can make use of it in the RISC-V backend. Differential Revision: https://reviews.llvm.org/D39848 llvm-svn: 320353
2017-12-11 19:53:54 +08:00
; RV32I-NEXT: sw ra, 12(sp)
[RISCV] Expand function call to "call" pseudoinstruction To do this: 1. Change GlobalAddress SDNode to TargetGlobalAddress to avoid legalizer split the symbol. 2. Change ExternalSymbol SDNode to TargetExternalSymbol to avoid legalizer split the symbol. 3. Let PseudoCALL match direct call with target operand TargetGlobalAddress and TargetExternalSymbol. Differential Revision: https://reviews.llvm.org/D44885 llvm-svn: 330827
2018-04-25 22:19:12 +08:00
; RV32I-NEXT: call __ashrdi3
[RISCV] Support lowering FrameIndex Introduces the AddrFI "addressing mode", which is necessary simply because it's not possible to write a pattern that directly matches a frameindex. Ensure callee-saved registers are accessed relative to the stackpointer. This is necessary as callee-saved register spills are performed before the frame pointer is set. Move HexagonDAGToDAGISel::isOrEquivalentToAdd to SelectionDAGISel, so we can make use of it in the RISC-V backend. Differential Revision: https://reviews.llvm.org/D39848 llvm-svn: 320353
2017-12-11 19:53:54 +08:00
; RV32I-NEXT: lw ra, 12(sp)
[RISCV] Implement prolog and epilog insertion As frame pointer elimination isn't implemented until a later patch and we make extensive use of update_llc_test_checks.py, this changes touches a lot of the RISC-V tests. Differential Revision: https://reviews.llvm.org/D39849 llvm-svn: 320357
2017-12-11 20:34:11 +08:00
; RV32I-NEXT: addi sp, sp, 16
[RISCV] Enable emission of alias instructions by default This patch switches the default for -riscv-no-aliases to false and updates all affected MC and CodeGen tests. As recommended in D41071, MC tests use the canonical instructions and the CodeGen tests use the aliases. Additionally, for the f and d instructions with rounding mode, the tests for the aliased versions are moved and tightened such that they can actually detect if alias emission is enabled. (see D40902 for context) Differential Revision: https://reviews.llvm.org/D41225 Patch by Mario Werner. llvm-svn: 320797
2017-12-15 17:47:01 +08:00
; RV32I-NEXT: ret
[RISCV] Custom lower SHL_PARTS, SRA_PARTS, SRL_PARTS When not optimizing for minimum size (-Oz) we custom lower wide shifts (SHL_PARTS, SRA_PARTS, SRL_PARTS) instead of expanding to a libcall. Differential Revision: https://reviews.llvm.org/D59477 llvm-svn: 358498
2019-04-16 22:38:32 +08:00
;
; RV64I-LABEL: ashr64_minsize:
; RV64I: # %bb.0:
; RV64I-NEXT: sra a0, a0, a1
; RV64I-NEXT: ret
[RISCV] Support and tests for a variety of additional LLVM IR constructs Previous patches primarily ensured that codegen was possible for the standard RISC-V instructions. However, there are a number of IR inputs that wouldn't be appropriately lowered. This patch both adds test cases and supports lowering for a number of these cases: * Improved sext/zext/trunc support * Support for setcc variants that don't map directly to RISC-V instructions * Lowering mul, and hence support for external symbols * addc, adde, subc, sube * mulhs, srem, mulhu, urem, udiv, sdiv * {srl,sra,shl}_parts * brind * br_jt * bswap, ctlz, cttz, ctpop * rotl, rotr * BlockAddress operands Differential Revision: https://reviews.llvm.org/D29938 llvm-svn: 318737
2017-11-21 16:11:03 +08:00
%1 = ashr i64 %a, %b
ret i64 %1
}
define i64 @shl64(i64 %a, i64 %b) nounwind {
; RV32I-LABEL: shl64:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; RV32I: # %bb.0:
[RISCV] Custom lower SHL_PARTS, SRA_PARTS, SRL_PARTS When not optimizing for minimum size (-Oz) we custom lower wide shifts (SHL_PARTS, SRA_PARTS, SRL_PARTS) instead of expanding to a libcall. Differential Revision: https://reviews.llvm.org/D59477 llvm-svn: 358498
2019-04-16 22:38:32 +08:00
; RV32I-NEXT: addi a3, a2, -32
; RV32I-NEXT: bltz a3, .LBB4_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: sll a1, a0, a3
; RV32I-NEXT: mv a0, zero
; RV32I-NEXT: ret
; RV32I-NEXT: .LBB4_2:
[RISCV] Switch to the Machine Scheduler Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
2019-09-17 19:15:35 +08:00
; RV32I-NEXT: sll a1, a1, a2
[RISCV] Custom lower SHL_PARTS, SRA_PARTS, SRL_PARTS When not optimizing for minimum size (-Oz) we custom lower wide shifts (SHL_PARTS, SRA_PARTS, SRL_PARTS) instead of expanding to a libcall. Differential Revision: https://reviews.llvm.org/D59477 llvm-svn: 358498
2019-04-16 22:38:32 +08:00
; RV32I-NEXT: addi a3, zero, 31
; RV32I-NEXT: sub a3, a3, a2
; RV32I-NEXT: srli a4, a0, 1
; RV32I-NEXT: srl a3, a4, a3
; RV32I-NEXT: or a1, a1, a3
Reland [MachineCopyPropagation] Extend MCP to do trivial copy backward propagation. Fix assertion error ``` bool llvm::MachineOperand::isRenamable() const: Assertion `Register::isPhysicalRegister(getReg()) && "isRenamable should only be checked on physical registers"' failed. ``` by checking if the register is 0 before invoking `isRenamable`.
2019-12-05 14:01:00 +08:00
; RV32I-NEXT: sll a0, a0, a2
[RISCV] Custom lower SHL_PARTS, SRA_PARTS, SRL_PARTS When not optimizing for minimum size (-Oz) we custom lower wide shifts (SHL_PARTS, SRA_PARTS, SRL_PARTS) instead of expanding to a libcall. Differential Revision: https://reviews.llvm.org/D59477 llvm-svn: 358498
2019-04-16 22:38:32 +08:00
; RV32I-NEXT: ret
;
; RV64I-LABEL: shl64:
; RV64I: # %bb.0:
; RV64I-NEXT: sll a0, a0, a1
; RV64I-NEXT: ret
%1 = shl i64 %a, %b
ret i64 %1
}
define i64 @shl64_minsize(i64 %a, i64 %b) minsize nounwind {
; RV32I-LABEL: shl64_minsize:
; RV32I: # %bb.0:
[RISCV] Implement prolog and epilog insertion As frame pointer elimination isn't implemented until a later patch and we make extensive use of update_llc_test_checks.py, this changes touches a lot of the RISC-V tests. Differential Revision: https://reviews.llvm.org/D39849 llvm-svn: 320357
2017-12-11 20:34:11 +08:00
; RV32I-NEXT: addi sp, sp, -16
[RISCV] Support lowering FrameIndex Introduces the AddrFI "addressing mode", which is necessary simply because it's not possible to write a pattern that directly matches a frameindex. Ensure callee-saved registers are accessed relative to the stackpointer. This is necessary as callee-saved register spills are performed before the frame pointer is set. Move HexagonDAGToDAGISel::isOrEquivalentToAdd to SelectionDAGISel, so we can make use of it in the RISC-V backend. Differential Revision: https://reviews.llvm.org/D39848 llvm-svn: 320353
2017-12-11 19:53:54 +08:00
; RV32I-NEXT: sw ra, 12(sp)
[RISCV] Expand function call to "call" pseudoinstruction To do this: 1. Change GlobalAddress SDNode to TargetGlobalAddress to avoid legalizer split the symbol. 2. Change ExternalSymbol SDNode to TargetExternalSymbol to avoid legalizer split the symbol. 3. Let PseudoCALL match direct call with target operand TargetGlobalAddress and TargetExternalSymbol. Differential Revision: https://reviews.llvm.org/D44885 llvm-svn: 330827
2018-04-25 22:19:12 +08:00
; RV32I-NEXT: call __ashldi3
[RISCV] Support lowering FrameIndex Introduces the AddrFI "addressing mode", which is necessary simply because it's not possible to write a pattern that directly matches a frameindex. Ensure callee-saved registers are accessed relative to the stackpointer. This is necessary as callee-saved register spills are performed before the frame pointer is set. Move HexagonDAGToDAGISel::isOrEquivalentToAdd to SelectionDAGISel, so we can make use of it in the RISC-V backend. Differential Revision: https://reviews.llvm.org/D39848 llvm-svn: 320353
2017-12-11 19:53:54 +08:00
; RV32I-NEXT: lw ra, 12(sp)
[RISCV] Implement prolog and epilog insertion As frame pointer elimination isn't implemented until a later patch and we make extensive use of update_llc_test_checks.py, this changes touches a lot of the RISC-V tests. Differential Revision: https://reviews.llvm.org/D39849 llvm-svn: 320357
2017-12-11 20:34:11 +08:00
; RV32I-NEXT: addi sp, sp, 16
[RISCV] Enable emission of alias instructions by default This patch switches the default for -riscv-no-aliases to false and updates all affected MC and CodeGen tests. As recommended in D41071, MC tests use the canonical instructions and the CodeGen tests use the aliases. Additionally, for the f and d instructions with rounding mode, the tests for the aliased versions are moved and tightened such that they can actually detect if alias emission is enabled. (see D40902 for context) Differential Revision: https://reviews.llvm.org/D41225 Patch by Mario Werner. llvm-svn: 320797
2017-12-15 17:47:01 +08:00
; RV32I-NEXT: ret
[RISCV] Custom lower SHL_PARTS, SRA_PARTS, SRL_PARTS When not optimizing for minimum size (-Oz) we custom lower wide shifts (SHL_PARTS, SRA_PARTS, SRL_PARTS) instead of expanding to a libcall. Differential Revision: https://reviews.llvm.org/D59477 llvm-svn: 358498
2019-04-16 22:38:32 +08:00
;
; RV64I-LABEL: shl64_minsize:
; RV64I: # %bb.0:
; RV64I-NEXT: sll a0, a0, a1
; RV64I-NEXT: ret
[RISCV] Support and tests for a variety of additional LLVM IR constructs Previous patches primarily ensured that codegen was possible for the standard RISC-V instructions. However, there are a number of IR inputs that wouldn't be appropriately lowered. This patch both adds test cases and supports lowering for a number of these cases: * Improved sext/zext/trunc support * Support for setcc variants that don't map directly to RISC-V instructions * Lowering mul, and hence support for external symbols * addc, adde, subc, sube * mulhs, srem, mulhu, urem, udiv, sdiv * {srl,sra,shl}_parts * brind * br_jt * bswap, ctlz, cttz, ctpop * rotl, rotr * BlockAddress operands Differential Revision: https://reviews.llvm.org/D29938 llvm-svn: 318737
2017-11-21 16:11:03 +08:00
%1 = shl i64 %a, %b
ret i64 %1
}
[RISCV] Custom lower SHL_PARTS, SRA_PARTS, SRL_PARTS When not optimizing for minimum size (-Oz) we custom lower wide shifts (SHL_PARTS, SRA_PARTS, SRL_PARTS) instead of expanding to a libcall. Differential Revision: https://reviews.llvm.org/D59477 llvm-svn: 358498
2019-04-16 22:38:32 +08:00
define i128 @lshr128(i128 %a, i128 %b) nounwind {
; RV32I-LABEL: lshr128:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -48
; RV32I-NEXT: sw ra, 44(sp)
; RV32I-NEXT: sw s0, 40(sp)
Revert Patch from Phabricator This reverts r372092 (git commit e38695a0255c9e7b53639f349f8101bae1ce5c04) llvm-svn: 372104
2019-09-17 18:52:09 +08:00
; RV32I-NEXT: lw a2, 0(a2)
[RISCV] Switch to the Machine Scheduler Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
2019-09-17 19:15:35 +08:00
; RV32I-NEXT: lw a3, 0(a1)
; RV32I-NEXT: lw a4, 4(a1)
; RV32I-NEXT: lw a5, 8(a1)
; RV32I-NEXT: lw a1, 12(a1)
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: sw a1, 20(sp)
; RV32I-NEXT: sw a5, 16(sp)
; RV32I-NEXT: sw a4, 12(sp)
[RISCV] Custom lower SHL_PARTS, SRA_PARTS, SRL_PARTS When not optimizing for minimum size (-Oz) we custom lower wide shifts (SHL_PARTS, SRA_PARTS, SRL_PARTS) instead of expanding to a libcall. Differential Revision: https://reviews.llvm.org/D59477 llvm-svn: 358498
2019-04-16 22:38:32 +08:00
; RV32I-NEXT: addi a0, sp, 24
; RV32I-NEXT: addi a1, sp, 8
[RISCV] Switch to the Machine Scheduler Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
2019-09-17 19:15:35 +08:00
; RV32I-NEXT: sw a3, 8(sp)
[RISCV] Custom lower SHL_PARTS, SRA_PARTS, SRL_PARTS When not optimizing for minimum size (-Oz) we custom lower wide shifts (SHL_PARTS, SRA_PARTS, SRL_PARTS) instead of expanding to a libcall. Differential Revision: https://reviews.llvm.org/D59477 llvm-svn: 358498
2019-04-16 22:38:32 +08:00
; RV32I-NEXT: call __lshrti3
; RV32I-NEXT: lw a0, 36(sp)
[RISCV] Switch to the Machine Scheduler Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
2019-09-17 19:15:35 +08:00
; RV32I-NEXT: lw a1, 32(sp)
; RV32I-NEXT: lw a2, 28(sp)
; RV32I-NEXT: lw a3, 24(sp)
[RISCV] Custom lower SHL_PARTS, SRA_PARTS, SRL_PARTS When not optimizing for minimum size (-Oz) we custom lower wide shifts (SHL_PARTS, SRA_PARTS, SRL_PARTS) instead of expanding to a libcall. Differential Revision: https://reviews.llvm.org/D59477 llvm-svn: 358498
2019-04-16 22:38:32 +08:00
; RV32I-NEXT: sw a0, 12(s0)
[RISCV] Switch to the Machine Scheduler Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
2019-09-17 19:15:35 +08:00
; RV32I-NEXT: sw a1, 8(s0)
; RV32I-NEXT: sw a2, 4(s0)
; RV32I-NEXT: sw a3, 0(s0)
[RISCV] Custom lower SHL_PARTS, SRA_PARTS, SRL_PARTS When not optimizing for minimum size (-Oz) we custom lower wide shifts (SHL_PARTS, SRA_PARTS, SRL_PARTS) instead of expanding to a libcall. Differential Revision: https://reviews.llvm.org/D59477 llvm-svn: 358498
2019-04-16 22:38:32 +08:00
; RV32I-NEXT: lw s0, 40(sp)
; RV32I-NEXT: lw ra, 44(sp)
; RV32I-NEXT: addi sp, sp, 48
; RV32I-NEXT: ret
;
; RV64I-LABEL: lshr128:
; RV64I: # %bb.0:
; RV64I-NEXT: addi a3, a2, -64
; RV64I-NEXT: bltz a3, .LBB6_2
; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: srl a0, a1, a3
; RV64I-NEXT: mv a1, zero
; RV64I-NEXT: ret
; RV64I-NEXT: .LBB6_2:
[RISCV] Switch to the Machine Scheduler Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
2019-09-17 19:15:35 +08:00
; RV64I-NEXT: srl a0, a0, a2
[RISCV] Custom lower SHL_PARTS, SRA_PARTS, SRL_PARTS When not optimizing for minimum size (-Oz) we custom lower wide shifts (SHL_PARTS, SRA_PARTS, SRL_PARTS) instead of expanding to a libcall. Differential Revision: https://reviews.llvm.org/D59477 llvm-svn: 358498
2019-04-16 22:38:32 +08:00
; RV64I-NEXT: addi a3, zero, 63
; RV64I-NEXT: sub a3, a3, a2
; RV64I-NEXT: slli a4, a1, 1
; RV64I-NEXT: sll a3, a4, a3
; RV64I-NEXT: or a0, a0, a3
Reland [MachineCopyPropagation] Extend MCP to do trivial copy backward propagation. Fix assertion error ``` bool llvm::MachineOperand::isRenamable() const: Assertion `Register::isPhysicalRegister(getReg()) && "isRenamable should only be checked on physical registers"' failed. ``` by checking if the register is 0 before invoking `isRenamable`.
2019-12-05 14:01:00 +08:00
; RV64I-NEXT: srl a1, a1, a2
[RISCV] Custom lower SHL_PARTS, SRA_PARTS, SRL_PARTS When not optimizing for minimum size (-Oz) we custom lower wide shifts (SHL_PARTS, SRA_PARTS, SRL_PARTS) instead of expanding to a libcall. Differential Revision: https://reviews.llvm.org/D59477 llvm-svn: 358498
2019-04-16 22:38:32 +08:00
; RV64I-NEXT: ret
%1 = lshr i128 %a, %b
ret i128 %1
}
define i128 @ashr128(i128 %a, i128 %b) nounwind {
; RV32I-LABEL: ashr128:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -48
; RV32I-NEXT: sw ra, 44(sp)
; RV32I-NEXT: sw s0, 40(sp)
Revert Patch from Phabricator This reverts r372092 (git commit e38695a0255c9e7b53639f349f8101bae1ce5c04) llvm-svn: 372104
2019-09-17 18:52:09 +08:00
; RV32I-NEXT: lw a2, 0(a2)
[RISCV] Switch to the Machine Scheduler Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
2019-09-17 19:15:35 +08:00
; RV32I-NEXT: lw a3, 0(a1)
; RV32I-NEXT: lw a4, 4(a1)
; RV32I-NEXT: lw a5, 8(a1)
; RV32I-NEXT: lw a1, 12(a1)
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: sw a1, 20(sp)
; RV32I-NEXT: sw a5, 16(sp)
; RV32I-NEXT: sw a4, 12(sp)
[RISCV] Custom lower SHL_PARTS, SRA_PARTS, SRL_PARTS When not optimizing for minimum size (-Oz) we custom lower wide shifts (SHL_PARTS, SRA_PARTS, SRL_PARTS) instead of expanding to a libcall. Differential Revision: https://reviews.llvm.org/D59477 llvm-svn: 358498
2019-04-16 22:38:32 +08:00
; RV32I-NEXT: addi a0, sp, 24
; RV32I-NEXT: addi a1, sp, 8
[RISCV] Switch to the Machine Scheduler Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
2019-09-17 19:15:35 +08:00
; RV32I-NEXT: sw a3, 8(sp)
[RISCV] Custom lower SHL_PARTS, SRA_PARTS, SRL_PARTS When not optimizing for minimum size (-Oz) we custom lower wide shifts (SHL_PARTS, SRA_PARTS, SRL_PARTS) instead of expanding to a libcall. Differential Revision: https://reviews.llvm.org/D59477 llvm-svn: 358498
2019-04-16 22:38:32 +08:00
; RV32I-NEXT: call __ashrti3
; RV32I-NEXT: lw a0, 36(sp)
[RISCV] Switch to the Machine Scheduler Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
2019-09-17 19:15:35 +08:00
; RV32I-NEXT: lw a1, 32(sp)
; RV32I-NEXT: lw a2, 28(sp)
; RV32I-NEXT: lw a3, 24(sp)
[RISCV] Custom lower SHL_PARTS, SRA_PARTS, SRL_PARTS When not optimizing for minimum size (-Oz) we custom lower wide shifts (SHL_PARTS, SRA_PARTS, SRL_PARTS) instead of expanding to a libcall. Differential Revision: https://reviews.llvm.org/D59477 llvm-svn: 358498
2019-04-16 22:38:32 +08:00
; RV32I-NEXT: sw a0, 12(s0)
[RISCV] Switch to the Machine Scheduler Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
2019-09-17 19:15:35 +08:00
; RV32I-NEXT: sw a1, 8(s0)
; RV32I-NEXT: sw a2, 4(s0)
; RV32I-NEXT: sw a3, 0(s0)
[RISCV] Custom lower SHL_PARTS, SRA_PARTS, SRL_PARTS When not optimizing for minimum size (-Oz) we custom lower wide shifts (SHL_PARTS, SRA_PARTS, SRL_PARTS) instead of expanding to a libcall. Differential Revision: https://reviews.llvm.org/D59477 llvm-svn: 358498
2019-04-16 22:38:32 +08:00
; RV32I-NEXT: lw s0, 40(sp)
; RV32I-NEXT: lw ra, 44(sp)
; RV32I-NEXT: addi sp, sp, 48
; RV32I-NEXT: ret
;
; RV64I-LABEL: ashr128:
; RV64I: # %bb.0:
; RV64I-NEXT: addi a3, a2, -64
; RV64I-NEXT: bltz a3, .LBB7_2
; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: sra a0, a1, a3
; RV64I-NEXT: srai a1, a1, 63
; RV64I-NEXT: ret
; RV64I-NEXT: .LBB7_2:
[RISCV] Switch to the Machine Scheduler Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
2019-09-17 19:15:35 +08:00
; RV64I-NEXT: srl a0, a0, a2
[RISCV] Custom lower SHL_PARTS, SRA_PARTS, SRL_PARTS When not optimizing for minimum size (-Oz) we custom lower wide shifts (SHL_PARTS, SRA_PARTS, SRL_PARTS) instead of expanding to a libcall. Differential Revision: https://reviews.llvm.org/D59477 llvm-svn: 358498
2019-04-16 22:38:32 +08:00
; RV64I-NEXT: addi a3, zero, 63
; RV64I-NEXT: sub a3, a3, a2
; RV64I-NEXT: slli a4, a1, 1
; RV64I-NEXT: sll a3, a4, a3
; RV64I-NEXT: or a0, a0, a3
; RV64I-NEXT: sra a1, a1, a2
; RV64I-NEXT: ret
%1 = ashr i128 %a, %b
ret i128 %1
}
define i128 @shl128(i128 %a, i128 %b) nounwind {
; RV32I-LABEL: shl128:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -48
; RV32I-NEXT: sw ra, 44(sp)
; RV32I-NEXT: sw s0, 40(sp)
Revert Patch from Phabricator This reverts r372092 (git commit e38695a0255c9e7b53639f349f8101bae1ce5c04) llvm-svn: 372104
2019-09-17 18:52:09 +08:00
; RV32I-NEXT: lw a2, 0(a2)
[RISCV] Switch to the Machine Scheduler Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
2019-09-17 19:15:35 +08:00
; RV32I-NEXT: lw a3, 0(a1)
; RV32I-NEXT: lw a4, 4(a1)
; RV32I-NEXT: lw a5, 8(a1)
; RV32I-NEXT: lw a1, 12(a1)
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: sw a1, 20(sp)
; RV32I-NEXT: sw a5, 16(sp)
; RV32I-NEXT: sw a4, 12(sp)
[RISCV] Custom lower SHL_PARTS, SRA_PARTS, SRL_PARTS When not optimizing for minimum size (-Oz) we custom lower wide shifts (SHL_PARTS, SRA_PARTS, SRL_PARTS) instead of expanding to a libcall. Differential Revision: https://reviews.llvm.org/D59477 llvm-svn: 358498
2019-04-16 22:38:32 +08:00
; RV32I-NEXT: addi a0, sp, 24
; RV32I-NEXT: addi a1, sp, 8
[RISCV] Switch to the Machine Scheduler Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
2019-09-17 19:15:35 +08:00
; RV32I-NEXT: sw a3, 8(sp)
[RISCV] Custom lower SHL_PARTS, SRA_PARTS, SRL_PARTS When not optimizing for minimum size (-Oz) we custom lower wide shifts (SHL_PARTS, SRA_PARTS, SRL_PARTS) instead of expanding to a libcall. Differential Revision: https://reviews.llvm.org/D59477 llvm-svn: 358498
2019-04-16 22:38:32 +08:00
; RV32I-NEXT: call __ashlti3
; RV32I-NEXT: lw a0, 36(sp)
[RISCV] Switch to the Machine Scheduler Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
2019-09-17 19:15:35 +08:00
; RV32I-NEXT: lw a1, 32(sp)
; RV32I-NEXT: lw a2, 28(sp)
; RV32I-NEXT: lw a3, 24(sp)
[RISCV] Custom lower SHL_PARTS, SRA_PARTS, SRL_PARTS When not optimizing for minimum size (-Oz) we custom lower wide shifts (SHL_PARTS, SRA_PARTS, SRL_PARTS) instead of expanding to a libcall. Differential Revision: https://reviews.llvm.org/D59477 llvm-svn: 358498
2019-04-16 22:38:32 +08:00
; RV32I-NEXT: sw a0, 12(s0)
[RISCV] Switch to the Machine Scheduler Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
2019-09-17 19:15:35 +08:00
; RV32I-NEXT: sw a1, 8(s0)
; RV32I-NEXT: sw a2, 4(s0)
; RV32I-NEXT: sw a3, 0(s0)
[RISCV] Custom lower SHL_PARTS, SRA_PARTS, SRL_PARTS When not optimizing for minimum size (-Oz) we custom lower wide shifts (SHL_PARTS, SRA_PARTS, SRL_PARTS) instead of expanding to a libcall. Differential Revision: https://reviews.llvm.org/D59477 llvm-svn: 358498
2019-04-16 22:38:32 +08:00
; RV32I-NEXT: lw s0, 40(sp)
; RV32I-NEXT: lw ra, 44(sp)
; RV32I-NEXT: addi sp, sp, 48
; RV32I-NEXT: ret
;
; RV64I-LABEL: shl128:
; RV64I: # %bb.0:
; RV64I-NEXT: addi a3, a2, -64
; RV64I-NEXT: bltz a3, .LBB8_2
; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: sll a1, a0, a3
; RV64I-NEXT: mv a0, zero
; RV64I-NEXT: ret
; RV64I-NEXT: .LBB8_2:
[RISCV] Switch to the Machine Scheduler Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
2019-09-17 19:15:35 +08:00
; RV64I-NEXT: sll a1, a1, a2
[RISCV] Custom lower SHL_PARTS, SRA_PARTS, SRL_PARTS When not optimizing for minimum size (-Oz) we custom lower wide shifts (SHL_PARTS, SRA_PARTS, SRL_PARTS) instead of expanding to a libcall. Differential Revision: https://reviews.llvm.org/D59477 llvm-svn: 358498
2019-04-16 22:38:32 +08:00
; RV64I-NEXT: addi a3, zero, 63
; RV64I-NEXT: sub a3, a3, a2
; RV64I-NEXT: srli a4, a0, 1
; RV64I-NEXT: srl a3, a4, a3
; RV64I-NEXT: or a1, a1, a3
Reland [MachineCopyPropagation] Extend MCP to do trivial copy backward propagation. Fix assertion error ``` bool llvm::MachineOperand::isRenamable() const: Assertion `Register::isPhysicalRegister(getReg()) && "isRenamable should only be checked on physical registers"' failed. ``` by checking if the register is 0 before invoking `isRenamable`.
2019-12-05 14:01:00 +08:00
; RV64I-NEXT: sll a0, a0, a2
[RISCV] Custom lower SHL_PARTS, SRA_PARTS, SRL_PARTS When not optimizing for minimum size (-Oz) we custom lower wide shifts (SHL_PARTS, SRA_PARTS, SRL_PARTS) instead of expanding to a libcall. Differential Revision: https://reviews.llvm.org/D59477 llvm-svn: 358498
2019-04-16 22:38:32 +08:00
; RV64I-NEXT: ret
%1 = shl i128 %a, %b
ret i128 %1
}