2015-07-19 23:23:10 +08:00
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//===------------------------- __libunwind_config.h -----------------------===//
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//
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2019-01-19 18:56:40 +08:00
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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2015-07-19 23:23:10 +08:00
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//
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//===----------------------------------------------------------------------===//
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#ifndef ____LIBUNWIND_CONFIG_H__
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#define ____LIBUNWIND_CONFIG_H__
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#if defined(__arm__) && !defined(__USING_SJLJ_EXCEPTIONS__) && \
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!defined(__ARM_DWARF_EH__)
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2017-03-31 23:28:06 +08:00
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#define _LIBUNWIND_ARM_EHABI
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2015-07-19 23:23:10 +08:00
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#endif
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2017-10-29 04:19:49 +08:00
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#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_X86 8
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#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_X86_64 32
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#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_PPC 112
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2018-01-17 04:54:10 +08:00
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#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_PPC64 116
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2017-10-29 04:19:49 +08:00
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#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_ARM64 95
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2017-11-02 16:16:16 +08:00
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#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_ARM 287
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[OR1K] Add the EPCR special-purpose register to register state.
This makes it possible to unwind hardware exception stack frames,
which necessarily save every register and so need an extra column
for storing the return address. CFI for the exception handler could
then look as follows:
.globl exception_vector
exception_vector:
.cfi_startproc
.cfi_signal_frame
.cfi_return_column 32
l.addi r1, r1, -0x100
.cfi_def_cfa_offset 0x100
l.sw 0x00(r1), r2
.cfi_offset 2, 0x00-0x100
l.sw 0x04(r1), r3
.cfi_offset 3, 0x04-0x100
l.sw 0x08(r1), r4
.cfi_offset 4, 0x08-0x100
l.mfspr r3, r0, SPR_EPCR_BASE
l.sw 0x78(r1), r3
.cfi_offset 32, 0x78-0x100
l.jal exception_handler
l.nop
l.lwz r2, 0x00(r1)
l.lwz r3, 0x04(r1)
l.lwz r4, 0x08(r1)
l.jr r9
l.nop
.cfi_endproc
This register could, of course, also be accessed by the trace
callback or personality function, if so desired.
llvm-svn: 332513
2018-05-17 03:09:48 +08:00
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#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_OR1K 32
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2017-12-13 05:43:36 +08:00
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#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_MIPS 65
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[Sparc] Add Sparc V8 support
Summary:
Adds the register class implementation for Sparc.
Adds support for DW_CFA_GNU_window_save.
Adds save and restore context functionality.
Adds getArch() function to each Registers_ class to be able to separate
between DW_CFA_AARCH64_negate_ra_state and DW_CFA_GNU_window_save which
are both represented by the same constant.
On Sparc the return address is the address of the call instruction, so
an offset needs to be added when returning to skip the call instruction
and its delay slot. If the function returns a struct it is also necessary
to skip one extra instruction on Sparc V8.
Reviewers: jyknight, mclow.lists, mstorsjo, compnerd
Reviewed By: jyknight, compnerd
Subscribers: jgorbe, mgorny, christof, llvm-commits, fedor.sergeev, JDevlieghere, ldionne, libcxx-commits
Differential Revision: https://reviews.llvm.org/D55763
llvm-svn: 351044
2019-01-14 18:15:20 +08:00
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#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_SPARC 31
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[libunwind][RISCV] Add 64-bit RISC-V support
Summary:
Add unwinding support for 64-bit RISC-V.
This is from the FreeBSD implementation with the following minor
changes:
- Renamed and renumbered DWARF registers to match the RISC-V ABI [1]
- Use the ABI mneumonics in getRegisterName() instead of the exact
register names
- Include checks for __riscv_xlen == 64 to facilitate adding the 32-bit
ABI in the future.
[1] https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md
Patch by Mitchell Horne (mhorne)
Reviewers: lenary, luismarques, compnerd, phosek
Reviewed By: lenary, luismarques
Subscribers: arichardson, sameer.abuasal, abidh, asb, aprantl, krytarowski, simoncook, kito-cheng, christof, shiva0217, rogfer01, rkruppe, PkmX, psnobl, benna, lenary, s.egerton, luismarques, emaste, cfe-commits
Differential Revision: https://reviews.llvm.org/D68362
2019-12-17 00:35:17 +08:00
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#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_RISCV 64
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2017-10-29 04:19:49 +08:00
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2016-05-25 20:36:34 +08:00
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#if defined(_LIBUNWIND_IS_NATIVE_ONLY)
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# if defined(__i386__)
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2017-03-31 23:28:06 +08:00
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# define _LIBUNWIND_TARGET_I386
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2016-05-25 20:36:34 +08:00
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# define _LIBUNWIND_CONTEXT_SIZE 8
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2017-10-31 03:06:34 +08:00
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# define _LIBUNWIND_CURSOR_SIZE 15
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2017-10-29 04:19:49 +08:00
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# define _LIBUNWIND_HIGHEST_DWARF_REGISTER _LIBUNWIND_HIGHEST_DWARF_REGISTER_X86
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2016-05-25 20:36:34 +08:00
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# elif defined(__x86_64__)
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# define _LIBUNWIND_TARGET_X86_64 1
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2017-10-27 16:11:36 +08:00
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# if defined(_WIN64)
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# define _LIBUNWIND_CONTEXT_SIZE 54
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Add support for SEH unwinding on Windows.
Summary:
I've tested this implementation on x86-64 to ensure that it works. All
`libc++abi` tests pass, as do all `libc++` exception-related tests. ARM
still remains to be implemented (@compnerd?).
Special thanks to KJK::Hyperion for his excellent series of articles on
how EH works on x86-64 Windows. (Seriously, check it out. It's awesome.)
I'm actually not sure if this should go in as is. I particularly don't
like that I duplicated the UnwindCursor class for this special case.
Reviewers: mstorsjo, rnk, compnerd, smeenai, javed.absar
Subscribers: mgorny, kristof.beyls, christof, chrib, cfe-commits, compnerd, llvm-commits
Differential Revision: https://reviews.llvm.org/D50564
llvm-svn: 341125
2018-08-31 05:29:00 +08:00
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# ifdef __SEH__
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# define _LIBUNWIND_CURSOR_SIZE 204
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# else
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# define _LIBUNWIND_CURSOR_SIZE 66
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# endif
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2017-10-27 16:11:36 +08:00
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# else
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# define _LIBUNWIND_CONTEXT_SIZE 21
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# define _LIBUNWIND_CURSOR_SIZE 33
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# endif
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2017-10-29 04:19:49 +08:00
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# define _LIBUNWIND_HIGHEST_DWARF_REGISTER _LIBUNWIND_HIGHEST_DWARF_REGISTER_X86_64
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2018-01-03 06:11:30 +08:00
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# elif defined(__powerpc64__)
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# define _LIBUNWIND_TARGET_PPC64 1
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2018-01-17 04:54:10 +08:00
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# define _LIBUNWIND_CONTEXT_SIZE 167
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# define _LIBUNWIND_CURSOR_SIZE 179
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2018-01-03 06:11:30 +08:00
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# define _LIBUNWIND_HIGHEST_DWARF_REGISTER _LIBUNWIND_HIGHEST_DWARF_REGISTER_PPC64
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2016-05-25 20:36:34 +08:00
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# elif defined(__ppc__)
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# define _LIBUNWIND_TARGET_PPC 1
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# define _LIBUNWIND_CONTEXT_SIZE 117
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2017-10-31 03:06:34 +08:00
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# define _LIBUNWIND_CURSOR_SIZE 124
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2017-10-29 04:19:49 +08:00
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# define _LIBUNWIND_HIGHEST_DWARF_REGISTER _LIBUNWIND_HIGHEST_DWARF_REGISTER_PPC
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2016-05-25 20:36:34 +08:00
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# elif defined(__aarch64__)
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# define _LIBUNWIND_TARGET_AARCH64 1
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# define _LIBUNWIND_CONTEXT_SIZE 66
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2018-12-19 04:05:59 +08:00
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# if defined(__SEH__)
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# define _LIBUNWIND_CURSOR_SIZE 164
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# else
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# define _LIBUNWIND_CURSOR_SIZE 78
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# endif
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2017-10-29 04:19:49 +08:00
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# define _LIBUNWIND_HIGHEST_DWARF_REGISTER _LIBUNWIND_HIGHEST_DWARF_REGISTER_ARM64
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2016-05-25 20:36:34 +08:00
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# elif defined(__arm__)
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# define _LIBUNWIND_TARGET_ARM 1
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Add support for SEH unwinding on Windows.
Summary:
I've tested this implementation on x86-64 to ensure that it works. All
`libc++abi` tests pass, as do all `libc++` exception-related tests. ARM
still remains to be implemented (@compnerd?).
Special thanks to KJK::Hyperion for his excellent series of articles on
how EH works on x86-64 Windows. (Seriously, check it out. It's awesome.)
I'm actually not sure if this should go in as is. I particularly don't
like that I duplicated the UnwindCursor class for this special case.
Reviewers: mstorsjo, rnk, compnerd, smeenai, javed.absar
Subscribers: mgorny, kristof.beyls, christof, chrib, cfe-commits, compnerd, llvm-commits
Differential Revision: https://reviews.llvm.org/D50564
llvm-svn: 341125
2018-08-31 05:29:00 +08:00
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# if defined(__SEH__)
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# define _LIBUNWIND_CONTEXT_SIZE 42
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2018-08-31 22:56:55 +08:00
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# define _LIBUNWIND_CURSOR_SIZE 80
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Add support for SEH unwinding on Windows.
Summary:
I've tested this implementation on x86-64 to ensure that it works. All
`libc++abi` tests pass, as do all `libc++` exception-related tests. ARM
still remains to be implemented (@compnerd?).
Special thanks to KJK::Hyperion for his excellent series of articles on
how EH works on x86-64 Windows. (Seriously, check it out. It's awesome.)
I'm actually not sure if this should go in as is. I particularly don't
like that I duplicated the UnwindCursor class for this special case.
Reviewers: mstorsjo, rnk, compnerd, smeenai, javed.absar
Subscribers: mgorny, kristof.beyls, christof, chrib, cfe-commits, compnerd, llvm-commits
Differential Revision: https://reviews.llvm.org/D50564
llvm-svn: 341125
2018-08-31 05:29:00 +08:00
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# elif defined(__ARM_WMMX)
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2017-10-25 16:07:19 +08:00
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# define _LIBUNWIND_CONTEXT_SIZE 61
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# define _LIBUNWIND_CURSOR_SIZE 68
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2016-07-07 18:55:39 +08:00
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# else
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# define _LIBUNWIND_CONTEXT_SIZE 42
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# define _LIBUNWIND_CURSOR_SIZE 49
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# endif
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2017-10-29 04:19:49 +08:00
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# define _LIBUNWIND_HIGHEST_DWARF_REGISTER _LIBUNWIND_HIGHEST_DWARF_REGISTER_ARM
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2016-05-25 20:36:34 +08:00
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# elif defined(__or1k__)
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# define _LIBUNWIND_TARGET_OR1K 1
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# define _LIBUNWIND_CONTEXT_SIZE 16
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2017-10-31 03:06:34 +08:00
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# define _LIBUNWIND_CURSOR_SIZE 24
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2017-10-29 04:19:49 +08:00
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# define _LIBUNWIND_HIGHEST_DWARF_REGISTER _LIBUNWIND_HIGHEST_DWARF_REGISTER_OR1K
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2017-12-13 05:43:36 +08:00
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# elif defined(__mips__)
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2018-05-16 06:44:56 +08:00
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# if defined(_ABIO32) && _MIPS_SIM == _ABIO32
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2017-12-13 05:43:36 +08:00
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# define _LIBUNWIND_TARGET_MIPS_O32 1
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2018-05-16 06:44:56 +08:00
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# if defined(__mips_hard_float)
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# define _LIBUNWIND_CONTEXT_SIZE 50
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# define _LIBUNWIND_CURSOR_SIZE 57
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# else
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# define _LIBUNWIND_CONTEXT_SIZE 18
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# define _LIBUNWIND_CURSOR_SIZE 24
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# endif
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# elif defined(_ABIN32) && _MIPS_SIM == _ABIN32
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2018-02-28 05:24:02 +08:00
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# define _LIBUNWIND_TARGET_MIPS_NEWABI 1
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2018-05-16 06:44:56 +08:00
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# if defined(__mips_hard_float)
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# define _LIBUNWIND_CONTEXT_SIZE 67
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# define _LIBUNWIND_CURSOR_SIZE 74
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# else
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# define _LIBUNWIND_CONTEXT_SIZE 35
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# define _LIBUNWIND_CURSOR_SIZE 42
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# endif
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# elif defined(_ABI64) && _MIPS_SIM == _ABI64
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2018-01-10 01:07:18 +08:00
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# define _LIBUNWIND_TARGET_MIPS_NEWABI 1
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2018-05-16 06:44:56 +08:00
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# if defined(__mips_hard_float)
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# define _LIBUNWIND_CONTEXT_SIZE 67
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# define _LIBUNWIND_CURSOR_SIZE 79
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# else
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# define _LIBUNWIND_CONTEXT_SIZE 35
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# define _LIBUNWIND_CURSOR_SIZE 47
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# endif
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2017-12-13 05:43:36 +08:00
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# else
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# error "Unsupported MIPS ABI and/or environment"
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# endif
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# define _LIBUNWIND_HIGHEST_DWARF_REGISTER _LIBUNWIND_HIGHEST_DWARF_REGISTER_MIPS
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[Sparc] Add Sparc V8 support
Summary:
Adds the register class implementation for Sparc.
Adds support for DW_CFA_GNU_window_save.
Adds save and restore context functionality.
Adds getArch() function to each Registers_ class to be able to separate
between DW_CFA_AARCH64_negate_ra_state and DW_CFA_GNU_window_save which
are both represented by the same constant.
On Sparc the return address is the address of the call instruction, so
an offset needs to be added when returning to skip the call instruction
and its delay slot. If the function returns a struct it is also necessary
to skip one extra instruction on Sparc V8.
Reviewers: jyknight, mclow.lists, mstorsjo, compnerd
Reviewed By: jyknight, compnerd
Subscribers: jgorbe, mgorny, christof, llvm-commits, fedor.sergeev, JDevlieghere, ldionne, libcxx-commits
Differential Revision: https://reviews.llvm.org/D55763
llvm-svn: 351044
2019-01-14 18:15:20 +08:00
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# elif defined(__sparc__)
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#define _LIBUNWIND_TARGET_SPARC 1
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#define _LIBUNWIND_HIGHEST_DWARF_REGISTER _LIBUNWIND_HIGHEST_DWARF_REGISTER_SPARC
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#define _LIBUNWIND_CONTEXT_SIZE 16
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#define _LIBUNWIND_CURSOR_SIZE 23
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[libunwind][RISCV] Add 64-bit RISC-V support
Summary:
Add unwinding support for 64-bit RISC-V.
This is from the FreeBSD implementation with the following minor
changes:
- Renamed and renumbered DWARF registers to match the RISC-V ABI [1]
- Use the ABI mneumonics in getRegisterName() instead of the exact
register names
- Include checks for __riscv_xlen == 64 to facilitate adding the 32-bit
ABI in the future.
[1] https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md
Patch by Mitchell Horne (mhorne)
Reviewers: lenary, luismarques, compnerd, phosek
Reviewed By: lenary, luismarques
Subscribers: arichardson, sameer.abuasal, abidh, asb, aprantl, krytarowski, simoncook, kito-cheng, christof, shiva0217, rogfer01, rkruppe, PkmX, psnobl, benna, lenary, s.egerton, luismarques, emaste, cfe-commits
Differential Revision: https://reviews.llvm.org/D68362
2019-12-17 00:35:17 +08:00
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# elif defined(__riscv)
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# if __riscv_xlen == 64
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# define _LIBUNWIND_TARGET_RISCV 1
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# define _LIBUNWIND_CONTEXT_SIZE 64
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# define _LIBUNWIND_CURSOR_SIZE 76
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# else
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# error "Unsupported RISC-V ABI"
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# endif
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# define _LIBUNWIND_HIGHEST_DWARF_REGISTER _LIBUNWIND_HIGHEST_DWARF_REGISTER_RISCV
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2016-05-25 20:36:34 +08:00
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# else
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# error "Unsupported architecture."
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# endif
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#else // !_LIBUNWIND_IS_NATIVE_ONLY
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2017-03-31 23:28:06 +08:00
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# define _LIBUNWIND_TARGET_I386
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2016-05-25 20:36:34 +08:00
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# define _LIBUNWIND_TARGET_X86_64 1
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# define _LIBUNWIND_TARGET_PPC 1
|
2018-01-03 06:11:30 +08:00
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# define _LIBUNWIND_TARGET_PPC64 1
|
2016-05-25 20:36:34 +08:00
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# define _LIBUNWIND_TARGET_AARCH64 1
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# define _LIBUNWIND_TARGET_ARM 1
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# define _LIBUNWIND_TARGET_OR1K 1
|
2017-12-13 05:43:36 +08:00
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# define _LIBUNWIND_TARGET_MIPS_O32 1
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2018-01-10 01:07:18 +08:00
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# define _LIBUNWIND_TARGET_MIPS_NEWABI 1
|
[Sparc] Add Sparc V8 support
Summary:
Adds the register class implementation for Sparc.
Adds support for DW_CFA_GNU_window_save.
Adds save and restore context functionality.
Adds getArch() function to each Registers_ class to be able to separate
between DW_CFA_AARCH64_negate_ra_state and DW_CFA_GNU_window_save which
are both represented by the same constant.
On Sparc the return address is the address of the call instruction, so
an offset needs to be added when returning to skip the call instruction
and its delay slot. If the function returns a struct it is also necessary
to skip one extra instruction on Sparc V8.
Reviewers: jyknight, mclow.lists, mstorsjo, compnerd
Reviewed By: jyknight, compnerd
Subscribers: jgorbe, mgorny, christof, llvm-commits, fedor.sergeev, JDevlieghere, ldionne, libcxx-commits
Differential Revision: https://reviews.llvm.org/D55763
llvm-svn: 351044
2019-01-14 18:15:20 +08:00
|
|
|
# define _LIBUNWIND_TARGET_SPARC 1
|
[libunwind][RISCV] Add 64-bit RISC-V support
Summary:
Add unwinding support for 64-bit RISC-V.
This is from the FreeBSD implementation with the following minor
changes:
- Renamed and renumbered DWARF registers to match the RISC-V ABI [1]
- Use the ABI mneumonics in getRegisterName() instead of the exact
register names
- Include checks for __riscv_xlen == 64 to facilitate adding the 32-bit
ABI in the future.
[1] https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md
Patch by Mitchell Horne (mhorne)
Reviewers: lenary, luismarques, compnerd, phosek
Reviewed By: lenary, luismarques
Subscribers: arichardson, sameer.abuasal, abidh, asb, aprantl, krytarowski, simoncook, kito-cheng, christof, shiva0217, rogfer01, rkruppe, PkmX, psnobl, benna, lenary, s.egerton, luismarques, emaste, cfe-commits
Differential Revision: https://reviews.llvm.org/D68362
2019-12-17 00:35:17 +08:00
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# define _LIBUNWIND_TARGET_RISCV 1
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2018-01-17 04:54:10 +08:00
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# define _LIBUNWIND_CONTEXT_SIZE 167
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# define _LIBUNWIND_CURSOR_SIZE 179
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2017-11-02 16:16:16 +08:00
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# define _LIBUNWIND_HIGHEST_DWARF_REGISTER 287
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2016-05-25 20:36:34 +08:00
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#endif // _LIBUNWIND_IS_NATIVE_ONLY
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2015-07-19 23:23:10 +08:00
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#endif // ____LIBUNWIND_CONFIG_H__
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