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llvm-project/llvm/test/CodeGen/R600/trunc.ll

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R600/SI: Use -verify-machineinstrs for most tests We can't enable the verifier for tests with SI_IF and SI_ELSE, because these instructions are always followed by a COPY which copies their result to the next basic block. This violates the machine verifier's rule that non-terminators can not folow terminators. Reviewed-by: Vincent Lejeune<vljn at ovi.com> llvm-svn: 192366
2013-10-11 01:11:46 +08:00
; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI %s
R600: Fix i64 to i32 trunc on SI llvm-svn: 190091
2013-09-06 03:41:10 +08:00
; RUN: llc -march=r600 -mcpu=cypress < %s | FileCheck -check-prefix=EG %s
define void @trunc_i64_to_i32_store(i32 addrspace(1)* %out, i64 %in) {
; SI-LABEL: @trunc_i64_to_i32_store
R600/SI: Print more immediates in hex format Print in decimal for inline immediates, and hex otherwise. Use hex always for offsets in addressing offsets. This approximately matches what the shader compiler does. llvm-svn: 206335
2014-04-16 06:32:49 +08:00
; SI: S_LOAD_DWORD s0, s[0:1], 0xb
R600/SI: Change formatting of printed registers. Print the range of registers used with a single letter prefix. This better matches what the shader compiler produces and is overall less obnoxious than concatenating all of the subregister names together. Instead of SGPR0, it will print s0. Instead of SGPR0_SGPR1, it will print s[0:1] and so on. There doesn't appear to be a straightforward way to get the actual register info in the InstPrinter, so this parses the generated name to print with the new syntax. The required test changes are pretty nasty, and register matching regexes are now worse. Since there isn't a way to add to a variable in FileCheck, some of the tests now don't check the exact number of registers used, but I don't think that will be a real problem. llvm-svn: 194443
2013-11-12 10:35:51 +08:00
; SI: V_MOV_B32_e32 v0, s0
; SI: BUFFER_STORE_DWORD v0
R600: Fix i64 to i32 trunc on SI llvm-svn: 190091
2013-09-06 03:41:10 +08:00
; EG-LABEL: @trunc_i64_to_i32_store
; EG: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
; EG: LSHR
; EG-NEXT: 2(
%result = trunc i64 %in to i32 store i32 %result, i32 addrspace(1)* %out, align 4
ret void
}
R600: Implement isNarrowingProfitable. llvm-svn: 204658
2014-03-25 03:43:31 +08:00
; SI-LABEL: @trunc_load_shl_i64:
; SI-DAG: S_LOAD_DWORDX2
; SI-DAG: S_LOAD_DWORD [[SREG:s[0-9]+]],
; SI: S_LSHL_B32 [[SHL:s[0-9]+]], [[SREG]], 2
; SI: V_MOV_B32_e32 [[VSHL:v[0-9]+]], [[SHL]]
; SI: BUFFER_STORE_DWORD [[VSHL]],
define void @trunc_load_shl_i64(i32 addrspace(1)* %out, i64 %a) {
%b = shl i64 %a, 2
%result = trunc i64 %b to i32
store i32 %result, i32 addrspace(1)* %out, align 4
ret void
}
R600: Fix trunc i64 to i32 on SI llvm-svn: 192375
2013-10-11 02:04:16 +08:00
; SI-LABEL: @trunc_shl_i64:
R600/SI: Implement areLoadsFromSameBasePtr This currently has a noticable effect on the kernel argument loads. LDS and global loads are more problematic, I think because of how copies are currently inserted to ensure that the address is a VGPR. llvm-svn: 214942
2014-08-06 08:29:43 +08:00
; SI: S_LOAD_DWORDX2 s{{\[}}[[LO_SREG:[0-9]+]]:{{[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0xd
; SI: S_ADD_I32 s[[LO_SREG2:[0-9]+]], s[[LO_SREG]],
; SI: S_ADDC_U32
; SI: S_LSHL_B64 s{{\[}}[[LO_SHL:[0-9]+]]:{{[0-9]+\]}}, s{{\[}}[[LO_SREG2]]:{{[0-9]+\]}}, 2
; SI: V_MOV_B32_e32 v[[LO_VREG:[0-9]+]], s[[LO_SHL]]
R600/SI: Change formatting of printed registers. Print the range of registers used with a single letter prefix. This better matches what the shader compiler produces and is overall less obnoxious than concatenating all of the subregister names together. Instead of SGPR0, it will print s0. Instead of SGPR0_SGPR1, it will print s[0:1] and so on. There doesn't appear to be a straightforward way to get the actual register info in the InstPrinter, so this parses the generated name to print with the new syntax. The required test changes are pretty nasty, and register matching regexes are now worse. Since there isn't a way to add to a variable in FileCheck, some of the tests now don't check the exact number of registers used, but I don't think that will be a real problem. llvm-svn: 194443
2013-11-12 10:35:51 +08:00
; SI: BUFFER_STORE_DWORD v[[LO_VREG]],
R600: Implement isZExtFree. This allows 64-bit operations that are truncated to be reduced to 32-bit ones. llvm-svn: 204946
2014-03-28 01:23:31 +08:00
define void @trunc_shl_i64(i64 addrspace(1)* %out2, i32 addrspace(1)* %out, i64 %a) {
R600: Implement isNarrowingProfitable. llvm-svn: 204658
2014-03-25 03:43:31 +08:00
%aa = add i64 %a, 234 ; Prevent shrinking store.
%b = shl i64 %aa, 2
R600: Fix trunc i64 to i32 on SI llvm-svn: 192375
2013-10-11 02:04:16 +08:00
%result = trunc i64 %b to i32
store i32 %result, i32 addrspace(1)* %out, align 4
R600: Implement isZExtFree. This allows 64-bit operations that are truncated to be reduced to 32-bit ones. llvm-svn: 204946
2014-03-28 01:23:31 +08:00
store i64 %b, i64 addrspace(1)* %out2, align 8 ; Prevent reducing ops to 32-bits
R600: Fix trunc i64 to i32 on SI llvm-svn: 192375
2013-10-11 02:04:16 +08:00
ret void
}
R600/SI: Add pattern for truncating i32 to i1 Fixes half a dozen piglit tests with radeonsi. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 200283
2014-01-28 11:01:16 +08:00
; SI-LABEL: @trunc_i32_to_i1:
; SI: V_AND_B32
; SI: V_CMP_EQ_I32
define void @trunc_i32_to_i1(i32 addrspace(1)* %out, i32 %a) {
%trunc = trunc i32 %a to i1
%result = select i1 %trunc, i32 1, i32 0
store i32 %result, i32 addrspace(1)* %out, align 4
ret void
}