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[FPEnv] Expand constrained FP operations Add a helper function to expand constrained FP operations as needed. Note that the Strict POWI operation is not handled in this patch since the format is slightly different from the others. Differential Revision: https://reviews.llvm.org/D47491 llvm-svn: 334603
2018-06-13 22:32:12 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
[FPEnv] Expand constrained FP POWI Modify ExpandStrictFPOp(...) to handle nodes that have scalar operands. Also, add a Strict FMA test and do some other light cleanup in the Strict FP code. Differential Revision: https://reviews.llvm.org/D48149 llvm-svn: 334863
2018-06-16 04:57:55 +08:00
; RUN: llc -O3 -mtriple=x86_64-pc-linux < %s | FileCheck --check-prefix=COMMON --check-prefix=NO-FMA --check-prefix=FMACALL64 --check-prefix=FMACALL32 %s
; RUN: llc -O3 -mtriple=x86_64-pc-linux -mattr=+fma < %s | FileCheck -check-prefix=COMMON --check-prefix=HAS-FMA --check-prefix=FMA64 --check-prefix=FMA32 %s
[FPEnv] Expand constrained FP operations Add a helper function to expand constrained FP operations as needed. Note that the Strict POWI operation is not handled in this patch since the format is slightly different from the others. Differential Revision: https://reviews.llvm.org/D47491 llvm-svn: 334603
2018-06-13 22:32:12 +08:00
[FPEnv] Scalarize StrictFP vector operations Add a helper function to scalarize constrained FP operations as needed. Differential Revision: https://reviews.llvm.org/D50720 llvm-svn: 339735
2018-08-15 06:13:11 +08:00
define <1 x float> @constrained_vector_fdiv_v1f32() {
; NO-FMA-LABEL: constrained_vector_fdiv_v1f32:
; NO-FMA: # %bb.0: # %entry
; NO-FMA-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; NO-FMA-NEXT: divss {{.*}}(%rip), %xmm0
; NO-FMA-NEXT: retq
;
; HAS-FMA-LABEL: constrained_vector_fdiv_v1f32:
; HAS-FMA: # %bb.0: # %entry
; HAS-FMA-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; HAS-FMA-NEXT: vdivss {{.*}}(%rip), %xmm0, %xmm0
; HAS-FMA-NEXT: retq
entry:
%div = call <1 x float> @llvm.experimental.constrained.fdiv.v1f32(
<1 x float> <float 1.000000e+00>,
<1 x float> <float 1.000000e+01>,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <1 x float> %div
}
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
define <2 x double> @constrained_vector_fdiv_v2f64() {
; NO-FMA-LABEL: constrained_vector_fdiv_v2f64:
[FPEnv] Expand constrained FP POWI Modify ExpandStrictFPOp(...) to handle nodes that have scalar operands. Also, add a Strict FMA test and do some other light cleanup in the Strict FP code. Differential Revision: https://reviews.llvm.org/D48149 llvm-svn: 334863
2018-06-16 04:57:55 +08:00
; NO-FMA: # %bb.0: # %entry
[X86] Force floating point values in constant pool decoding to print in scientific notation so they can't be confused with integers. When the floating point constants are whole numbers they have no decimal point so look like integers, but mean something very different in something like an 'and' instruction. Ideally we would just print a decimal point and a 0, but I couldn't see how to make APFloat::toString do that. llvm-svn: 345488
2018-10-29 12:52:04 +08:00
; NO-FMA-NEXT: movapd {{.*#+}} xmm0 = [1.0E+0,2.0E+0]
[FPEnv] Expand constrained FP POWI Modify ExpandStrictFPOp(...) to handle nodes that have scalar operands. Also, add a Strict FMA test and do some other light cleanup in the Strict FP code. Differential Revision: https://reviews.llvm.org/D48149 llvm-svn: 334863
2018-06-16 04:57:55 +08:00
; NO-FMA-NEXT: divpd {{.*}}(%rip), %xmm0
; NO-FMA-NEXT: retq
;
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
; HAS-FMA-LABEL: constrained_vector_fdiv_v2f64:
[FPEnv] Expand constrained FP POWI Modify ExpandStrictFPOp(...) to handle nodes that have scalar operands. Also, add a Strict FMA test and do some other light cleanup in the Strict FP code. Differential Revision: https://reviews.llvm.org/D48149 llvm-svn: 334863
2018-06-16 04:57:55 +08:00
; HAS-FMA: # %bb.0: # %entry
[X86] Force floating point values in constant pool decoding to print in scientific notation so they can't be confused with integers. When the floating point constants are whole numbers they have no decimal point so look like integers, but mean something very different in something like an 'and' instruction. Ideally we would just print a decimal point and a 0, but I couldn't see how to make APFloat::toString do that. llvm-svn: 345488
2018-10-29 12:52:04 +08:00
; HAS-FMA-NEXT: vmovapd {{.*#+}} xmm0 = [1.0E+0,2.0E+0]
[FPEnv] Expand constrained FP POWI Modify ExpandStrictFPOp(...) to handle nodes that have scalar operands. Also, add a Strict FMA test and do some other light cleanup in the Strict FP code. Differential Revision: https://reviews.llvm.org/D48149 llvm-svn: 334863
2018-06-16 04:57:55 +08:00
; HAS-FMA-NEXT: vdivpd {{.*}}(%rip), %xmm0, %xmm0
; HAS-FMA-NEXT: retq
[FPEnv] Expand constrained FP operations Add a helper function to expand constrained FP operations as needed. Note that the Strict POWI operation is not handled in this patch since the format is slightly different from the others. Differential Revision: https://reviews.llvm.org/D47491 llvm-svn: 334603
2018-06-13 22:32:12 +08:00
entry:
%div = call <2 x double> @llvm.experimental.constrained.fdiv.v2f64(
<2 x double> <double 1.000000e+00, double 2.000000e+00>,
<2 x double> <double 1.000000e+01, double 1.000000e+01>,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <2 x double> %div
}
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
define <3 x float> @constrained_vector_fdiv_v3f32() {
; NO-FMA-LABEL: constrained_vector_fdiv_v3f32:
; NO-FMA: # %bb.0: # %entry
; NO-FMA-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; NO-FMA-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; NO-FMA-NEXT: divss %xmm1, %xmm2
; NO-FMA-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; NO-FMA-NEXT: divss %xmm1, %xmm0
; NO-FMA-NEXT: movss {{.*#+}} xmm3 = mem[0],zero,zero,zero
; NO-FMA-NEXT: divss %xmm1, %xmm3
; NO-FMA-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1]
; NO-FMA-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0]
; NO-FMA-NEXT: retq
;
; HAS-FMA-LABEL: constrained_vector_fdiv_v3f32:
; HAS-FMA: # %bb.0: # %entry
; HAS-FMA-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; HAS-FMA-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; HAS-FMA-NEXT: vdivss %xmm0, %xmm1, %xmm1
; HAS-FMA-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; HAS-FMA-NEXT: vdivss %xmm0, %xmm2, %xmm2
; HAS-FMA-NEXT: vmovss {{.*#+}} xmm3 = mem[0],zero,zero,zero
; HAS-FMA-NEXT: vdivss %xmm0, %xmm3, %xmm0
; HAS-FMA-NEXT: vinsertps {{.*#+}} xmm0 = xmm2[0],xmm0[0],xmm2[2,3]
; HAS-FMA-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0],xmm0[3]
; HAS-FMA-NEXT: retq
entry:
%div = call <3 x float> @llvm.experimental.constrained.fdiv.v3f32(
<3 x float> <float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>,
<3 x float> <float 1.000000e+01, float 1.000000e+01, float 1.000000e+01>,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <3 x float> %div
}
define <3 x double> @constrained_vector_fdiv_v3f64() {
; NO-FMA-LABEL: constrained_vector_fdiv_v3f64:
; NO-FMA: # %bb.0: # %entry
[X86] Force floating point values in constant pool decoding to print in scientific notation so they can't be confused with integers. When the floating point constants are whole numbers they have no decimal point so look like integers, but mean something very different in something like an 'and' instruction. Ideally we would just print a decimal point and a 0, but I couldn't see how to make APFloat::toString do that. llvm-svn: 345488
2018-10-29 12:52:04 +08:00
; NO-FMA-NEXT: movapd {{.*#+}} xmm0 = [1.0E+0,2.0E+0]
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
; NO-FMA-NEXT: divpd {{.*}}(%rip), %xmm0
; NO-FMA-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
; NO-FMA-NEXT: divsd {{.*}}(%rip), %xmm1
; NO-FMA-NEXT: movsd %xmm1, -{{[0-9]+}}(%rsp)
; NO-FMA-NEXT: movapd %xmm0, %xmm1
[X86] Prefer unpckhpd over movhlps in isel for fake unary cases In r337348, I changed lowering to prefer X86ISD::UNPCKL/UNPCKH opcodes over MOVLHPS/MOVHLPS for v2f64 {0,0} and {1,1} shuffles when we have SSE2. This enabled the removal of a bunch of weirdly bitcasted isel patterns in r337349. To avoid changing the tests I placed a gross hack in isel to still emit movhlps instructions for fake unary unpckh nodes. A similar hack was not needed for unpckl and movlhps because we do execution domain switching for those. But unpckh and movhlps have swapped operand order. This patch removes the hack. This is a code size increase since unpckhpd requires a 0x66 prefix and movhlps does not. But if that's a big concern we should be using movhlps for all unpckhpd opcodes and let commuteInstruction turnit into unpckhpd when its an advantage. Differential Revision: https://reviews.llvm.org/D49499 llvm-svn: 341973
2018-09-12 01:57:27 +08:00
; NO-FMA-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
; NO-FMA-NEXT: fldl -{{[0-9]+}}(%rsp)
; NO-FMA-NEXT: retq
;
; HAS-FMA-LABEL: constrained_vector_fdiv_v3f64:
; HAS-FMA: # %bb.0: # %entry
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: vdivsd {{.*}}(%rip), %xmm0, %xmm0
[X86] Force floating point values in constant pool decoding to print in scientific notation so they can't be confused with integers. When the floating point constants are whole numbers they have no decimal point so look like integers, but mean something very different in something like an 'and' instruction. Ideally we would just print a decimal point and a 0, but I couldn't see how to make APFloat::toString do that. llvm-svn: 345488
2018-10-29 12:52:04 +08:00
; HAS-FMA-NEXT: vmovapd {{.*#+}} xmm1 = [1.0E+0,2.0E+0]
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
; HAS-FMA-NEXT: vdivpd {{.*}}(%rip), %xmm1, %xmm1
; HAS-FMA-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; HAS-FMA-NEXT: retq
entry:
%div = call <3 x double> @llvm.experimental.constrained.fdiv.v3f64(
<3 x double> <double 1.000000e+00, double 2.000000e+00, double 3.000000e+00>,
<3 x double> <double 1.000000e+01, double 1.000000e+01, double 1.000000e+01>,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <3 x double> %div
}
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
define <4 x double> @constrained_vector_fdiv_v4f64() {
; NO-FMA-LABEL: constrained_vector_fdiv_v4f64:
[FPEnv] Support constrained FREM intrinsic Differential Revision: https://reviews.llvm.org/D50975 llvm-svn: 340201
2018-08-21 03:28:56 +08:00
; NO-FMA: # %bb.0: # %entry
[X86] Force floating point values in constant pool decoding to print in scientific notation so they can't be confused with integers. When the floating point constants are whole numbers they have no decimal point so look like integers, but mean something very different in something like an 'and' instruction. Ideally we would just print a decimal point and a 0, but I couldn't see how to make APFloat::toString do that. llvm-svn: 345488
2018-10-29 12:52:04 +08:00
; NO-FMA-NEXT: movapd {{.*#+}} xmm2 = [1.0E+1,1.0E+1]
; NO-FMA-NEXT: movapd {{.*#+}} xmm0 = [1.0E+0,2.0E+0]
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
; NO-FMA-NEXT: divpd %xmm2, %xmm0
[X86] Force floating point values in constant pool decoding to print in scientific notation so they can't be confused with integers. When the floating point constants are whole numbers they have no decimal point so look like integers, but mean something very different in something like an 'and' instruction. Ideally we would just print a decimal point and a 0, but I couldn't see how to make APFloat::toString do that. llvm-svn: 345488
2018-10-29 12:52:04 +08:00
; NO-FMA-NEXT: movapd {{.*#+}} xmm1 = [3.0E+0,4.0E+0]
Fix corruption of result number in LegalizeVectorOps.cpp When VectorLegalizer::LegalizeOp creates a new SDValue after iterating over its arguments, we need to refer to the same result number of the new node that the original value used. Reviewed by: cameron.mcinally Differential Revision: https://reviews.llvm.org/D49805 llvm-svn: 337939
2018-07-26 01:08:13 +08:00
; NO-FMA-NEXT: divpd %xmm2, %xmm1
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
; NO-FMA-NEXT: retq
;
; HAS-FMA-LABEL: constrained_vector_fdiv_v4f64:
[FPEnv] Support constrained FREM intrinsic Differential Revision: https://reviews.llvm.org/D50975 llvm-svn: 340201
2018-08-21 03:28:56 +08:00
; HAS-FMA: # %bb.0: # %entry
[X86] Force floating point values in constant pool decoding to print in scientific notation so they can't be confused with integers. When the floating point constants are whole numbers they have no decimal point so look like integers, but mean something very different in something like an 'and' instruction. Ideally we would just print a decimal point and a 0, but I couldn't see how to make APFloat::toString do that. llvm-svn: 345488
2018-10-29 12:52:04 +08:00
; HAS-FMA-NEXT: vmovapd {{.*#+}} ymm0 = [1.0E+0,2.0E+0,3.0E+0,4.0E+0]
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
; HAS-FMA-NEXT: vdivpd {{.*}}(%rip), %ymm0, %ymm0
; HAS-FMA-NEXT: retq
[FPEnv] Support constrained FREM intrinsic Differential Revision: https://reviews.llvm.org/D50975 llvm-svn: 340201
2018-08-21 03:28:56 +08:00
entry:
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
%div = call <4 x double> @llvm.experimental.constrained.fdiv.v4f64(
<4 x double> <double 1.000000e+00, double 2.000000e+00,
double 3.000000e+00, double 4.000000e+00>,
<4 x double> <double 1.000000e+01, double 1.000000e+01,
double 1.000000e+01, double 1.000000e+01>,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <4 x double> %div
}
[FPEnv] Support constrained FREM intrinsic Differential Revision: https://reviews.llvm.org/D50975 llvm-svn: 340201
2018-08-21 03:28:56 +08:00
define <1 x float> @constrained_vector_frem_v1f32() {
; NO-FMA-LABEL: constrained_vector_frem_v1f32:
; NO-FMA: # %bb.0: # %entry
; NO-FMA-NEXT: pushq %rax
; NO-FMA-NEXT: .cfi_def_cfa_offset 16
; NO-FMA-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; NO-FMA-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; NO-FMA-NEXT: callq fmodf
; NO-FMA-NEXT: popq %rax
; NO-FMA-NEXT: .cfi_def_cfa_offset 8
; NO-FMA-NEXT: retq
;
; HAS-FMA-LABEL: constrained_vector_frem_v1f32:
; HAS-FMA: # %bb.0: # %entry
; HAS-FMA-NEXT: pushq %rax
; HAS-FMA-NEXT: .cfi_def_cfa_offset 16
; HAS-FMA-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; HAS-FMA-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; HAS-FMA-NEXT: callq fmodf
; HAS-FMA-NEXT: popq %rax
; HAS-FMA-NEXT: .cfi_def_cfa_offset 8
; HAS-FMA-NEXT: retq
entry:
%rem = call <1 x float> @llvm.experimental.constrained.frem.v1f32(
<1 x float> <float 1.000000e+00>,
<1 x float> <float 1.000000e+01>,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <1 x float> %rem
}
define <2 x double> @constrained_vector_frem_v2f64() {
; NO-FMA-LABEL: constrained_vector_frem_v2f64:
; NO-FMA: # %bb.0: # %entry
; NO-FMA-NEXT: subq $24, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 32
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
; NO-FMA-NEXT: callq fmod
; NO-FMA-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
; NO-FMA-NEXT: callq fmod
; NO-FMA-NEXT: unpcklpd (%rsp), %xmm0 # 16-byte Folded Reload
; NO-FMA-NEXT: # xmm0 = xmm0[0],mem[0]
; NO-FMA-NEXT: addq $24, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 8
; NO-FMA-NEXT: retq
;
; HAS-FMA-LABEL: constrained_vector_frem_v2f64:
; HAS-FMA: # %bb.0: # %entry
; HAS-FMA-NEXT: subq $24, %rsp
; HAS-FMA-NEXT: .cfi_def_cfa_offset 32
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero
; HAS-FMA-NEXT: callq fmod
; HAS-FMA-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero
; HAS-FMA-NEXT: callq fmod
; HAS-FMA-NEXT: vunpcklpd (%rsp), %xmm0, %xmm0 # 16-byte Folded Reload
; HAS-FMA-NEXT: # xmm0 = xmm0[0],mem[0]
; HAS-FMA-NEXT: addq $24, %rsp
; HAS-FMA-NEXT: .cfi_def_cfa_offset 8
; HAS-FMA-NEXT: retq
entry:
%rem = call <2 x double> @llvm.experimental.constrained.frem.v2f64(
<2 x double> <double 1.000000e+00, double 2.000000e+00>,
<2 x double> <double 1.000000e+01, double 1.000000e+01>,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <2 x double> %rem
}
define <3 x float> @constrained_vector_frem_v3f32() {
; NO-FMA-LABEL: constrained_vector_frem_v3f32:
; NO-FMA: # %bb.0: # %entry
; NO-FMA-NEXT: subq $40, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 48
; NO-FMA-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; NO-FMA-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; NO-FMA-NEXT: callq fmodf
; NO-FMA-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; NO-FMA-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; NO-FMA-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; NO-FMA-NEXT: callq fmodf
; NO-FMA-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; NO-FMA-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; NO-FMA-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; NO-FMA-NEXT: callq fmodf
; NO-FMA-NEXT: movaps (%rsp), %xmm1 # 16-byte Reload
; NO-FMA-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; NO-FMA-NEXT: unpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload
; NO-FMA-NEXT: # xmm1 = xmm1[0],mem[0]
; NO-FMA-NEXT: movaps %xmm1, %xmm0
; NO-FMA-NEXT: addq $40, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 8
; NO-FMA-NEXT: retq
;
; HAS-FMA-LABEL: constrained_vector_frem_v3f32:
; HAS-FMA: # %bb.0: # %entry
; HAS-FMA-NEXT: subq $40, %rsp
; HAS-FMA-NEXT: .cfi_def_cfa_offset 48
; HAS-FMA-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; HAS-FMA-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; HAS-FMA-NEXT: callq fmodf
; HAS-FMA-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; HAS-FMA-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; HAS-FMA-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; HAS-FMA-NEXT: callq fmodf
; HAS-FMA-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
; HAS-FMA-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; HAS-FMA-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; HAS-FMA-NEXT: callq fmodf
; HAS-FMA-NEXT: vmovaps (%rsp), %xmm1 # 16-byte Reload
; HAS-FMA-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[2,3]
; HAS-FMA-NEXT: vinsertps $32, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm0 # 16-byte Folded Reload
; HAS-FMA-NEXT: # xmm0 = xmm0[0,1],mem[0],xmm0[3]
; HAS-FMA-NEXT: addq $40, %rsp
; HAS-FMA-NEXT: .cfi_def_cfa_offset 8
; HAS-FMA-NEXT: retq
entry:
%rem = call <3 x float> @llvm.experimental.constrained.frem.v3f32(
<3 x float> <float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>,
<3 x float> <float 1.000000e+01, float 1.000000e+01, float 1.000000e+01>,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <3 x float> %rem
}
define <3 x double> @constrained_vector_frem_v3f64() {
; NO-FMA-LABEL: constrained_vector_frem_v3f64:
; NO-FMA: # %bb.0: # %entry
[X86] Add initial SimplifyDemandedVectorEltsForTargetNode support This patch adds an initial x86 SimplifyDemandedVectorEltsForTargetNode implementation to handle target shuffles. Currently the patch only decodes a target shuffle, calls SimplifyDemandedVectorElts on its input operands and removes any shuffle that reduces to undef/zero/identity. Future work will need to integrate this with combineX86ShufflesRecursively, add support for other x86 ops, etc. NOTE: There is a minor regression that appears to be affecting further (extractelement?) combines which I haven't been able to solve yet - possibly something to do with how nodes are added to the worklist after simplification. Differential Revision: https://reviews.llvm.org/D52140 llvm-svn: 342564
2018-09-20 02:11:34 +08:00
; NO-FMA-NEXT: subq $24, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 32
[FPEnv] Support constrained FREM intrinsic Differential Revision: https://reviews.llvm.org/D50975 llvm-svn: 340201
2018-08-21 03:28:56 +08:00
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
; NO-FMA-NEXT: callq fmod
[X86] Add initial SimplifyDemandedVectorEltsForTargetNode support This patch adds an initial x86 SimplifyDemandedVectorEltsForTargetNode implementation to handle target shuffles. Currently the patch only decodes a target shuffle, calls SimplifyDemandedVectorElts on its input operands and removes any shuffle that reduces to undef/zero/identity. Future work will need to integrate this with combineX86ShufflesRecursively, add support for other x86 ops, etc. NOTE: There is a minor regression that appears to be affecting further (extractelement?) combines which I haven't been able to solve yet - possibly something to do with how nodes are added to the worklist after simplification. Differential Revision: https://reviews.llvm.org/D52140 llvm-svn: 342564
2018-09-20 02:11:34 +08:00
; NO-FMA-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
[FPEnv] Support constrained FREM intrinsic Differential Revision: https://reviews.llvm.org/D50975 llvm-svn: 340201
2018-08-21 03:28:56 +08:00
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
; NO-FMA-NEXT: callq fmod
[X86] Add initial SimplifyDemandedVectorEltsForTargetNode support This patch adds an initial x86 SimplifyDemandedVectorEltsForTargetNode implementation to handle target shuffles. Currently the patch only decodes a target shuffle, calls SimplifyDemandedVectorElts on its input operands and removes any shuffle that reduces to undef/zero/identity. Future work will need to integrate this with combineX86ShufflesRecursively, add support for other x86 ops, etc. NOTE: There is a minor regression that appears to be affecting further (extractelement?) combines which I haven't been able to solve yet - possibly something to do with how nodes are added to the worklist after simplification. Differential Revision: https://reviews.llvm.org/D52140 llvm-svn: 342564
2018-09-20 02:11:34 +08:00
; NO-FMA-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill
[FPEnv] Support constrained FREM intrinsic Differential Revision: https://reviews.llvm.org/D50975 llvm-svn: 340201
2018-08-21 03:28:56 +08:00
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
; NO-FMA-NEXT: callq fmod
; NO-FMA-NEXT: movsd %xmm0, {{[0-9]+}}(%rsp)
; NO-FMA-NEXT: fldl {{[0-9]+}}(%rsp)
[X86] Add initial SimplifyDemandedVectorEltsForTargetNode support This patch adds an initial x86 SimplifyDemandedVectorEltsForTargetNode implementation to handle target shuffles. Currently the patch only decodes a target shuffle, calls SimplifyDemandedVectorElts on its input operands and removes any shuffle that reduces to undef/zero/identity. Future work will need to integrate this with combineX86ShufflesRecursively, add support for other x86 ops, etc. NOTE: There is a minor regression that appears to be affecting further (extractelement?) combines which I haven't been able to solve yet - possibly something to do with how nodes are added to the worklist after simplification. Differential Revision: https://reviews.llvm.org/D52140 llvm-svn: 342564
2018-09-20 02:11:34 +08:00
; NO-FMA-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload
; NO-FMA-NEXT: # xmm0 = mem[0],zero
; NO-FMA-NEXT: movsd (%rsp), %xmm1 # 8-byte Reload
; NO-FMA-NEXT: # xmm1 = mem[0],zero
; NO-FMA-NEXT: addq $24, %rsp
[FPEnv] Support constrained FREM intrinsic Differential Revision: https://reviews.llvm.org/D50975 llvm-svn: 340201
2018-08-21 03:28:56 +08:00
; NO-FMA-NEXT: .cfi_def_cfa_offset 8
; NO-FMA-NEXT: retq
;
; HAS-FMA-LABEL: constrained_vector_frem_v3f64:
; HAS-FMA: # %bb.0: # %entry
; HAS-FMA-NEXT: subq $56, %rsp
; HAS-FMA-NEXT: .cfi_def_cfa_offset 64
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero
; HAS-FMA-NEXT: callq fmod
; HAS-FMA-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero
; HAS-FMA-NEXT: callq fmod
; HAS-FMA-NEXT: vunpcklpd (%rsp), %xmm0, %xmm0 # 16-byte Folded Reload
; HAS-FMA-NEXT: # xmm0 = xmm0[0],mem[0]
; HAS-FMA-NEXT: vmovups %ymm0, (%rsp) # 32-byte Spill
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero
; HAS-FMA-NEXT: vzeroupper
; HAS-FMA-NEXT: callq fmod
; HAS-FMA-NEXT: vmovups (%rsp), %ymm1 # 32-byte Reload
; HAS-FMA-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; HAS-FMA-NEXT: addq $56, %rsp
; HAS-FMA-NEXT: .cfi_def_cfa_offset 8
; HAS-FMA-NEXT: retq
entry:
%rem = call <3 x double> @llvm.experimental.constrained.frem.v3f64(
<3 x double> <double 1.000000e+00, double 2.000000e+00, double 3.000000e+00>,
<3 x double> <double 1.000000e+01, double 1.000000e+01, double 1.000000e+01>,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <3 x double> %rem
}
define <4 x double> @constrained_vector_frem_v4f64() {
; NO-FMA-LABEL: constrained_vector_frem_v4f64:
; NO-FMA: # %bb.0:
; NO-FMA-NEXT: subq $40, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 48
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
; NO-FMA-NEXT: callq fmod
; NO-FMA-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
; NO-FMA-NEXT: callq fmod
; NO-FMA-NEXT: unpcklpd (%rsp), %xmm0 # 16-byte Folded Reload
; NO-FMA-NEXT: # xmm0 = xmm0[0],mem[0]
; NO-FMA-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
; NO-FMA-NEXT: callq fmod
; NO-FMA-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
; NO-FMA-NEXT: callq fmod
; NO-FMA-NEXT: movaps %xmm0, %xmm1
; NO-FMA-NEXT: unpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload
; NO-FMA-NEXT: # xmm1 = xmm1[0],mem[0]
; NO-FMA-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; NO-FMA-NEXT: addq $40, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 8
; NO-FMA-NEXT: retq
;
; HAS-FMA-LABEL: constrained_vector_frem_v4f64:
; HAS-FMA: # %bb.0:
; HAS-FMA-NEXT: subq $40, %rsp
; HAS-FMA-NEXT: .cfi_def_cfa_offset 48
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero
; HAS-FMA-NEXT: callq fmod
; HAS-FMA-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero
; HAS-FMA-NEXT: callq fmod
; HAS-FMA-NEXT: vunpcklpd (%rsp), %xmm0, %xmm0 # 16-byte Folded Reload
; HAS-FMA-NEXT: # xmm0 = xmm0[0],mem[0]
; HAS-FMA-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero
; HAS-FMA-NEXT: callq fmod
; HAS-FMA-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero
; HAS-FMA-NEXT: callq fmod
; HAS-FMA-NEXT: vunpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm0 # 16-byte Folded Reload
; HAS-FMA-NEXT: # xmm0 = xmm0[0],mem[0]
; HAS-FMA-NEXT: vinsertf128 $1, (%rsp), %ymm0, %ymm0 # 16-byte Folded Reload
; HAS-FMA-NEXT: addq $40, %rsp
; HAS-FMA-NEXT: .cfi_def_cfa_offset 8
; HAS-FMA-NEXT: retq
%rem = call <4 x double> @llvm.experimental.constrained.frem.v4f64(
<4 x double> <double 1.000000e+00, double 2.000000e+00,
double 3.000000e+00, double 4.000000e+00>,
<4 x double> <double 1.000000e+01, double 1.000000e+01,
double 1.000000e+01, double 1.000000e+01>,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <4 x double> %rem
}
[FPEnv] Scalarize StrictFP vector operations Add a helper function to scalarize constrained FP operations as needed. Differential Revision: https://reviews.llvm.org/D50720 llvm-svn: 339735
2018-08-15 06:13:11 +08:00
define <1 x float> @constrained_vector_fmul_v1f32() {
; NO-FMA-LABEL: constrained_vector_fmul_v1f32:
; NO-FMA: # %bb.0: # %entry
; NO-FMA-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; NO-FMA-NEXT: mulss {{.*}}(%rip), %xmm0
; NO-FMA-NEXT: retq
;
; HAS-FMA-LABEL: constrained_vector_fmul_v1f32:
; HAS-FMA: # %bb.0: # %entry
; HAS-FMA-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; HAS-FMA-NEXT: vmulss {{.*}}(%rip), %xmm0, %xmm0
; HAS-FMA-NEXT: retq
entry:
%mul = call <1 x float> @llvm.experimental.constrained.fmul.v1f32(
<1 x float> <float 0x7FF0000000000000>,
<1 x float> <float 2.000000e+00>,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <1 x float> %mul
}
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
define <2 x double> @constrained_vector_fmul_v2f64() {
; NO-FMA-LABEL: constrained_vector_fmul_v2f64:
[FPEnv] Expand constrained FP POWI Modify ExpandStrictFPOp(...) to handle nodes that have scalar operands. Also, add a Strict FMA test and do some other light cleanup in the Strict FP code. Differential Revision: https://reviews.llvm.org/D48149 llvm-svn: 334863
2018-06-16 04:57:55 +08:00
; NO-FMA: # %bb.0: # %entry
[X86] Standardize floating point assembly comments Consistently try to use APFloat::toString for floating point constant comments to get rid of differences between Constant / ConstantDataSequential values - it should help stop some of the linux-windows buildbot failures matching NaN/INF etc. as well. Differential Revision: https://reviews.llvm.org/D52702 llvm-svn: 343562
2018-10-02 17:08:51 +08:00
; NO-FMA-NEXT: movapd {{.*#+}} xmm0 = [1.7976931348623157E+308,1.7976931348623157E+308]
[FPEnv] Expand constrained FP POWI Modify ExpandStrictFPOp(...) to handle nodes that have scalar operands. Also, add a Strict FMA test and do some other light cleanup in the Strict FP code. Differential Revision: https://reviews.llvm.org/D48149 llvm-svn: 334863
2018-06-16 04:57:55 +08:00
; NO-FMA-NEXT: mulpd {{.*}}(%rip), %xmm0
; NO-FMA-NEXT: retq
;
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
; HAS-FMA-LABEL: constrained_vector_fmul_v2f64:
[FPEnv] Expand constrained FP POWI Modify ExpandStrictFPOp(...) to handle nodes that have scalar operands. Also, add a Strict FMA test and do some other light cleanup in the Strict FP code. Differential Revision: https://reviews.llvm.org/D48149 llvm-svn: 334863
2018-06-16 04:57:55 +08:00
; HAS-FMA: # %bb.0: # %entry
[X86] Standardize floating point assembly comments Consistently try to use APFloat::toString for floating point constant comments to get rid of differences between Constant / ConstantDataSequential values - it should help stop some of the linux-windows buildbot failures matching NaN/INF etc. as well. Differential Revision: https://reviews.llvm.org/D52702 llvm-svn: 343562
2018-10-02 17:08:51 +08:00
; HAS-FMA-NEXT: vmovapd {{.*#+}} xmm0 = [1.7976931348623157E+308,1.7976931348623157E+308]
[FPEnv] Expand constrained FP POWI Modify ExpandStrictFPOp(...) to handle nodes that have scalar operands. Also, add a Strict FMA test and do some other light cleanup in the Strict FP code. Differential Revision: https://reviews.llvm.org/D48149 llvm-svn: 334863
2018-06-16 04:57:55 +08:00
; HAS-FMA-NEXT: vmulpd {{.*}}(%rip), %xmm0, %xmm0
; HAS-FMA-NEXT: retq
[FPEnv] Expand constrained FP operations Add a helper function to expand constrained FP operations as needed. Note that the Strict POWI operation is not handled in this patch since the format is slightly different from the others. Differential Revision: https://reviews.llvm.org/D47491 llvm-svn: 334603
2018-06-13 22:32:12 +08:00
entry:
%mul = call <2 x double> @llvm.experimental.constrained.fmul.v2f64(
<2 x double> <double 0x7FEFFFFFFFFFFFFF, double 0x7FEFFFFFFFFFFFFF>,
<2 x double> <double 2.000000e+00, double 3.000000e+00>,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <2 x double> %mul
}
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
define <3 x float> @constrained_vector_fmul_v3f32() {
; NO-FMA-LABEL: constrained_vector_fmul_v3f32:
; NO-FMA: # %bb.0: # %entry
; NO-FMA-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; NO-FMA-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; NO-FMA-NEXT: mulss %xmm1, %xmm2
; NO-FMA-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; NO-FMA-NEXT: mulss %xmm1, %xmm0
; NO-FMA-NEXT: mulss {{.*}}(%rip), %xmm1
; NO-FMA-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; NO-FMA-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0]
; NO-FMA-NEXT: retq
;
; HAS-FMA-LABEL: constrained_vector_fmul_v3f32:
; HAS-FMA: # %bb.0: # %entry
; HAS-FMA-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; HAS-FMA-NEXT: vmulss {{.*}}(%rip), %xmm0, %xmm1
; HAS-FMA-NEXT: vmulss {{.*}}(%rip), %xmm0, %xmm2
; HAS-FMA-NEXT: vmulss {{.*}}(%rip), %xmm0, %xmm0
; HAS-FMA-NEXT: vinsertps {{.*#+}} xmm0 = xmm2[0],xmm0[0],xmm2[2,3]
; HAS-FMA-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0],xmm0[3]
; HAS-FMA-NEXT: retq
entry:
%mul = call <3 x float> @llvm.experimental.constrained.fmul.v3f32(
<3 x float> <float 0x7FF0000000000000, float 0x7FF0000000000000,
float 0x7FF0000000000000>,
<3 x float> <float 1.000000e+00, float 1.000000e+01, float 1.000000e+02>,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <3 x float> %mul
}
define <3 x double> @constrained_vector_fmul_v3f64() {
; NO-FMA-LABEL: constrained_vector_fmul_v3f64:
; NO-FMA: # %bb.0: # %entry
[X86] Standardize floating point assembly comments Consistently try to use APFloat::toString for floating point constant comments to get rid of differences between Constant / ConstantDataSequential values - it should help stop some of the linux-windows buildbot failures matching NaN/INF etc. as well. Differential Revision: https://reviews.llvm.org/D52702 llvm-svn: 343562
2018-10-02 17:08:51 +08:00
; NO-FMA-NEXT: movapd {{.*#+}} xmm0 = [1.7976931348623157E+308,1.7976931348623157E+308]
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
; NO-FMA-NEXT: mulpd {{.*}}(%rip), %xmm0
; NO-FMA-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
; NO-FMA-NEXT: mulsd {{.*}}(%rip), %xmm1
; NO-FMA-NEXT: movsd %xmm1, -{{[0-9]+}}(%rsp)
; NO-FMA-NEXT: movapd %xmm0, %xmm1
[X86] Prefer unpckhpd over movhlps in isel for fake unary cases In r337348, I changed lowering to prefer X86ISD::UNPCKL/UNPCKH opcodes over MOVLHPS/MOVHLPS for v2f64 {0,0} and {1,1} shuffles when we have SSE2. This enabled the removal of a bunch of weirdly bitcasted isel patterns in r337349. To avoid changing the tests I placed a gross hack in isel to still emit movhlps instructions for fake unary unpckh nodes. A similar hack was not needed for unpckl and movlhps because we do execution domain switching for those. But unpckh and movhlps have swapped operand order. This patch removes the hack. This is a code size increase since unpckhpd requires a 0x66 prefix and movhlps does not. But if that's a big concern we should be using movhlps for all unpckhpd opcodes and let commuteInstruction turnit into unpckhpd when its an advantage. Differential Revision: https://reviews.llvm.org/D49499 llvm-svn: 341973
2018-09-12 01:57:27 +08:00
; NO-FMA-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
; NO-FMA-NEXT: fldl -{{[0-9]+}}(%rsp)
; NO-FMA-NEXT: retq
;
; HAS-FMA-LABEL: constrained_vector_fmul_v3f64:
; HAS-FMA: # %bb.0: # %entry
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: vmulsd {{.*}}(%rip), %xmm0, %xmm0
[X86] Standardize floating point assembly comments Consistently try to use APFloat::toString for floating point constant comments to get rid of differences between Constant / ConstantDataSequential values - it should help stop some of the linux-windows buildbot failures matching NaN/INF etc. as well. Differential Revision: https://reviews.llvm.org/D52702 llvm-svn: 343562
2018-10-02 17:08:51 +08:00
; HAS-FMA-NEXT: vmovapd {{.*#+}} xmm1 = [1.7976931348623157E+308,1.7976931348623157E+308]
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
; HAS-FMA-NEXT: vmulpd {{.*}}(%rip), %xmm1, %xmm1
; HAS-FMA-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; HAS-FMA-NEXT: retq
entry:
%mul = call <3 x double> @llvm.experimental.constrained.fmul.v3f64(
<3 x double> <double 0x7FEFFFFFFFFFFFFF, double 0x7FEFFFFFFFFFFFFF,
double 0x7FEFFFFFFFFFFFFF>,
<3 x double> <double 1.000000e+00, double 1.000000e+01, double 1.000000e+02>,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <3 x double> %mul
}
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
define <4 x double> @constrained_vector_fmul_v4f64() {
; NO-FMA-LABEL: constrained_vector_fmul_v4f64:
; NO-FMA: # %bb.0: # %entry
[X86] Standardize floating point assembly comments Consistently try to use APFloat::toString for floating point constant comments to get rid of differences between Constant / ConstantDataSequential values - it should help stop some of the linux-windows buildbot failures matching NaN/INF etc. as well. Differential Revision: https://reviews.llvm.org/D52702 llvm-svn: 343562
2018-10-02 17:08:51 +08:00
; NO-FMA-NEXT: movapd {{.*#+}} xmm1 = [1.7976931348623157E+308,1.7976931348623157E+308]
[X86] Force floating point values in constant pool decoding to print in scientific notation so they can't be confused with integers. When the floating point constants are whole numbers they have no decimal point so look like integers, but mean something very different in something like an 'and' instruction. Ideally we would just print a decimal point and a 0, but I couldn't see how to make APFloat::toString do that. llvm-svn: 345488
2018-10-29 12:52:04 +08:00
; NO-FMA-NEXT: movapd {{.*#+}} xmm0 = [2.0E+0,3.0E+0]
Fix corruption of result number in LegalizeVectorOps.cpp When VectorLegalizer::LegalizeOp creates a new SDValue after iterating over its arguments, we need to refer to the same result number of the new node that the original value used. Reviewed by: cameron.mcinally Differential Revision: https://reviews.llvm.org/D49805 llvm-svn: 337939
2018-07-26 01:08:13 +08:00
; NO-FMA-NEXT: mulpd %xmm1, %xmm0
; NO-FMA-NEXT: mulpd {{.*}}(%rip), %xmm1
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
; NO-FMA-NEXT: retq
;
; HAS-FMA-LABEL: constrained_vector_fmul_v4f64:
; HAS-FMA: # %bb.0: # %entry
[X86] Standardize floating point assembly comments Consistently try to use APFloat::toString for floating point constant comments to get rid of differences between Constant / ConstantDataSequential values - it should help stop some of the linux-windows buildbot failures matching NaN/INF etc. as well. Differential Revision: https://reviews.llvm.org/D52702 llvm-svn: 343562
2018-10-02 17:08:51 +08:00
; HAS-FMA-NEXT: vmovapd {{.*#+}} ymm0 = [1.7976931348623157E+308,1.7976931348623157E+308,1.7976931348623157E+308,1.7976931348623157E+308]
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
; HAS-FMA-NEXT: vmulpd {{.*}}(%rip), %ymm0, %ymm0
; HAS-FMA-NEXT: retq
entry:
%mul = call <4 x double> @llvm.experimental.constrained.fmul.v4f64(
<4 x double> <double 0x7FEFFFFFFFFFFFFF, double 0x7FEFFFFFFFFFFFFF,
double 0x7FEFFFFFFFFFFFFF, double 0x7FEFFFFFFFFFFFFF>,
<4 x double> <double 2.000000e+00, double 3.000000e+00,
double 4.000000e+00, double 5.000000e+00>,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <4 x double> %mul
}
[FPEnv] Scalarize StrictFP vector operations Add a helper function to scalarize constrained FP operations as needed. Differential Revision: https://reviews.llvm.org/D50720 llvm-svn: 339735
2018-08-15 06:13:11 +08:00
define <1 x float> @constrained_vector_fadd_v1f32() {
; NO-FMA-LABEL: constrained_vector_fadd_v1f32:
; NO-FMA: # %bb.0: # %entry
; NO-FMA-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; NO-FMA-NEXT: addss {{.*}}(%rip), %xmm0
; NO-FMA-NEXT: retq
;
; HAS-FMA-LABEL: constrained_vector_fadd_v1f32:
; HAS-FMA: # %bb.0: # %entry
; HAS-FMA-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; HAS-FMA-NEXT: vaddss {{.*}}(%rip), %xmm0, %xmm0
; HAS-FMA-NEXT: retq
entry:
%add = call <1 x float> @llvm.experimental.constrained.fadd.v1f32(
<1 x float> <float 0x7FF0000000000000>,
<1 x float> <float 1.0>,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <1 x float> %add
}
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
define <2 x double> @constrained_vector_fadd_v2f64() {
; NO-FMA-LABEL: constrained_vector_fadd_v2f64:
[FPEnv] Expand constrained FP POWI Modify ExpandStrictFPOp(...) to handle nodes that have scalar operands. Also, add a Strict FMA test and do some other light cleanup in the Strict FP code. Differential Revision: https://reviews.llvm.org/D48149 llvm-svn: 334863
2018-06-16 04:57:55 +08:00
; NO-FMA: # %bb.0: # %entry
[X86] Standardize floating point assembly comments Consistently try to use APFloat::toString for floating point constant comments to get rid of differences between Constant / ConstantDataSequential values - it should help stop some of the linux-windows buildbot failures matching NaN/INF etc. as well. Differential Revision: https://reviews.llvm.org/D52702 llvm-svn: 343562
2018-10-02 17:08:51 +08:00
; NO-FMA-NEXT: movapd {{.*#+}} xmm0 = [1.7976931348623157E+308,1.7976931348623157E+308]
[FPEnv] Expand constrained FP POWI Modify ExpandStrictFPOp(...) to handle nodes that have scalar operands. Also, add a Strict FMA test and do some other light cleanup in the Strict FP code. Differential Revision: https://reviews.llvm.org/D48149 llvm-svn: 334863
2018-06-16 04:57:55 +08:00
; NO-FMA-NEXT: addpd {{.*}}(%rip), %xmm0
; NO-FMA-NEXT: retq
;
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
; HAS-FMA-LABEL: constrained_vector_fadd_v2f64:
[FPEnv] Expand constrained FP POWI Modify ExpandStrictFPOp(...) to handle nodes that have scalar operands. Also, add a Strict FMA test and do some other light cleanup in the Strict FP code. Differential Revision: https://reviews.llvm.org/D48149 llvm-svn: 334863
2018-06-16 04:57:55 +08:00
; HAS-FMA: # %bb.0: # %entry
[X86] Standardize floating point assembly comments Consistently try to use APFloat::toString for floating point constant comments to get rid of differences between Constant / ConstantDataSequential values - it should help stop some of the linux-windows buildbot failures matching NaN/INF etc. as well. Differential Revision: https://reviews.llvm.org/D52702 llvm-svn: 343562
2018-10-02 17:08:51 +08:00
; HAS-FMA-NEXT: vmovapd {{.*#+}} xmm0 = [1.7976931348623157E+308,1.7976931348623157E+308]
[FPEnv] Expand constrained FP POWI Modify ExpandStrictFPOp(...) to handle nodes that have scalar operands. Also, add a Strict FMA test and do some other light cleanup in the Strict FP code. Differential Revision: https://reviews.llvm.org/D48149 llvm-svn: 334863
2018-06-16 04:57:55 +08:00
; HAS-FMA-NEXT: vaddpd {{.*}}(%rip), %xmm0, %xmm0
; HAS-FMA-NEXT: retq
[FPEnv] Expand constrained FP operations Add a helper function to expand constrained FP operations as needed. Note that the Strict POWI operation is not handled in this patch since the format is slightly different from the others. Differential Revision: https://reviews.llvm.org/D47491 llvm-svn: 334603
2018-06-13 22:32:12 +08:00
entry:
%add = call <2 x double> @llvm.experimental.constrained.fadd.v2f64(
<2 x double> <double 0x7FEFFFFFFFFFFFFF, double 0x7FEFFFFFFFFFFFFF>,
<2 x double> <double 1.000000e+00, double 1.000000e-01>,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <2 x double> %add
}
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
define <3 x float> @constrained_vector_fadd_v3f32() {
; NO-FMA-LABEL: constrained_vector_fadd_v3f32:
; NO-FMA: # %bb.0: # %entry
; NO-FMA-NEXT: xorps %xmm1, %xmm1
; NO-FMA-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; NO-FMA-NEXT: addss %xmm2, %xmm1
; NO-FMA-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; NO-FMA-NEXT: addss %xmm2, %xmm0
; NO-FMA-NEXT: addss {{.*}}(%rip), %xmm2
; NO-FMA-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
; NO-FMA-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; NO-FMA-NEXT: retq
;
; HAS-FMA-LABEL: constrained_vector_fadd_v3f32:
; HAS-FMA: # %bb.0: # %entry
; HAS-FMA-NEXT: vxorps %xmm0, %xmm0, %xmm0
; HAS-FMA-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; HAS-FMA-NEXT: vaddss %xmm0, %xmm1, %xmm0
; HAS-FMA-NEXT: vaddss {{.*}}(%rip), %xmm1, %xmm2
; HAS-FMA-NEXT: vaddss {{.*}}(%rip), %xmm1, %xmm1
; HAS-FMA-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[2,3]
; HAS-FMA-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1],xmm0[0],xmm1[3]
; HAS-FMA-NEXT: retq
entry:
%add = call <3 x float> @llvm.experimental.constrained.fadd.v3f32(
<3 x float> <float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000,
float 0xFFFFFFFFE0000000>,
<3 x float> <float 2.0, float 1.0, float 0.0>,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <3 x float> %add
}
define <3 x double> @constrained_vector_fadd_v3f64() {
; NO-FMA-LABEL: constrained_vector_fadd_v3f64:
; NO-FMA: # %bb.0: # %entry
[X86] Standardize floating point assembly comments Consistently try to use APFloat::toString for floating point constant comments to get rid of differences between Constant / ConstantDataSequential values - it should help stop some of the linux-windows buildbot failures matching NaN/INF etc. as well. Differential Revision: https://reviews.llvm.org/D52702 llvm-svn: 343562
2018-10-02 17:08:51 +08:00
; NO-FMA-NEXT: movapd {{.*#+}} xmm0 = [1.7976931348623157E+308,1.7976931348623157E+308]
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
; NO-FMA-NEXT: addpd {{.*}}(%rip), %xmm0
; NO-FMA-NEXT: xorpd %xmm1, %xmm1
; NO-FMA-NEXT: addsd {{.*}}(%rip), %xmm1
; NO-FMA-NEXT: movsd %xmm1, -{{[0-9]+}}(%rsp)
; NO-FMA-NEXT: movapd %xmm0, %xmm1
[X86] Prefer unpckhpd over movhlps in isel for fake unary cases In r337348, I changed lowering to prefer X86ISD::UNPCKL/UNPCKH opcodes over MOVLHPS/MOVHLPS for v2f64 {0,0} and {1,1} shuffles when we have SSE2. This enabled the removal of a bunch of weirdly bitcasted isel patterns in r337349. To avoid changing the tests I placed a gross hack in isel to still emit movhlps instructions for fake unary unpckh nodes. A similar hack was not needed for unpckl and movlhps because we do execution domain switching for those. But unpckh and movhlps have swapped operand order. This patch removes the hack. This is a code size increase since unpckhpd requires a 0x66 prefix and movhlps does not. But if that's a big concern we should be using movhlps for all unpckhpd opcodes and let commuteInstruction turnit into unpckhpd when its an advantage. Differential Revision: https://reviews.llvm.org/D49499 llvm-svn: 341973
2018-09-12 01:57:27 +08:00
; NO-FMA-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
; NO-FMA-NEXT: fldl -{{[0-9]+}}(%rsp)
; NO-FMA-NEXT: retq
;
; HAS-FMA-LABEL: constrained_vector_fadd_v3f64:
; HAS-FMA: # %bb.0: # %entry
; HAS-FMA-NEXT: vxorpd %xmm0, %xmm0, %xmm0
; HAS-FMA-NEXT: vaddsd {{.*}}(%rip), %xmm0, %xmm0
[X86] Standardize floating point assembly comments Consistently try to use APFloat::toString for floating point constant comments to get rid of differences between Constant / ConstantDataSequential values - it should help stop some of the linux-windows buildbot failures matching NaN/INF etc. as well. Differential Revision: https://reviews.llvm.org/D52702 llvm-svn: 343562
2018-10-02 17:08:51 +08:00
; HAS-FMA-NEXT: vmovapd {{.*#+}} xmm1 = [1.7976931348623157E+308,1.7976931348623157E+308]
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
; HAS-FMA-NEXT: vaddpd {{.*}}(%rip), %xmm1, %xmm1
; HAS-FMA-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; HAS-FMA-NEXT: retq
entry:
%add = call <3 x double> @llvm.experimental.constrained.fadd.v3f64(
<3 x double> <double 0x7FEFFFFFFFFFFFFF, double 0x7FEFFFFFFFFFFFFF,
double 0x7FEFFFFFFFFFFFFF>,
<3 x double> <double 2.0, double 1.0, double 0.0>,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <3 x double> %add
}
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
define <4 x double> @constrained_vector_fadd_v4f64() {
; NO-FMA-LABEL: constrained_vector_fadd_v4f64:
; NO-FMA: # %bb.0: # %entry
[X86] Standardize floating point assembly comments Consistently try to use APFloat::toString for floating point constant comments to get rid of differences between Constant / ConstantDataSequential values - it should help stop some of the linux-windows buildbot failures matching NaN/INF etc. as well. Differential Revision: https://reviews.llvm.org/D52702 llvm-svn: 343562
2018-10-02 17:08:51 +08:00
; NO-FMA-NEXT: movapd {{.*#+}} xmm1 = [1.7976931348623157E+308,1.7976931348623157E+308]
[X86] Force floating point values in constant pool decoding to print in scientific notation so they can't be confused with integers. When the floating point constants are whole numbers they have no decimal point so look like integers, but mean something very different in something like an 'and' instruction. Ideally we would just print a decimal point and a 0, but I couldn't see how to make APFloat::toString do that. llvm-svn: 345488
2018-10-29 12:52:04 +08:00
; NO-FMA-NEXT: movapd {{.*#+}} xmm0 = [1.0E+0,1.0000000000000001E-1]
Fix corruption of result number in LegalizeVectorOps.cpp When VectorLegalizer::LegalizeOp creates a new SDValue after iterating over its arguments, we need to refer to the same result number of the new node that the original value used. Reviewed by: cameron.mcinally Differential Revision: https://reviews.llvm.org/D49805 llvm-svn: 337939
2018-07-26 01:08:13 +08:00
; NO-FMA-NEXT: addpd %xmm1, %xmm0
; NO-FMA-NEXT: addpd {{.*}}(%rip), %xmm1
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
; NO-FMA-NEXT: retq
;
; HAS-FMA-LABEL: constrained_vector_fadd_v4f64:
; HAS-FMA: # %bb.0: # %entry
[X86] Standardize floating point assembly comments Consistently try to use APFloat::toString for floating point constant comments to get rid of differences between Constant / ConstantDataSequential values - it should help stop some of the linux-windows buildbot failures matching NaN/INF etc. as well. Differential Revision: https://reviews.llvm.org/D52702 llvm-svn: 343562
2018-10-02 17:08:51 +08:00
; HAS-FMA-NEXT: vmovapd {{.*#+}} ymm0 = [1.7976931348623157E+308,1.7976931348623157E+308,1.7976931348623157E+308,1.7976931348623157E+308]
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
; HAS-FMA-NEXT: vaddpd {{.*}}(%rip), %ymm0, %ymm0
; HAS-FMA-NEXT: retq
entry:
%add = call <4 x double> @llvm.experimental.constrained.fadd.v4f64(
<4 x double> <double 0x7FEFFFFFFFFFFFFF, double 0x7FEFFFFFFFFFFFFF,
double 0x7FEFFFFFFFFFFFFF, double 0x7FEFFFFFFFFFFFFF>,
<4 x double> <double 1.000000e+00, double 1.000000e-01,
double 2.000000e+00, double 2.000000e-01>,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <4 x double> %add
}
[FPEnv] Scalarize StrictFP vector operations Add a helper function to scalarize constrained FP operations as needed. Differential Revision: https://reviews.llvm.org/D50720 llvm-svn: 339735
2018-08-15 06:13:11 +08:00
define <1 x float> @constrained_vector_fsub_v1f32() {
; NO-FMA-LABEL: constrained_vector_fsub_v1f32:
; NO-FMA: # %bb.0: # %entry
; NO-FMA-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; NO-FMA-NEXT: subss {{.*}}(%rip), %xmm0
; NO-FMA-NEXT: retq
;
; HAS-FMA-LABEL: constrained_vector_fsub_v1f32:
; HAS-FMA: # %bb.0: # %entry
; HAS-FMA-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; HAS-FMA-NEXT: vsubss {{.*}}(%rip), %xmm0, %xmm0
; HAS-FMA-NEXT: retq
entry:
%sub = call <1 x float> @llvm.experimental.constrained.fsub.v1f32(
<1 x float> <float 0x7FF0000000000000>,
<1 x float> <float 1.000000e+00>,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <1 x float> %sub
}
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
define <2 x double> @constrained_vector_fsub_v2f64() {
; NO-FMA-LABEL: constrained_vector_fsub_v2f64:
[FPEnv] Expand constrained FP POWI Modify ExpandStrictFPOp(...) to handle nodes that have scalar operands. Also, add a Strict FMA test and do some other light cleanup in the Strict FP code. Differential Revision: https://reviews.llvm.org/D48149 llvm-svn: 334863
2018-06-16 04:57:55 +08:00
; NO-FMA: # %bb.0: # %entry
[X86] Standardize floating point assembly comments Consistently try to use APFloat::toString for floating point constant comments to get rid of differences between Constant / ConstantDataSequential values - it should help stop some of the linux-windows buildbot failures matching NaN/INF etc. as well. Differential Revision: https://reviews.llvm.org/D52702 llvm-svn: 343562
2018-10-02 17:08:51 +08:00
; NO-FMA-NEXT: movapd {{.*#+}} xmm0 = [-1.7976931348623157E+308,-1.7976931348623157E+308]
[FPEnv] Expand constrained FP POWI Modify ExpandStrictFPOp(...) to handle nodes that have scalar operands. Also, add a Strict FMA test and do some other light cleanup in the Strict FP code. Differential Revision: https://reviews.llvm.org/D48149 llvm-svn: 334863
2018-06-16 04:57:55 +08:00
; NO-FMA-NEXT: subpd {{.*}}(%rip), %xmm0
; NO-FMA-NEXT: retq
;
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
; HAS-FMA-LABEL: constrained_vector_fsub_v2f64:
[FPEnv] Expand constrained FP POWI Modify ExpandStrictFPOp(...) to handle nodes that have scalar operands. Also, add a Strict FMA test and do some other light cleanup in the Strict FP code. Differential Revision: https://reviews.llvm.org/D48149 llvm-svn: 334863
2018-06-16 04:57:55 +08:00
; HAS-FMA: # %bb.0: # %entry
[X86] Standardize floating point assembly comments Consistently try to use APFloat::toString for floating point constant comments to get rid of differences between Constant / ConstantDataSequential values - it should help stop some of the linux-windows buildbot failures matching NaN/INF etc. as well. Differential Revision: https://reviews.llvm.org/D52702 llvm-svn: 343562
2018-10-02 17:08:51 +08:00
; HAS-FMA-NEXT: vmovapd {{.*#+}} xmm0 = [-1.7976931348623157E+308,-1.7976931348623157E+308]
[FPEnv] Expand constrained FP POWI Modify ExpandStrictFPOp(...) to handle nodes that have scalar operands. Also, add a Strict FMA test and do some other light cleanup in the Strict FP code. Differential Revision: https://reviews.llvm.org/D48149 llvm-svn: 334863
2018-06-16 04:57:55 +08:00
; HAS-FMA-NEXT: vsubpd {{.*}}(%rip), %xmm0, %xmm0
; HAS-FMA-NEXT: retq
[FPEnv] Expand constrained FP operations Add a helper function to expand constrained FP operations as needed. Note that the Strict POWI operation is not handled in this patch since the format is slightly different from the others. Differential Revision: https://reviews.llvm.org/D47491 llvm-svn: 334603
2018-06-13 22:32:12 +08:00
entry:
%sub = call <2 x double> @llvm.experimental.constrained.fsub.v2f64(
<2 x double> <double 0xFFEFFFFFFFFFFFFF, double 0xFFEFFFFFFFFFFFFF>,
<2 x double> <double 1.000000e+00, double 1.000000e-01>,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <2 x double> %sub
}
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
define <3 x float> @constrained_vector_fsub_v3f32() {
; NO-FMA-LABEL: constrained_vector_fsub_v3f32:
; NO-FMA: # %bb.0: # %entry
; NO-FMA-NEXT: xorps %xmm0, %xmm0
; NO-FMA-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; NO-FMA-NEXT: movaps %xmm1, %xmm2
; NO-FMA-NEXT: subss %xmm0, %xmm2
; NO-FMA-NEXT: movaps %xmm1, %xmm0
; NO-FMA-NEXT: subss {{.*}}(%rip), %xmm0
; NO-FMA-NEXT: subss {{.*}}(%rip), %xmm1
; NO-FMA-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; NO-FMA-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0]
; NO-FMA-NEXT: retq
;
; HAS-FMA-LABEL: constrained_vector_fsub_v3f32:
; HAS-FMA: # %bb.0: # %entry
; HAS-FMA-NEXT: vxorps %xmm0, %xmm0, %xmm0
; HAS-FMA-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; HAS-FMA-NEXT: vsubss %xmm0, %xmm1, %xmm0
; HAS-FMA-NEXT: vsubss {{.*}}(%rip), %xmm1, %xmm2
; HAS-FMA-NEXT: vsubss {{.*}}(%rip), %xmm1, %xmm1
; HAS-FMA-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[2,3]
; HAS-FMA-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1],xmm0[0],xmm1[3]
; HAS-FMA-NEXT: retq
entry:
%sub = call <3 x float> @llvm.experimental.constrained.fsub.v3f32(
<3 x float> <float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000,
float 0xFFFFFFFFE0000000>,
<3 x float> <float 2.0, float 1.0, float 0.0>,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <3 x float> %sub
}
define <3 x double> @constrained_vector_fsub_v3f64() {
; NO-FMA-LABEL: constrained_vector_fsub_v3f64:
; NO-FMA: # %bb.0: # %entry
; NO-FMA-NEXT: xorpd %xmm0, %xmm0
; NO-FMA-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
; NO-FMA-NEXT: subsd %xmm0, %xmm1
[X86] Standardize floating point assembly comments Consistently try to use APFloat::toString for floating point constant comments to get rid of differences between Constant / ConstantDataSequential values - it should help stop some of the linux-windows buildbot failures matching NaN/INF etc. as well. Differential Revision: https://reviews.llvm.org/D52702 llvm-svn: 343562
2018-10-02 17:08:51 +08:00
; NO-FMA-NEXT: movapd {{.*#+}} xmm0 = [-1.7976931348623157E+308,-1.7976931348623157E+308]
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
; NO-FMA-NEXT: subpd {{.*}}(%rip), %xmm0
; NO-FMA-NEXT: movsd %xmm1, -{{[0-9]+}}(%rsp)
; NO-FMA-NEXT: movapd %xmm0, %xmm1
[X86] Prefer unpckhpd over movhlps in isel for fake unary cases In r337348, I changed lowering to prefer X86ISD::UNPCKL/UNPCKH opcodes over MOVLHPS/MOVHLPS for v2f64 {0,0} and {1,1} shuffles when we have SSE2. This enabled the removal of a bunch of weirdly bitcasted isel patterns in r337349. To avoid changing the tests I placed a gross hack in isel to still emit movhlps instructions for fake unary unpckh nodes. A similar hack was not needed for unpckl and movlhps because we do execution domain switching for those. But unpckh and movhlps have swapped operand order. This patch removes the hack. This is a code size increase since unpckhpd requires a 0x66 prefix and movhlps does not. But if that's a big concern we should be using movhlps for all unpckhpd opcodes and let commuteInstruction turnit into unpckhpd when its an advantage. Differential Revision: https://reviews.llvm.org/D49499 llvm-svn: 341973
2018-09-12 01:57:27 +08:00
; NO-FMA-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
; NO-FMA-NEXT: fldl -{{[0-9]+}}(%rsp)
; NO-FMA-NEXT: retq
;
; HAS-FMA-LABEL: constrained_vector_fsub_v3f64:
; HAS-FMA: # %bb.0: # %entry
; HAS-FMA-NEXT: vxorpd %xmm0, %xmm0, %xmm0
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero
; HAS-FMA-NEXT: vsubsd %xmm0, %xmm1, %xmm0
[X86] Standardize floating point assembly comments Consistently try to use APFloat::toString for floating point constant comments to get rid of differences between Constant / ConstantDataSequential values - it should help stop some of the linux-windows buildbot failures matching NaN/INF etc. as well. Differential Revision: https://reviews.llvm.org/D52702 llvm-svn: 343562
2018-10-02 17:08:51 +08:00
; HAS-FMA-NEXT: vmovapd {{.*#+}} xmm1 = [-1.7976931348623157E+308,-1.7976931348623157E+308]
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
; HAS-FMA-NEXT: vsubpd {{.*}}(%rip), %xmm1, %xmm1
; HAS-FMA-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; HAS-FMA-NEXT: retq
entry:
%sub = call <3 x double> @llvm.experimental.constrained.fsub.v3f64(
<3 x double> <double 0xFFEFFFFFFFFFFFFF, double 0xFFEFFFFFFFFFFFFF,
double 0xFFEFFFFFFFFFFFFF>,
<3 x double> <double 2.0, double 1.0, double 0.0>,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <3 x double> %sub
}
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
define <4 x double> @constrained_vector_fsub_v4f64() {
; NO-FMA-LABEL: constrained_vector_fsub_v4f64:
; NO-FMA: # %bb.0: # %entry
[X86] Standardize floating point assembly comments Consistently try to use APFloat::toString for floating point constant comments to get rid of differences between Constant / ConstantDataSequential values - it should help stop some of the linux-windows buildbot failures matching NaN/INF etc. as well. Differential Revision: https://reviews.llvm.org/D52702 llvm-svn: 343562
2018-10-02 17:08:51 +08:00
; NO-FMA-NEXT: movapd {{.*#+}} xmm1 = [-1.7976931348623157E+308,-1.7976931348623157E+308]
Fix corruption of result number in LegalizeVectorOps.cpp When VectorLegalizer::LegalizeOp creates a new SDValue after iterating over its arguments, we need to refer to the same result number of the new node that the original value used. Reviewed by: cameron.mcinally Differential Revision: https://reviews.llvm.org/D49805 llvm-svn: 337939
2018-07-26 01:08:13 +08:00
; NO-FMA-NEXT: movapd %xmm1, %xmm0
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
; NO-FMA-NEXT: subpd {{.*}}(%rip), %xmm0
Fix corruption of result number in LegalizeVectorOps.cpp When VectorLegalizer::LegalizeOp creates a new SDValue after iterating over its arguments, we need to refer to the same result number of the new node that the original value used. Reviewed by: cameron.mcinally Differential Revision: https://reviews.llvm.org/D49805 llvm-svn: 337939
2018-07-26 01:08:13 +08:00
; NO-FMA-NEXT: subpd {{.*}}(%rip), %xmm1
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
; NO-FMA-NEXT: retq
;
; HAS-FMA-LABEL: constrained_vector_fsub_v4f64:
; HAS-FMA: # %bb.0: # %entry
[X86] Standardize floating point assembly comments Consistently try to use APFloat::toString for floating point constant comments to get rid of differences between Constant / ConstantDataSequential values - it should help stop some of the linux-windows buildbot failures matching NaN/INF etc. as well. Differential Revision: https://reviews.llvm.org/D52702 llvm-svn: 343562
2018-10-02 17:08:51 +08:00
; HAS-FMA-NEXT: vmovapd {{.*#+}} ymm0 = [-1.7976931348623157E+308,-1.7976931348623157E+308,-1.7976931348623157E+308,-1.7976931348623157E+308]
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
; HAS-FMA-NEXT: vsubpd {{.*}}(%rip), %ymm0, %ymm0
; HAS-FMA-NEXT: retq
entry:
%sub = call <4 x double> @llvm.experimental.constrained.fsub.v4f64(
<4 x double> <double 0xFFEFFFFFFFFFFFFF, double 0xFFEFFFFFFFFFFFFF,
double 0xFFEFFFFFFFFFFFFF, double 0xFFEFFFFFFFFFFFFF>,
<4 x double> <double 1.000000e+00, double 1.000000e-01,
double 2.000000e+00, double 2.000000e-01>,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <4 x double> %sub
}
[FPEnv] Scalarize StrictFP vector operations Add a helper function to scalarize constrained FP operations as needed. Differential Revision: https://reviews.llvm.org/D50720 llvm-svn: 339735
2018-08-15 06:13:11 +08:00
define <1 x float> @constrained_vector_fma_v1f32() {
; NO-FMA-LABEL: constrained_vector_fma_v1f32:
; NO-FMA: # %bb.0: # %entry
; NO-FMA-NEXT: pushq %rax
; NO-FMA-NEXT: .cfi_def_cfa_offset 16
; NO-FMA-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; NO-FMA-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; NO-FMA-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; NO-FMA-NEXT: callq fmaf
; NO-FMA-NEXT: popq %rax
; NO-FMA-NEXT: .cfi_def_cfa_offset 8
; NO-FMA-NEXT: retq
;
; HAS-FMA-LABEL: constrained_vector_fma_v1f32:
; HAS-FMA: # %bb.0: # %entry
; HAS-FMA-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; HAS-FMA-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; HAS-FMA-NEXT: vfmadd213ss {{.*#+}} xmm0 = (xmm1 * xmm0) + mem
; HAS-FMA-NEXT: retq
entry:
%fma = call <1 x float> @llvm.experimental.constrained.fma.v1f32(
<1 x float> <float 0.5>,
<1 x float> <float 2.5>,
<1 x float> <float 4.5>,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <1 x float> %fma
}
[FPEnv] Expand constrained FP POWI Modify ExpandStrictFPOp(...) to handle nodes that have scalar operands. Also, add a Strict FMA test and do some other light cleanup in the Strict FP code. Differential Revision: https://reviews.llvm.org/D48149 llvm-svn: 334863
2018-06-16 04:57:55 +08:00
define <2 x double> @constrained_vector_fma_v2f64() {
; NO-FMA-LABEL: constrained_vector_fma_v2f64:
; NO-FMA: # %bb.0: # %entry
; NO-FMA-NEXT: subq $24, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 32
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
; NO-FMA-NEXT: movsd {{.*#+}} xmm2 = mem[0],zero
; NO-FMA-NEXT: callq fma
; NO-FMA-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
; NO-FMA-NEXT: movsd {{.*#+}} xmm2 = mem[0],zero
; NO-FMA-NEXT: callq fma
; NO-FMA-NEXT: unpcklpd (%rsp), %xmm0 # 16-byte Folded Reload
; NO-FMA-NEXT: # xmm0 = xmm0[0],mem[0]
; NO-FMA-NEXT: addq $24, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 8
; NO-FMA-NEXT: retq
;
; HAS-FMA-LABEL: constrained_vector_fma_v2f64:
; HAS-FMA: # %bb.0: # %entry
[X86] Force floating point values in constant pool decoding to print in scientific notation so they can't be confused with integers. When the floating point constants are whole numbers they have no decimal point so look like integers, but mean something very different in something like an 'and' instruction. Ideally we would just print a decimal point and a 0, but I couldn't see how to make APFloat::toString do that. llvm-svn: 345488
2018-10-29 12:52:04 +08:00
; HAS-FMA-NEXT: vmovapd {{.*#+}} xmm1 = [1.5E+0,5.0E-1]
; HAS-FMA-NEXT: vmovapd {{.*#+}} xmm0 = [3.5E+0,2.5E+0]
[FPEnv] Expand constrained FP POWI Modify ExpandStrictFPOp(...) to handle nodes that have scalar operands. Also, add a Strict FMA test and do some other light cleanup in the Strict FP code. Differential Revision: https://reviews.llvm.org/D48149 llvm-svn: 334863
2018-06-16 04:57:55 +08:00
; HAS-FMA-NEXT: vfmadd213pd {{.*#+}} xmm0 = (xmm1 * xmm0) + mem
; HAS-FMA-NEXT: retq
entry:
%fma = call <2 x double> @llvm.experimental.constrained.fma.v2f64(
<2 x double> <double 1.5, double 0.5>,
<2 x double> <double 3.5, double 2.5>,
<2 x double> <double 5.5, double 4.5>,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <2 x double> %fma
}
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
define <3 x float> @constrained_vector_fma_v3f32() {
; NO-FMA-LABEL: constrained_vector_fma_v3f32:
; NO-FMA: # %bb.0: # %entry
; NO-FMA-NEXT: subq $40, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 48
; NO-FMA-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; NO-FMA-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; NO-FMA-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; NO-FMA-NEXT: callq fmaf
; NO-FMA-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; NO-FMA-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; NO-FMA-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; NO-FMA-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; NO-FMA-NEXT: callq fmaf
; NO-FMA-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; NO-FMA-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; NO-FMA-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; NO-FMA-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; NO-FMA-NEXT: callq fmaf
; NO-FMA-NEXT: movaps (%rsp), %xmm1 # 16-byte Reload
; NO-FMA-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; NO-FMA-NEXT: unpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload
; NO-FMA-NEXT: # xmm1 = xmm1[0],mem[0]
; NO-FMA-NEXT: movaps %xmm1, %xmm0
; NO-FMA-NEXT: addq $40, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 8
; NO-FMA-NEXT: retq
;
; HAS-FMA-LABEL: constrained_vector_fma_v3f32:
; HAS-FMA: # %bb.0: # %entry
; HAS-FMA-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; HAS-FMA-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; HAS-FMA-NEXT: vfmadd213ss {{.*#+}} xmm1 = (xmm0 * xmm1) + mem
; HAS-FMA-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; HAS-FMA-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; HAS-FMA-NEXT: vfmadd213ss {{.*#+}} xmm2 = (xmm0 * xmm2) + mem
; HAS-FMA-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; HAS-FMA-NEXT: vmovss {{.*#+}} xmm3 = mem[0],zero,zero,zero
; HAS-FMA-NEXT: vfmadd213ss {{.*#+}} xmm3 = (xmm0 * xmm3) + mem
; HAS-FMA-NEXT: vinsertps {{.*#+}} xmm0 = xmm2[0],xmm3[0],xmm2[2,3]
; HAS-FMA-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0],xmm0[3]
; HAS-FMA-NEXT: retq
entry:
%fma = call <3 x float> @llvm.experimental.constrained.fma.v3f32(
<3 x float> <float 2.5, float 1.5, float 0.5>,
<3 x float> <float 5.5, float 4.5, float 3.5>,
<3 x float> <float 8.5, float 7.5, float 6.5>,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <3 x float> %fma
}
define <3 x double> @constrained_vector_fma_v3f64() {
; NO-FMA-LABEL: constrained_vector_fma_v3f64:
; NO-FMA: # %bb.0: # %entry
[X86] Add initial SimplifyDemandedVectorEltsForTargetNode support This patch adds an initial x86 SimplifyDemandedVectorEltsForTargetNode implementation to handle target shuffles. Currently the patch only decodes a target shuffle, calls SimplifyDemandedVectorElts on its input operands and removes any shuffle that reduces to undef/zero/identity. Future work will need to integrate this with combineX86ShufflesRecursively, add support for other x86 ops, etc. NOTE: There is a minor regression that appears to be affecting further (extractelement?) combines which I haven't been able to solve yet - possibly something to do with how nodes are added to the worklist after simplification. Differential Revision: https://reviews.llvm.org/D52140 llvm-svn: 342564
2018-09-20 02:11:34 +08:00
; NO-FMA-NEXT: subq $24, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 32
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
; NO-FMA-NEXT: movsd {{.*#+}} xmm2 = mem[0],zero
; NO-FMA-NEXT: callq fma
[X86] Add initial SimplifyDemandedVectorEltsForTargetNode support This patch adds an initial x86 SimplifyDemandedVectorEltsForTargetNode implementation to handle target shuffles. Currently the patch only decodes a target shuffle, calls SimplifyDemandedVectorElts on its input operands and removes any shuffle that reduces to undef/zero/identity. Future work will need to integrate this with combineX86ShufflesRecursively, add support for other x86 ops, etc. NOTE: There is a minor regression that appears to be affecting further (extractelement?) combines which I haven't been able to solve yet - possibly something to do with how nodes are added to the worklist after simplification. Differential Revision: https://reviews.llvm.org/D52140 llvm-svn: 342564
2018-09-20 02:11:34 +08:00
; NO-FMA-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
; NO-FMA-NEXT: movsd {{.*#+}} xmm2 = mem[0],zero
; NO-FMA-NEXT: callq fma
[X86] Add initial SimplifyDemandedVectorEltsForTargetNode support This patch adds an initial x86 SimplifyDemandedVectorEltsForTargetNode implementation to handle target shuffles. Currently the patch only decodes a target shuffle, calls SimplifyDemandedVectorElts on its input operands and removes any shuffle that reduces to undef/zero/identity. Future work will need to integrate this with combineX86ShufflesRecursively, add support for other x86 ops, etc. NOTE: There is a minor regression that appears to be affecting further (extractelement?) combines which I haven't been able to solve yet - possibly something to do with how nodes are added to the worklist after simplification. Differential Revision: https://reviews.llvm.org/D52140 llvm-svn: 342564
2018-09-20 02:11:34 +08:00
; NO-FMA-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
; NO-FMA-NEXT: movsd {{.*#+}} xmm2 = mem[0],zero
; NO-FMA-NEXT: callq fma
; NO-FMA-NEXT: movsd %xmm0, {{[0-9]+}}(%rsp)
; NO-FMA-NEXT: fldl {{[0-9]+}}(%rsp)
[X86] Add initial SimplifyDemandedVectorEltsForTargetNode support This patch adds an initial x86 SimplifyDemandedVectorEltsForTargetNode implementation to handle target shuffles. Currently the patch only decodes a target shuffle, calls SimplifyDemandedVectorElts on its input operands and removes any shuffle that reduces to undef/zero/identity. Future work will need to integrate this with combineX86ShufflesRecursively, add support for other x86 ops, etc. NOTE: There is a minor regression that appears to be affecting further (extractelement?) combines which I haven't been able to solve yet - possibly something to do with how nodes are added to the worklist after simplification. Differential Revision: https://reviews.llvm.org/D52140 llvm-svn: 342564
2018-09-20 02:11:34 +08:00
; NO-FMA-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload
; NO-FMA-NEXT: # xmm0 = mem[0],zero
; NO-FMA-NEXT: movsd (%rsp), %xmm1 # 8-byte Reload
; NO-FMA-NEXT: # xmm1 = mem[0],zero
; NO-FMA-NEXT: addq $24, %rsp
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
; NO-FMA-NEXT: .cfi_def_cfa_offset 8
; NO-FMA-NEXT: retq
;
; HAS-FMA-LABEL: constrained_vector_fma_v3f64:
; HAS-FMA: # %bb.0: # %entry
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero
; HAS-FMA-NEXT: vfmadd213sd {{.*#+}} xmm1 = (xmm0 * xmm1) + mem
[X86] Force floating point values in constant pool decoding to print in scientific notation so they can't be confused with integers. When the floating point constants are whole numbers they have no decimal point so look like integers, but mean something very different in something like an 'and' instruction. Ideally we would just print a decimal point and a 0, but I couldn't see how to make APFloat::toString do that. llvm-svn: 345488
2018-10-29 12:52:04 +08:00
; HAS-FMA-NEXT: vmovapd {{.*#+}} xmm0 = [2.5E+0,1.5E+0]
; HAS-FMA-NEXT: vmovapd {{.*#+}} xmm2 = [5.5E+0,4.5E+0]
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
; HAS-FMA-NEXT: vfmadd213pd {{.*#+}} xmm2 = (xmm0 * xmm2) + mem
; HAS-FMA-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm0
; HAS-FMA-NEXT: retq
entry:
%fma = call <3 x double> @llvm.experimental.constrained.fma.v3f64(
<3 x double> <double 2.5, double 1.5, double 0.5>,
<3 x double> <double 5.5, double 4.5, double 3.5>,
<3 x double> <double 8.5, double 7.5, double 6.5>,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <3 x double> %fma
}
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
define <4 x double> @constrained_vector_fma_v4f64() {
; NO-FMA-LABEL: constrained_vector_fma_v4f64:
; NO-FMA: # %bb.0: # %entry
; NO-FMA-NEXT: subq $40, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 48
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
; NO-FMA-NEXT: movsd {{.*#+}} xmm2 = mem[0],zero
; NO-FMA-NEXT: callq fma
; NO-FMA-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
; NO-FMA-NEXT: movsd {{.*#+}} xmm2 = mem[0],zero
; NO-FMA-NEXT: callq fma
; NO-FMA-NEXT: unpcklpd (%rsp), %xmm0 # 16-byte Folded Reload
; NO-FMA-NEXT: # xmm0 = xmm0[0],mem[0]
; NO-FMA-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
; NO-FMA-NEXT: movsd {{.*#+}} xmm2 = mem[0],zero
; NO-FMA-NEXT: callq fma
; NO-FMA-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
; NO-FMA-NEXT: movsd {{.*#+}} xmm2 = mem[0],zero
; NO-FMA-NEXT: callq fma
; NO-FMA-NEXT: movaps %xmm0, %xmm1
; NO-FMA-NEXT: unpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload
; NO-FMA-NEXT: # xmm1 = xmm1[0],mem[0]
; NO-FMA-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; NO-FMA-NEXT: addq $40, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 8
; NO-FMA-NEXT: retq
;
; HAS-FMA-LABEL: constrained_vector_fma_v4f64:
; HAS-FMA: # %bb.0: # %entry
[X86] Force floating point values in constant pool decoding to print in scientific notation so they can't be confused with integers. When the floating point constants are whole numbers they have no decimal point so look like integers, but mean something very different in something like an 'and' instruction. Ideally we would just print a decimal point and a 0, but I couldn't see how to make APFloat::toString do that. llvm-svn: 345488
2018-10-29 12:52:04 +08:00
; HAS-FMA-NEXT: vmovapd {{.*#+}} ymm1 = [3.5E+0,2.5E+0,1.5E+0,5.0E-1]
; HAS-FMA-NEXT: vmovapd {{.*#+}} ymm0 = [7.5E+0,6.5E+0,5.5E+0,4.5E+0]
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
; HAS-FMA-NEXT: vfmadd213pd {{.*#+}} ymm0 = (ymm1 * ymm0) + mem
; HAS-FMA-NEXT: retq
entry:
%fma = call <4 x double> @llvm.experimental.constrained.fma.v4f64(
<4 x double> <double 3.5, double 2.5, double 1.5, double 0.5>,
<4 x double> <double 7.5, double 6.5, double 5.5, double 4.5>,
<4 x double> <double 11.5, double 10.5, double 9.5, double 8.5>,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <4 x double> %fma
}
[FPEnv] Expand constrained FP POWI Modify ExpandStrictFPOp(...) to handle nodes that have scalar operands. Also, add a Strict FMA test and do some other light cleanup in the Strict FP code. Differential Revision: https://reviews.llvm.org/D48149 llvm-svn: 334863
2018-06-16 04:57:55 +08:00
define <4 x float> @constrained_vector_fma_v4f32() {
; NO-FMA-LABEL: constrained_vector_fma_v4f32:
; NO-FMA: # %bb.0: # %entry
; NO-FMA-NEXT: subq $40, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 48
; NO-FMA-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; NO-FMA-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; NO-FMA-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; NO-FMA-NEXT: callq fmaf
; NO-FMA-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; NO-FMA-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; NO-FMA-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; NO-FMA-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; NO-FMA-NEXT: callq fmaf
; NO-FMA-NEXT: unpcklps (%rsp), %xmm0 # 16-byte Folded Reload
; NO-FMA-NEXT: # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
; NO-FMA-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; NO-FMA-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; NO-FMA-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; NO-FMA-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; NO-FMA-NEXT: callq fmaf
; NO-FMA-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; NO-FMA-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; NO-FMA-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; NO-FMA-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; NO-FMA-NEXT: callq fmaf
; NO-FMA-NEXT: unpcklps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; NO-FMA-NEXT: # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
; NO-FMA-NEXT: unpcklpd (%rsp), %xmm0 # 16-byte Folded Reload
; NO-FMA-NEXT: # xmm0 = xmm0[0],mem[0]
; NO-FMA-NEXT: addq $40, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 8
; NO-FMA-NEXT: retq
;
; HAS-FMA-LABEL: constrained_vector_fma_v4f32:
; HAS-FMA: # %bb.0: # %entry
[X86] Force floating point values in constant pool decoding to print in scientific notation so they can't be confused with integers. When the floating point constants are whole numbers they have no decimal point so look like integers, but mean something very different in something like an 'and' instruction. Ideally we would just print a decimal point and a 0, but I couldn't see how to make APFloat::toString do that. llvm-svn: 345488
2018-10-29 12:52:04 +08:00
; HAS-FMA-NEXT: vmovaps {{.*#+}} xmm1 = [3.5E+0,2.5E+0,1.5E+0,5.0E-1]
; HAS-FMA-NEXT: vmovaps {{.*#+}} xmm0 = [7.5E+0,6.5E+0,5.5E+0,4.5E+0]
[FPEnv] Expand constrained FP POWI Modify ExpandStrictFPOp(...) to handle nodes that have scalar operands. Also, add a Strict FMA test and do some other light cleanup in the Strict FP code. Differential Revision: https://reviews.llvm.org/D48149 llvm-svn: 334863
2018-06-16 04:57:55 +08:00
; HAS-FMA-NEXT: vfmadd213ps {{.*#+}} xmm0 = (xmm1 * xmm0) + mem
; HAS-FMA-NEXT: retq
entry:
%fma = call <4 x float> @llvm.experimental.constrained.fma.v4f32(
<4 x float> <float 3.5, float 2.5, float 1.5, float 0.5>,
<4 x float> <float 7.5, float 6.5, float 5.5, float 4.5>,
<4 x float> <float 11.5, float 10.5, float 9.5, float 8.5>,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <4 x float> %fma
}
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
define <8 x float> @constrained_vector_fma_v8f32() {
; NO-FMA-LABEL: constrained_vector_fma_v8f32:
; NO-FMA: # %bb.0: # %entry
; NO-FMA-NEXT: subq $56, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 64
; NO-FMA-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; NO-FMA-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; NO-FMA-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; NO-FMA-NEXT: callq fmaf
; NO-FMA-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; NO-FMA-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; NO-FMA-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; NO-FMA-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; NO-FMA-NEXT: callq fmaf
; NO-FMA-NEXT: unpcklps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; NO-FMA-NEXT: # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
; NO-FMA-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; NO-FMA-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; NO-FMA-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; NO-FMA-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; NO-FMA-NEXT: callq fmaf
; NO-FMA-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; NO-FMA-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; NO-FMA-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; NO-FMA-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; NO-FMA-NEXT: callq fmaf
; NO-FMA-NEXT: unpcklps (%rsp), %xmm0 # 16-byte Folded Reload
; NO-FMA-NEXT: # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
; NO-FMA-NEXT: unpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; NO-FMA-NEXT: # xmm0 = xmm0[0],mem[0]
; NO-FMA-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; NO-FMA-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; NO-FMA-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; NO-FMA-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; NO-FMA-NEXT: callq fmaf
; NO-FMA-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; NO-FMA-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; NO-FMA-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; NO-FMA-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; NO-FMA-NEXT: callq fmaf
; NO-FMA-NEXT: unpcklps (%rsp), %xmm0 # 16-byte Folded Reload
; NO-FMA-NEXT: # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
; NO-FMA-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; NO-FMA-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; NO-FMA-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; NO-FMA-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; NO-FMA-NEXT: callq fmaf
; NO-FMA-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; NO-FMA-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; NO-FMA-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; NO-FMA-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; NO-FMA-NEXT: callq fmaf
; NO-FMA-NEXT: movaps %xmm0, %xmm1
; NO-FMA-NEXT: unpcklps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload
; NO-FMA-NEXT: # xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
; NO-FMA-NEXT: unpcklpd (%rsp), %xmm1 # 16-byte Folded Reload
; NO-FMA-NEXT: # xmm1 = xmm1[0],mem[0]
; NO-FMA-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; NO-FMA-NEXT: addq $56, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 8
; NO-FMA-NEXT: retq
;
; HAS-FMA-LABEL: constrained_vector_fma_v8f32:
; HAS-FMA: # %bb.0: # %entry
[X86] Force floating point values in constant pool decoding to print in scientific notation so they can't be confused with integers. When the floating point constants are whole numbers they have no decimal point so look like integers, but mean something very different in something like an 'and' instruction. Ideally we would just print a decimal point and a 0, but I couldn't see how to make APFloat::toString do that. llvm-svn: 345488
2018-10-29 12:52:04 +08:00
; HAS-FMA-NEXT: vmovaps {{.*#+}} ymm1 = [3.5E+0,2.5E+0,1.5E+0,5.0E-1,7.5E+0,6.5E+0,5.5E+0,4.5E+0]
; HAS-FMA-NEXT: vmovaps {{.*#+}} ymm0 = [7.5E+0,6.5E+0,5.5E+0,4.5E+0,1.15E+1,1.05E+1,9.5E+0,8.5E+0]
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
; HAS-FMA-NEXT: vfmadd213ps {{.*#+}} ymm0 = (ymm1 * ymm0) + mem
; HAS-FMA-NEXT: retq
entry:
%fma = call <8 x float> @llvm.experimental.constrained.fma.v8f32(
<8 x float> <float 3.5, float 2.5, float 1.5, float 0.5,
float 7.5, float 6.5, float 5.5, float 4.5>,
<8 x float> <float 7.5, float 6.5, float 5.5, float 4.5,
float 11.5, float 10.5, float 9.5, float 8.5>,
<8 x float> <float 11.5, float 10.5, float 9.5, float 8.5,
float 15.5, float 14.5, float 13.5, float 12.5>,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <8 x float> %fma
}
[FPEnv] Scalarize StrictFP vector operations Add a helper function to scalarize constrained FP operations as needed. Differential Revision: https://reviews.llvm.org/D50720 llvm-svn: 339735
2018-08-15 06:13:11 +08:00
define <1 x float> @constrained_vector_sqrt_v1f32() {
; NO-FMA-LABEL: constrained_vector_sqrt_v1f32:
; NO-FMA: # %bb.0: # %entry
; NO-FMA-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; NO-FMA-NEXT: sqrtss %xmm0, %xmm0
; NO-FMA-NEXT: retq
;
; HAS-FMA-LABEL: constrained_vector_sqrt_v1f32:
; HAS-FMA: # %bb.0: # %entry
; HAS-FMA-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; HAS-FMA-NEXT: vsqrtss %xmm0, %xmm0, %xmm0
; HAS-FMA-NEXT: retq
entry:
%sqrt = call <1 x float> @llvm.experimental.constrained.sqrt.v1f32(
<1 x float> <float 42.0>,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <1 x float> %sqrt
}
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
define <2 x double> @constrained_vector_sqrt_v2f64() {
; NO-FMA-LABEL: constrained_vector_sqrt_v2f64:
[FPEnv] Expand constrained FP POWI Modify ExpandStrictFPOp(...) to handle nodes that have scalar operands. Also, add a Strict FMA test and do some other light cleanup in the Strict FP code. Differential Revision: https://reviews.llvm.org/D48149 llvm-svn: 334863
2018-06-16 04:57:55 +08:00
; NO-FMA: # %bb.0: # %entry
; NO-FMA-NEXT: sqrtpd {{.*}}(%rip), %xmm0
; NO-FMA-NEXT: retq
;
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
; HAS-FMA-LABEL: constrained_vector_sqrt_v2f64:
[FPEnv] Expand constrained FP POWI Modify ExpandStrictFPOp(...) to handle nodes that have scalar operands. Also, add a Strict FMA test and do some other light cleanup in the Strict FP code. Differential Revision: https://reviews.llvm.org/D48149 llvm-svn: 334863
2018-06-16 04:57:55 +08:00
; HAS-FMA: # %bb.0: # %entry
; HAS-FMA-NEXT: vsqrtpd {{.*}}(%rip), %xmm0
; HAS-FMA-NEXT: retq
[FPEnv] Expand constrained FP operations Add a helper function to expand constrained FP operations as needed. Note that the Strict POWI operation is not handled in this patch since the format is slightly different from the others. Differential Revision: https://reviews.llvm.org/D47491 llvm-svn: 334603
2018-06-13 22:32:12 +08:00
entry:
%sqrt = call <2 x double> @llvm.experimental.constrained.sqrt.v2f64(
<2 x double> <double 42.0, double 42.1>,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <2 x double> %sqrt
}
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
define <3 x float> @constrained_vector_sqrt_v3f32() {
; NO-FMA-LABEL: constrained_vector_sqrt_v3f32:
; NO-FMA: # %bb.0: # %entry
; NO-FMA-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; NO-FMA-NEXT: sqrtss %xmm0, %xmm1
; NO-FMA-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; NO-FMA-NEXT: sqrtss %xmm0, %xmm0
; NO-FMA-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; NO-FMA-NEXT: sqrtss %xmm2, %xmm2
; NO-FMA-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
; NO-FMA-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; NO-FMA-NEXT: retq
;
; HAS-FMA-LABEL: constrained_vector_sqrt_v3f32:
; HAS-FMA: # %bb.0: # %entry
; HAS-FMA-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; HAS-FMA-NEXT: vsqrtss %xmm0, %xmm0, %xmm0
; HAS-FMA-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; HAS-FMA-NEXT: vsqrtss %xmm1, %xmm1, %xmm1
; HAS-FMA-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; HAS-FMA-NEXT: vsqrtss %xmm2, %xmm2, %xmm2
; HAS-FMA-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[2,3]
; HAS-FMA-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1],xmm0[0],xmm1[3]
; HAS-FMA-NEXT: retq
entry:
%sqrt = call <3 x float> @llvm.experimental.constrained.sqrt.v3f32(
<3 x float> <float 42.0, float 43.0, float 44.0>,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <3 x float> %sqrt
}
define <3 x double> @constrained_vector_sqrt_v3f64() {
; NO-FMA-LABEL: constrained_vector_sqrt_v3f64:
; NO-FMA: # %bb.0: # %entry
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: sqrtsd %xmm0, %xmm1
; NO-FMA-NEXT: sqrtpd {{.*}}(%rip), %xmm0
; NO-FMA-NEXT: movsd %xmm1, -{{[0-9]+}}(%rsp)
; NO-FMA-NEXT: movapd %xmm0, %xmm1
[X86] Prefer unpckhpd over movhlps in isel for fake unary cases In r337348, I changed lowering to prefer X86ISD::UNPCKL/UNPCKH opcodes over MOVLHPS/MOVHLPS for v2f64 {0,0} and {1,1} shuffles when we have SSE2. This enabled the removal of a bunch of weirdly bitcasted isel patterns in r337349. To avoid changing the tests I placed a gross hack in isel to still emit movhlps instructions for fake unary unpckh nodes. A similar hack was not needed for unpckl and movlhps because we do execution domain switching for those. But unpckh and movhlps have swapped operand order. This patch removes the hack. This is a code size increase since unpckhpd requires a 0x66 prefix and movhlps does not. But if that's a big concern we should be using movhlps for all unpckhpd opcodes and let commuteInstruction turnit into unpckhpd when its an advantage. Differential Revision: https://reviews.llvm.org/D49499 llvm-svn: 341973
2018-09-12 01:57:27 +08:00
; NO-FMA-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
; NO-FMA-NEXT: fldl -{{[0-9]+}}(%rsp)
; NO-FMA-NEXT: retq
;
; HAS-FMA-LABEL: constrained_vector_sqrt_v3f64:
; HAS-FMA: # %bb.0: # %entry
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: vsqrtsd %xmm0, %xmm0, %xmm0
; HAS-FMA-NEXT: vsqrtpd {{.*}}(%rip), %xmm1
; HAS-FMA-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; HAS-FMA-NEXT: retq
entry:
%sqrt = call <3 x double> @llvm.experimental.constrained.sqrt.v3f64(
<3 x double> <double 42.0, double 42.1, double 42.2>,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <3 x double> %sqrt
}
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
define <4 x double> @constrained_vector_sqrt_v4f64() {
; NO-FMA-LABEL: constrained_vector_sqrt_v4f64:
; NO-FMA: # %bb.0: # %entry
; NO-FMA-NEXT: sqrtpd {{.*}}(%rip), %xmm0
Fix corruption of result number in LegalizeVectorOps.cpp When VectorLegalizer::LegalizeOp creates a new SDValue after iterating over its arguments, we need to refer to the same result number of the new node that the original value used. Reviewed by: cameron.mcinally Differential Revision: https://reviews.llvm.org/D49805 llvm-svn: 337939
2018-07-26 01:08:13 +08:00
; NO-FMA-NEXT: sqrtpd {{.*}}(%rip), %xmm1
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
; NO-FMA-NEXT: retq
;
; HAS-FMA-LABEL: constrained_vector_sqrt_v4f64:
; HAS-FMA: # %bb.0: # %entry
; HAS-FMA-NEXT: vsqrtpd {{.*}}(%rip), %ymm0
; HAS-FMA-NEXT: retq
entry:
%sqrt = call <4 x double> @llvm.experimental.constrained.sqrt.v4f64(
<4 x double> <double 42.0, double 42.1,
double 42.2, double 42.3>,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <4 x double> %sqrt
}
[FPEnv] Scalarize StrictFP vector operations Add a helper function to scalarize constrained FP operations as needed. Differential Revision: https://reviews.llvm.org/D50720 llvm-svn: 339735
2018-08-15 06:13:11 +08:00
define <1 x float> @constrained_vector_pow_v1f32() {
; NO-FMA-LABEL: constrained_vector_pow_v1f32:
; NO-FMA: # %bb.0: # %entry
; NO-FMA-NEXT: pushq %rax
; NO-FMA-NEXT: .cfi_def_cfa_offset 16
; NO-FMA-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; NO-FMA-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; NO-FMA-NEXT: callq powf
; NO-FMA-NEXT: popq %rax
; NO-FMA-NEXT: .cfi_def_cfa_offset 8
; NO-FMA-NEXT: retq
;
; HAS-FMA-LABEL: constrained_vector_pow_v1f32:
; HAS-FMA: # %bb.0: # %entry
; HAS-FMA-NEXT: pushq %rax
; HAS-FMA-NEXT: .cfi_def_cfa_offset 16
; HAS-FMA-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; HAS-FMA-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; HAS-FMA-NEXT: callq powf
; HAS-FMA-NEXT: popq %rax
; HAS-FMA-NEXT: .cfi_def_cfa_offset 8
; HAS-FMA-NEXT: retq
entry:
%pow = call <1 x float> @llvm.experimental.constrained.pow.v1f32(
<1 x float> <float 42.0>,
<1 x float> <float 3.0>,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <1 x float> %pow
}
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
define <2 x double> @constrained_vector_pow_v2f64() {
; NO-FMA-LABEL: constrained_vector_pow_v2f64:
[FPEnv] Expand constrained FP POWI Modify ExpandStrictFPOp(...) to handle nodes that have scalar operands. Also, add a Strict FMA test and do some other light cleanup in the Strict FP code. Differential Revision: https://reviews.llvm.org/D48149 llvm-svn: 334863
2018-06-16 04:57:55 +08:00
; NO-FMA: # %bb.0: # %entry
; NO-FMA-NEXT: subq $24, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 32
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
; NO-FMA-NEXT: callq pow
; NO-FMA-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
; NO-FMA-NEXT: callq pow
; NO-FMA-NEXT: unpcklpd (%rsp), %xmm0 # 16-byte Folded Reload
; NO-FMA-NEXT: # xmm0 = xmm0[0],mem[0]
; NO-FMA-NEXT: addq $24, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 8
; NO-FMA-NEXT: retq
;
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
; HAS-FMA-LABEL: constrained_vector_pow_v2f64:
[FPEnv] Expand constrained FP POWI Modify ExpandStrictFPOp(...) to handle nodes that have scalar operands. Also, add a Strict FMA test and do some other light cleanup in the Strict FP code. Differential Revision: https://reviews.llvm.org/D48149 llvm-svn: 334863
2018-06-16 04:57:55 +08:00
; HAS-FMA: # %bb.0: # %entry
; HAS-FMA-NEXT: subq $24, %rsp
; HAS-FMA-NEXT: .cfi_def_cfa_offset 32
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero
; HAS-FMA-NEXT: callq pow
; HAS-FMA-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero
; HAS-FMA-NEXT: callq pow
; HAS-FMA-NEXT: vunpcklpd (%rsp), %xmm0, %xmm0 # 16-byte Folded Reload
; HAS-FMA-NEXT: # xmm0 = xmm0[0],mem[0]
; HAS-FMA-NEXT: addq $24, %rsp
; HAS-FMA-NEXT: .cfi_def_cfa_offset 8
; HAS-FMA-NEXT: retq
[FPEnv] Expand constrained FP operations Add a helper function to expand constrained FP operations as needed. Note that the Strict POWI operation is not handled in this patch since the format is slightly different from the others. Differential Revision: https://reviews.llvm.org/D47491 llvm-svn: 334603
2018-06-13 22:32:12 +08:00
entry:
%pow = call <2 x double> @llvm.experimental.constrained.pow.v2f64(
<2 x double> <double 42.1, double 42.2>,
<2 x double> <double 3.0, double 3.0>,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <2 x double> %pow
}
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
define <3 x float> @constrained_vector_pow_v3f32() {
; NO-FMA-LABEL: constrained_vector_pow_v3f32:
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
; NO-FMA: # %bb.0: # %entry
; NO-FMA-NEXT: subq $40, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 48
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
; NO-FMA-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; NO-FMA-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; NO-FMA-NEXT: callq powf
; NO-FMA-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; NO-FMA-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; NO-FMA-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; NO-FMA-NEXT: callq powf
; NO-FMA-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; NO-FMA-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; NO-FMA-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; NO-FMA-NEXT: callq powf
; NO-FMA-NEXT: movaps (%rsp), %xmm1 # 16-byte Reload
; NO-FMA-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; NO-FMA-NEXT: unpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload
; NO-FMA-NEXT: # xmm1 = xmm1[0],mem[0]
; NO-FMA-NEXT: movaps %xmm1, %xmm0
; NO-FMA-NEXT: addq $40, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 8
; NO-FMA-NEXT: retq
;
; HAS-FMA-LABEL: constrained_vector_pow_v3f32:
; HAS-FMA: # %bb.0: # %entry
; HAS-FMA-NEXT: subq $40, %rsp
; HAS-FMA-NEXT: .cfi_def_cfa_offset 48
; HAS-FMA-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; HAS-FMA-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; HAS-FMA-NEXT: callq powf
; HAS-FMA-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; HAS-FMA-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; HAS-FMA-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; HAS-FMA-NEXT: callq powf
; HAS-FMA-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
; HAS-FMA-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; HAS-FMA-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; HAS-FMA-NEXT: callq powf
; HAS-FMA-NEXT: vmovaps (%rsp), %xmm1 # 16-byte Reload
; HAS-FMA-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[2,3]
; HAS-FMA-NEXT: vinsertps $32, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm0 # 16-byte Folded Reload
; HAS-FMA-NEXT: # xmm0 = xmm0[0,1],mem[0],xmm0[3]
; HAS-FMA-NEXT: addq $40, %rsp
; HAS-FMA-NEXT: .cfi_def_cfa_offset 8
; HAS-FMA-NEXT: retq
entry:
%pow = call <3 x float> @llvm.experimental.constrained.pow.v3f32(
<3 x float> <float 42.0, float 43.0, float 44.0>,
<3 x float> <float 3.0, float 3.0, float 3.0>,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <3 x float> %pow
}
define <3 x double> @constrained_vector_pow_v3f64() {
; NO-FMA-LABEL: constrained_vector_pow_v3f64:
; NO-FMA: # %bb.0: # %entry
[X86] Add initial SimplifyDemandedVectorEltsForTargetNode support This patch adds an initial x86 SimplifyDemandedVectorEltsForTargetNode implementation to handle target shuffles. Currently the patch only decodes a target shuffle, calls SimplifyDemandedVectorElts on its input operands and removes any shuffle that reduces to undef/zero/identity. Future work will need to integrate this with combineX86ShufflesRecursively, add support for other x86 ops, etc. NOTE: There is a minor regression that appears to be affecting further (extractelement?) combines which I haven't been able to solve yet - possibly something to do with how nodes are added to the worklist after simplification. Differential Revision: https://reviews.llvm.org/D52140 llvm-svn: 342564
2018-09-20 02:11:34 +08:00
; NO-FMA-NEXT: subq $24, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 32
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
; NO-FMA-NEXT: callq pow
[X86] Add initial SimplifyDemandedVectorEltsForTargetNode support This patch adds an initial x86 SimplifyDemandedVectorEltsForTargetNode implementation to handle target shuffles. Currently the patch only decodes a target shuffle, calls SimplifyDemandedVectorElts on its input operands and removes any shuffle that reduces to undef/zero/identity. Future work will need to integrate this with combineX86ShufflesRecursively, add support for other x86 ops, etc. NOTE: There is a minor regression that appears to be affecting further (extractelement?) combines which I haven't been able to solve yet - possibly something to do with how nodes are added to the worklist after simplification. Differential Revision: https://reviews.llvm.org/D52140 llvm-svn: 342564
2018-09-20 02:11:34 +08:00
; NO-FMA-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
; NO-FMA-NEXT: callq pow
[X86] Add initial SimplifyDemandedVectorEltsForTargetNode support This patch adds an initial x86 SimplifyDemandedVectorEltsForTargetNode implementation to handle target shuffles. Currently the patch only decodes a target shuffle, calls SimplifyDemandedVectorElts on its input operands and removes any shuffle that reduces to undef/zero/identity. Future work will need to integrate this with combineX86ShufflesRecursively, add support for other x86 ops, etc. NOTE: There is a minor regression that appears to be affecting further (extractelement?) combines which I haven't been able to solve yet - possibly something to do with how nodes are added to the worklist after simplification. Differential Revision: https://reviews.llvm.org/D52140 llvm-svn: 342564
2018-09-20 02:11:34 +08:00
; NO-FMA-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
; NO-FMA-NEXT: callq pow
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
; NO-FMA-NEXT: movsd %xmm0, {{[0-9]+}}(%rsp)
; NO-FMA-NEXT: fldl {{[0-9]+}}(%rsp)
[X86] Add initial SimplifyDemandedVectorEltsForTargetNode support This patch adds an initial x86 SimplifyDemandedVectorEltsForTargetNode implementation to handle target shuffles. Currently the patch only decodes a target shuffle, calls SimplifyDemandedVectorElts on its input operands and removes any shuffle that reduces to undef/zero/identity. Future work will need to integrate this with combineX86ShufflesRecursively, add support for other x86 ops, etc. NOTE: There is a minor regression that appears to be affecting further (extractelement?) combines which I haven't been able to solve yet - possibly something to do with how nodes are added to the worklist after simplification. Differential Revision: https://reviews.llvm.org/D52140 llvm-svn: 342564
2018-09-20 02:11:34 +08:00
; NO-FMA-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload
; NO-FMA-NEXT: # xmm0 = mem[0],zero
; NO-FMA-NEXT: movsd (%rsp), %xmm1 # 8-byte Reload
; NO-FMA-NEXT: # xmm1 = mem[0],zero
; NO-FMA-NEXT: addq $24, %rsp
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
; NO-FMA-NEXT: .cfi_def_cfa_offset 8
; NO-FMA-NEXT: retq
;
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
; HAS-FMA-LABEL: constrained_vector_pow_v3f64:
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
; HAS-FMA: # %bb.0: # %entry
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
; HAS-FMA-NEXT: subq $56, %rsp
; HAS-FMA-NEXT: .cfi_def_cfa_offset 64
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero
; HAS-FMA-NEXT: callq pow
; HAS-FMA-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero
; HAS-FMA-NEXT: callq pow
; HAS-FMA-NEXT: vunpcklpd (%rsp), %xmm0, %xmm0 # 16-byte Folded Reload
; HAS-FMA-NEXT: # xmm0 = xmm0[0],mem[0]
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
; HAS-FMA-NEXT: vmovups %ymm0, (%rsp) # 32-byte Spill
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
; HAS-FMA-NEXT: vzeroupper
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
; HAS-FMA-NEXT: callq pow
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
; HAS-FMA-NEXT: vmovups (%rsp), %ymm1 # 32-byte Reload
; HAS-FMA-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; HAS-FMA-NEXT: addq $56, %rsp
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
; HAS-FMA-NEXT: .cfi_def_cfa_offset 8
; HAS-FMA-NEXT: retq
entry:
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
%pow = call <3 x double> @llvm.experimental.constrained.pow.v3f64(
<3 x double> <double 42.0, double 42.1, double 42.2>,
<3 x double> <double 3.0, double 3.0, double 3.0>,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <3 x double> %pow
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
}
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
define <4 x double> @constrained_vector_pow_v4f64() {
; NO-FMA-LABEL: constrained_vector_pow_v4f64:
; NO-FMA: # %bb.0: # %entry
; NO-FMA-NEXT: subq $40, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 48
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
; NO-FMA-NEXT: callq pow
; NO-FMA-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
; NO-FMA-NEXT: callq pow
; NO-FMA-NEXT: unpcklpd (%rsp), %xmm0 # 16-byte Folded Reload
; NO-FMA-NEXT: # xmm0 = xmm0[0],mem[0]
; NO-FMA-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
; NO-FMA-NEXT: callq pow
; NO-FMA-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
; NO-FMA-NEXT: callq pow
; NO-FMA-NEXT: movaps %xmm0, %xmm1
; NO-FMA-NEXT: unpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload
; NO-FMA-NEXT: # xmm1 = xmm1[0],mem[0]
; NO-FMA-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; NO-FMA-NEXT: addq $40, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 8
; NO-FMA-NEXT: retq
;
; HAS-FMA-LABEL: constrained_vector_pow_v4f64:
; HAS-FMA: # %bb.0: # %entry
; HAS-FMA-NEXT: subq $40, %rsp
; HAS-FMA-NEXT: .cfi_def_cfa_offset 48
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero
; HAS-FMA-NEXT: callq pow
; HAS-FMA-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero
; HAS-FMA-NEXT: callq pow
; HAS-FMA-NEXT: vunpcklpd (%rsp), %xmm0, %xmm0 # 16-byte Folded Reload
; HAS-FMA-NEXT: # xmm0 = xmm0[0],mem[0]
; HAS-FMA-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero
; HAS-FMA-NEXT: callq pow
; HAS-FMA-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero
; HAS-FMA-NEXT: callq pow
; HAS-FMA-NEXT: vunpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm0 # 16-byte Folded Reload
; HAS-FMA-NEXT: # xmm0 = xmm0[0],mem[0]
; HAS-FMA-NEXT: vinsertf128 $1, (%rsp), %ymm0, %ymm0 # 16-byte Folded Reload
; HAS-FMA-NEXT: addq $40, %rsp
; HAS-FMA-NEXT: .cfi_def_cfa_offset 8
; HAS-FMA-NEXT: retq
entry:
%pow = call <4 x double> @llvm.experimental.constrained.pow.v4f64(
<4 x double> <double 42.1, double 42.2,
double 42.3, double 42.4>,
<4 x double> <double 3.0, double 3.0,
double 3.0, double 3.0>,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <4 x double> %pow
}
[FPEnv] Scalarize StrictFP vector operations Add a helper function to scalarize constrained FP operations as needed. Differential Revision: https://reviews.llvm.org/D50720 llvm-svn: 339735
2018-08-15 06:13:11 +08:00
define <1 x float> @constrained_vector_powi_v1f32() {
; NO-FMA-LABEL: constrained_vector_powi_v1f32:
; NO-FMA: # %bb.0: # %entry
; NO-FMA-NEXT: pushq %rax
; NO-FMA-NEXT: .cfi_def_cfa_offset 16
; NO-FMA-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; NO-FMA-NEXT: movl $3, %edi
; NO-FMA-NEXT: callq __powisf2
; NO-FMA-NEXT: popq %rax
; NO-FMA-NEXT: .cfi_def_cfa_offset 8
; NO-FMA-NEXT: retq
;
; HAS-FMA-LABEL: constrained_vector_powi_v1f32:
; HAS-FMA: # %bb.0: # %entry
; HAS-FMA-NEXT: pushq %rax
; HAS-FMA-NEXT: .cfi_def_cfa_offset 16
; HAS-FMA-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; HAS-FMA-NEXT: movl $3, %edi
; HAS-FMA-NEXT: callq __powisf2
; HAS-FMA-NEXT: popq %rax
; HAS-FMA-NEXT: .cfi_def_cfa_offset 8
; HAS-FMA-NEXT: retq
entry:
%powi = call <1 x float> @llvm.experimental.constrained.powi.v1f32(
<1 x float> <float 42.0>,
i32 3,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <1 x float> %powi
}
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
define <2 x double> @constrained_vector_powi_v2f64() {
; NO-FMA-LABEL: constrained_vector_powi_v2f64:
; NO-FMA: # %bb.0: # %entry
[FPEnv] Expand constrained FP POWI Modify ExpandStrictFPOp(...) to handle nodes that have scalar operands. Also, add a Strict FMA test and do some other light cleanup in the Strict FP code. Differential Revision: https://reviews.llvm.org/D48149 llvm-svn: 334863
2018-06-16 04:57:55 +08:00
; NO-FMA-NEXT: subq $24, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 32
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: movl $3, %edi
; NO-FMA-NEXT: callq __powidf2
; NO-FMA-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: movl $3, %edi
; NO-FMA-NEXT: callq __powidf2
; NO-FMA-NEXT: unpcklpd (%rsp), %xmm0 # 16-byte Folded Reload
; NO-FMA-NEXT: # xmm0 = xmm0[0],mem[0]
; NO-FMA-NEXT: addq $24, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 8
; NO-FMA-NEXT: retq
;
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
; HAS-FMA-LABEL: constrained_vector_powi_v2f64:
[FPEnv] Expand constrained FP POWI Modify ExpandStrictFPOp(...) to handle nodes that have scalar operands. Also, add a Strict FMA test and do some other light cleanup in the Strict FP code. Differential Revision: https://reviews.llvm.org/D48149 llvm-svn: 334863
2018-06-16 04:57:55 +08:00
; HAS-FMA: # %bb.0: # %entry
; HAS-FMA-NEXT: subq $24, %rsp
; HAS-FMA-NEXT: .cfi_def_cfa_offset 32
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: movl $3, %edi
; HAS-FMA-NEXT: callq __powidf2
; HAS-FMA-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: movl $3, %edi
; HAS-FMA-NEXT: callq __powidf2
; HAS-FMA-NEXT: vunpcklpd (%rsp), %xmm0, %xmm0 # 16-byte Folded Reload
; HAS-FMA-NEXT: # xmm0 = xmm0[0],mem[0]
; HAS-FMA-NEXT: addq $24, %rsp
; HAS-FMA-NEXT: .cfi_def_cfa_offset 8
; HAS-FMA-NEXT: retq
entry:
%powi = call <2 x double> @llvm.experimental.constrained.powi.v2f64(
<2 x double> <double 42.1, double 42.2>,
i32 3,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <2 x double> %powi
}
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
define <3 x float> @constrained_vector_powi_v3f32() {
; NO-FMA-LABEL: constrained_vector_powi_v3f32:
; NO-FMA: # %bb.0: # %entry
; NO-FMA-NEXT: subq $40, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 48
; NO-FMA-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; NO-FMA-NEXT: movl $3, %edi
; NO-FMA-NEXT: callq __powisf2
; NO-FMA-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; NO-FMA-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; NO-FMA-NEXT: movl $3, %edi
; NO-FMA-NEXT: callq __powisf2
; NO-FMA-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; NO-FMA-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; NO-FMA-NEXT: movl $3, %edi
; NO-FMA-NEXT: callq __powisf2
; NO-FMA-NEXT: movaps (%rsp), %xmm1 # 16-byte Reload
; NO-FMA-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; NO-FMA-NEXT: unpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload
; NO-FMA-NEXT: # xmm1 = xmm1[0],mem[0]
; NO-FMA-NEXT: movaps %xmm1, %xmm0
; NO-FMA-NEXT: addq $40, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 8
; NO-FMA-NEXT: retq
;
; HAS-FMA-LABEL: constrained_vector_powi_v3f32:
; HAS-FMA: # %bb.0: # %entry
; HAS-FMA-NEXT: subq $40, %rsp
; HAS-FMA-NEXT: .cfi_def_cfa_offset 48
; HAS-FMA-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; HAS-FMA-NEXT: movl $3, %edi
; HAS-FMA-NEXT: callq __powisf2
; HAS-FMA-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; HAS-FMA-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; HAS-FMA-NEXT: movl $3, %edi
; HAS-FMA-NEXT: callq __powisf2
; HAS-FMA-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
; HAS-FMA-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; HAS-FMA-NEXT: movl $3, %edi
; HAS-FMA-NEXT: callq __powisf2
; HAS-FMA-NEXT: vmovaps (%rsp), %xmm1 # 16-byte Reload
; HAS-FMA-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[2,3]
; HAS-FMA-NEXT: vinsertps $32, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm0 # 16-byte Folded Reload
; HAS-FMA-NEXT: # xmm0 = xmm0[0,1],mem[0],xmm0[3]
; HAS-FMA-NEXT: addq $40, %rsp
; HAS-FMA-NEXT: .cfi_def_cfa_offset 8
; HAS-FMA-NEXT: retq
entry:
%powi = call <3 x float> @llvm.experimental.constrained.powi.v3f32(
<3 x float> <float 42.0, float 43.0, float 44.0>,
i32 3,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <3 x float> %powi
}
define <3 x double> @constrained_vector_powi_v3f64() {
; NO-FMA-LABEL: constrained_vector_powi_v3f64:
; NO-FMA: # %bb.0: # %entry
[X86] Add initial SimplifyDemandedVectorEltsForTargetNode support This patch adds an initial x86 SimplifyDemandedVectorEltsForTargetNode implementation to handle target shuffles. Currently the patch only decodes a target shuffle, calls SimplifyDemandedVectorElts on its input operands and removes any shuffle that reduces to undef/zero/identity. Future work will need to integrate this with combineX86ShufflesRecursively, add support for other x86 ops, etc. NOTE: There is a minor regression that appears to be affecting further (extractelement?) combines which I haven't been able to solve yet - possibly something to do with how nodes are added to the worklist after simplification. Differential Revision: https://reviews.llvm.org/D52140 llvm-svn: 342564
2018-09-20 02:11:34 +08:00
; NO-FMA-NEXT: subq $24, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 32
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: movl $3, %edi
; NO-FMA-NEXT: callq __powidf2
[X86] Add initial SimplifyDemandedVectorEltsForTargetNode support This patch adds an initial x86 SimplifyDemandedVectorEltsForTargetNode implementation to handle target shuffles. Currently the patch only decodes a target shuffle, calls SimplifyDemandedVectorElts on its input operands and removes any shuffle that reduces to undef/zero/identity. Future work will need to integrate this with combineX86ShufflesRecursively, add support for other x86 ops, etc. NOTE: There is a minor regression that appears to be affecting further (extractelement?) combines which I haven't been able to solve yet - possibly something to do with how nodes are added to the worklist after simplification. Differential Revision: https://reviews.llvm.org/D52140 llvm-svn: 342564
2018-09-20 02:11:34 +08:00
; NO-FMA-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: movl $3, %edi
; NO-FMA-NEXT: callq __powidf2
[X86] Add initial SimplifyDemandedVectorEltsForTargetNode support This patch adds an initial x86 SimplifyDemandedVectorEltsForTargetNode implementation to handle target shuffles. Currently the patch only decodes a target shuffle, calls SimplifyDemandedVectorElts on its input operands and removes any shuffle that reduces to undef/zero/identity. Future work will need to integrate this with combineX86ShufflesRecursively, add support for other x86 ops, etc. NOTE: There is a minor regression that appears to be affecting further (extractelement?) combines which I haven't been able to solve yet - possibly something to do with how nodes are added to the worklist after simplification. Differential Revision: https://reviews.llvm.org/D52140 llvm-svn: 342564
2018-09-20 02:11:34 +08:00
; NO-FMA-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: movl $3, %edi
; NO-FMA-NEXT: callq __powidf2
; NO-FMA-NEXT: movsd %xmm0, {{[0-9]+}}(%rsp)
; NO-FMA-NEXT: fldl {{[0-9]+}}(%rsp)
[X86] Add initial SimplifyDemandedVectorEltsForTargetNode support This patch adds an initial x86 SimplifyDemandedVectorEltsForTargetNode implementation to handle target shuffles. Currently the patch only decodes a target shuffle, calls SimplifyDemandedVectorElts on its input operands and removes any shuffle that reduces to undef/zero/identity. Future work will need to integrate this with combineX86ShufflesRecursively, add support for other x86 ops, etc. NOTE: There is a minor regression that appears to be affecting further (extractelement?) combines which I haven't been able to solve yet - possibly something to do with how nodes are added to the worklist after simplification. Differential Revision: https://reviews.llvm.org/D52140 llvm-svn: 342564
2018-09-20 02:11:34 +08:00
; NO-FMA-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload
; NO-FMA-NEXT: # xmm0 = mem[0],zero
; NO-FMA-NEXT: movsd (%rsp), %xmm1 # 8-byte Reload
; NO-FMA-NEXT: # xmm1 = mem[0],zero
; NO-FMA-NEXT: addq $24, %rsp
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
; NO-FMA-NEXT: .cfi_def_cfa_offset 8
; NO-FMA-NEXT: retq
;
; HAS-FMA-LABEL: constrained_vector_powi_v3f64:
; HAS-FMA: # %bb.0: # %entry
; HAS-FMA-NEXT: subq $56, %rsp
; HAS-FMA-NEXT: .cfi_def_cfa_offset 64
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: movl $3, %edi
; HAS-FMA-NEXT: callq __powidf2
; HAS-FMA-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: movl $3, %edi
; HAS-FMA-NEXT: callq __powidf2
; HAS-FMA-NEXT: vunpcklpd (%rsp), %xmm0, %xmm0 # 16-byte Folded Reload
; HAS-FMA-NEXT: # xmm0 = xmm0[0],mem[0]
; HAS-FMA-NEXT: vmovups %ymm0, (%rsp) # 32-byte Spill
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: movl $3, %edi
; HAS-FMA-NEXT: vzeroupper
; HAS-FMA-NEXT: callq __powidf2
; HAS-FMA-NEXT: vmovups (%rsp), %ymm1 # 32-byte Reload
; HAS-FMA-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; HAS-FMA-NEXT: addq $56, %rsp
; HAS-FMA-NEXT: .cfi_def_cfa_offset 8
; HAS-FMA-NEXT: retq
entry:
%powi = call <3 x double> @llvm.experimental.constrained.powi.v3f64(
<3 x double> <double 42.0, double 42.1, double 42.2>,
i32 3,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <3 x double> %powi
}
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
define <4 x double> @constrained_vector_powi_v4f64() {
; NO-FMA-LABEL: constrained_vector_powi_v4f64:
[FPEnv] Expand constrained FP POWI Modify ExpandStrictFPOp(...) to handle nodes that have scalar operands. Also, add a Strict FMA test and do some other light cleanup in the Strict FP code. Differential Revision: https://reviews.llvm.org/D48149 llvm-svn: 334863
2018-06-16 04:57:55 +08:00
; NO-FMA: # %bb.0: # %entry
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
; NO-FMA-NEXT: subq $40, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 48
[FPEnv] Expand constrained FP POWI Modify ExpandStrictFPOp(...) to handle nodes that have scalar operands. Also, add a Strict FMA test and do some other light cleanup in the Strict FP code. Differential Revision: https://reviews.llvm.org/D48149 llvm-svn: 334863
2018-06-16 04:57:55 +08:00
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
; NO-FMA-NEXT: movl $3, %edi
; NO-FMA-NEXT: callq __powidf2
[FPEnv] Expand constrained FP POWI Modify ExpandStrictFPOp(...) to handle nodes that have scalar operands. Also, add a Strict FMA test and do some other light cleanup in the Strict FP code. Differential Revision: https://reviews.llvm.org/D48149 llvm-svn: 334863
2018-06-16 04:57:55 +08:00
; NO-FMA-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
; NO-FMA-NEXT: movl $3, %edi
; NO-FMA-NEXT: callq __powidf2
[FPEnv] Expand constrained FP POWI Modify ExpandStrictFPOp(...) to handle nodes that have scalar operands. Also, add a Strict FMA test and do some other light cleanup in the Strict FP code. Differential Revision: https://reviews.llvm.org/D48149 llvm-svn: 334863
2018-06-16 04:57:55 +08:00
; NO-FMA-NEXT: unpcklpd (%rsp), %xmm0 # 16-byte Folded Reload
; NO-FMA-NEXT: # xmm0 = xmm0[0],mem[0]
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
; NO-FMA-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: movl $3, %edi
; NO-FMA-NEXT: callq __powidf2
; NO-FMA-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: movl $3, %edi
; NO-FMA-NEXT: callq __powidf2
; NO-FMA-NEXT: movaps %xmm0, %xmm1
; NO-FMA-NEXT: unpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload
; NO-FMA-NEXT: # xmm1 = xmm1[0],mem[0]
; NO-FMA-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; NO-FMA-NEXT: addq $40, %rsp
[FPEnv] Expand constrained FP POWI Modify ExpandStrictFPOp(...) to handle nodes that have scalar operands. Also, add a Strict FMA test and do some other light cleanup in the Strict FP code. Differential Revision: https://reviews.llvm.org/D48149 llvm-svn: 334863
2018-06-16 04:57:55 +08:00
; NO-FMA-NEXT: .cfi_def_cfa_offset 8
; NO-FMA-NEXT: retq
;
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
; HAS-FMA-LABEL: constrained_vector_powi_v4f64:
[FPEnv] Expand constrained FP POWI Modify ExpandStrictFPOp(...) to handle nodes that have scalar operands. Also, add a Strict FMA test and do some other light cleanup in the Strict FP code. Differential Revision: https://reviews.llvm.org/D48149 llvm-svn: 334863
2018-06-16 04:57:55 +08:00
; HAS-FMA: # %bb.0: # %entry
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
; HAS-FMA-NEXT: subq $40, %rsp
; HAS-FMA-NEXT: .cfi_def_cfa_offset 48
[FPEnv] Expand constrained FP POWI Modify ExpandStrictFPOp(...) to handle nodes that have scalar operands. Also, add a Strict FMA test and do some other light cleanup in the Strict FP code. Differential Revision: https://reviews.llvm.org/D48149 llvm-svn: 334863
2018-06-16 04:57:55 +08:00
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
; HAS-FMA-NEXT: movl $3, %edi
; HAS-FMA-NEXT: callq __powidf2
[FPEnv] Expand constrained FP POWI Modify ExpandStrictFPOp(...) to handle nodes that have scalar operands. Also, add a Strict FMA test and do some other light cleanup in the Strict FP code. Differential Revision: https://reviews.llvm.org/D48149 llvm-svn: 334863
2018-06-16 04:57:55 +08:00
; HAS-FMA-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
; HAS-FMA-NEXT: movl $3, %edi
; HAS-FMA-NEXT: callq __powidf2
[FPEnv] Expand constrained FP POWI Modify ExpandStrictFPOp(...) to handle nodes that have scalar operands. Also, add a Strict FMA test and do some other light cleanup in the Strict FP code. Differential Revision: https://reviews.llvm.org/D48149 llvm-svn: 334863
2018-06-16 04:57:55 +08:00
; HAS-FMA-NEXT: vunpcklpd (%rsp), %xmm0, %xmm0 # 16-byte Folded Reload
; HAS-FMA-NEXT: # xmm0 = xmm0[0],mem[0]
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
; HAS-FMA-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: movl $3, %edi
; HAS-FMA-NEXT: callq __powidf2
; HAS-FMA-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: movl $3, %edi
; HAS-FMA-NEXT: callq __powidf2
; HAS-FMA-NEXT: vunpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm0 # 16-byte Folded Reload
; HAS-FMA-NEXT: # xmm0 = xmm0[0],mem[0]
; HAS-FMA-NEXT: vinsertf128 $1, (%rsp), %ymm0, %ymm0 # 16-byte Folded Reload
; HAS-FMA-NEXT: addq $40, %rsp
[FPEnv] Expand constrained FP POWI Modify ExpandStrictFPOp(...) to handle nodes that have scalar operands. Also, add a Strict FMA test and do some other light cleanup in the Strict FP code. Differential Revision: https://reviews.llvm.org/D48149 llvm-svn: 334863
2018-06-16 04:57:55 +08:00
; HAS-FMA-NEXT: .cfi_def_cfa_offset 8
; HAS-FMA-NEXT: retq
[FPEnv] Expand constrained FP operations Add a helper function to expand constrained FP operations as needed. Note that the Strict POWI operation is not handled in this patch since the format is slightly different from the others. Differential Revision: https://reviews.llvm.org/D47491 llvm-svn: 334603
2018-06-13 22:32:12 +08:00
entry:
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
%powi = call <4 x double> @llvm.experimental.constrained.powi.v4f64(
<4 x double> <double 42.1, double 42.2,
double 42.3, double 42.4>,
i32 3,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <4 x double> %powi
[FPEnv] Expand constrained FP operations Add a helper function to expand constrained FP operations as needed. Note that the Strict POWI operation is not handled in this patch since the format is slightly different from the others. Differential Revision: https://reviews.llvm.org/D47491 llvm-svn: 334603
2018-06-13 22:32:12 +08:00
}
[FPEnv] Scalarize StrictFP vector operations Add a helper function to scalarize constrained FP operations as needed. Differential Revision: https://reviews.llvm.org/D50720 llvm-svn: 339735
2018-08-15 06:13:11 +08:00
define <1 x float> @constrained_vector_sin_v1f32() {
; NO-FMA-LABEL: constrained_vector_sin_v1f32:
; NO-FMA: # %bb.0: # %entry
; NO-FMA-NEXT: pushq %rax
; NO-FMA-NEXT: .cfi_def_cfa_offset 16
; NO-FMA-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; NO-FMA-NEXT: callq sinf
; NO-FMA-NEXT: popq %rax
; NO-FMA-NEXT: .cfi_def_cfa_offset 8
; NO-FMA-NEXT: retq
;
; HAS-FMA-LABEL: constrained_vector_sin_v1f32:
; HAS-FMA: # %bb.0: # %entry
; HAS-FMA-NEXT: pushq %rax
; HAS-FMA-NEXT: .cfi_def_cfa_offset 16
; HAS-FMA-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; HAS-FMA-NEXT: callq sinf
; HAS-FMA-NEXT: popq %rax
; HAS-FMA-NEXT: .cfi_def_cfa_offset 8
; HAS-FMA-NEXT: retq
entry:
%sin = call <1 x float> @llvm.experimental.constrained.sin.v1f32(
<1 x float> <float 42.0>,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <1 x float> %sin
}
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
define <2 x double> @constrained_vector_sin_v2f64() {
; NO-FMA-LABEL: constrained_vector_sin_v2f64:
[FPEnv] Expand constrained FP POWI Modify ExpandStrictFPOp(...) to handle nodes that have scalar operands. Also, add a Strict FMA test and do some other light cleanup in the Strict FP code. Differential Revision: https://reviews.llvm.org/D48149 llvm-svn: 334863
2018-06-16 04:57:55 +08:00
; NO-FMA: # %bb.0: # %entry
; NO-FMA-NEXT: subq $24, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 32
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
; NO-FMA-NEXT: callq sin
[FPEnv] Expand constrained FP POWI Modify ExpandStrictFPOp(...) to handle nodes that have scalar operands. Also, add a Strict FMA test and do some other light cleanup in the Strict FP code. Differential Revision: https://reviews.llvm.org/D48149 llvm-svn: 334863
2018-06-16 04:57:55 +08:00
; NO-FMA-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
; NO-FMA-NEXT: callq sin
[FPEnv] Expand constrained FP POWI Modify ExpandStrictFPOp(...) to handle nodes that have scalar operands. Also, add a Strict FMA test and do some other light cleanup in the Strict FP code. Differential Revision: https://reviews.llvm.org/D48149 llvm-svn: 334863
2018-06-16 04:57:55 +08:00
; NO-FMA-NEXT: unpcklpd (%rsp), %xmm0 # 16-byte Folded Reload
; NO-FMA-NEXT: # xmm0 = xmm0[0],mem[0]
; NO-FMA-NEXT: addq $24, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 8
; NO-FMA-NEXT: retq
;
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
; HAS-FMA-LABEL: constrained_vector_sin_v2f64:
[FPEnv] Expand constrained FP POWI Modify ExpandStrictFPOp(...) to handle nodes that have scalar operands. Also, add a Strict FMA test and do some other light cleanup in the Strict FP code. Differential Revision: https://reviews.llvm.org/D48149 llvm-svn: 334863
2018-06-16 04:57:55 +08:00
; HAS-FMA: # %bb.0: # %entry
; HAS-FMA-NEXT: subq $24, %rsp
; HAS-FMA-NEXT: .cfi_def_cfa_offset 32
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
; HAS-FMA-NEXT: callq sin
[FPEnv] Expand constrained FP POWI Modify ExpandStrictFPOp(...) to handle nodes that have scalar operands. Also, add a Strict FMA test and do some other light cleanup in the Strict FP code. Differential Revision: https://reviews.llvm.org/D48149 llvm-svn: 334863
2018-06-16 04:57:55 +08:00
; HAS-FMA-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
; HAS-FMA-NEXT: callq sin
[FPEnv] Expand constrained FP POWI Modify ExpandStrictFPOp(...) to handle nodes that have scalar operands. Also, add a Strict FMA test and do some other light cleanup in the Strict FP code. Differential Revision: https://reviews.llvm.org/D48149 llvm-svn: 334863
2018-06-16 04:57:55 +08:00
; HAS-FMA-NEXT: vunpcklpd (%rsp), %xmm0, %xmm0 # 16-byte Folded Reload
; HAS-FMA-NEXT: # xmm0 = xmm0[0],mem[0]
; HAS-FMA-NEXT: addq $24, %rsp
; HAS-FMA-NEXT: .cfi_def_cfa_offset 8
; HAS-FMA-NEXT: retq
[FPEnv] Expand constrained FP operations Add a helper function to expand constrained FP operations as needed. Note that the Strict POWI operation is not handled in this patch since the format is slightly different from the others. Differential Revision: https://reviews.llvm.org/D47491 llvm-svn: 334603
2018-06-13 22:32:12 +08:00
entry:
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
%sin = call <2 x double> @llvm.experimental.constrained.sin.v2f64(
[FPEnv] Expand constrained FP operations Add a helper function to expand constrained FP operations as needed. Note that the Strict POWI operation is not handled in this patch since the format is slightly different from the others. Differential Revision: https://reviews.llvm.org/D47491 llvm-svn: 334603
2018-06-13 22:32:12 +08:00
<2 x double> <double 42.0, double 42.1>,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
ret <2 x double> %sin
[FPEnv] Expand constrained FP operations Add a helper function to expand constrained FP operations as needed. Note that the Strict POWI operation is not handled in this patch since the format is slightly different from the others. Differential Revision: https://reviews.llvm.org/D47491 llvm-svn: 334603
2018-06-13 22:32:12 +08:00
}
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
define <3 x float> @constrained_vector_sin_v3f32() {
; NO-FMA-LABEL: constrained_vector_sin_v3f32:
; NO-FMA: # %bb.0: # %entry
; NO-FMA-NEXT: subq $40, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 48
; NO-FMA-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; NO-FMA-NEXT: callq sinf
; NO-FMA-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; NO-FMA-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; NO-FMA-NEXT: callq sinf
; NO-FMA-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; NO-FMA-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; NO-FMA-NEXT: callq sinf
; NO-FMA-NEXT: movaps (%rsp), %xmm1 # 16-byte Reload
; NO-FMA-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; NO-FMA-NEXT: unpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload
; NO-FMA-NEXT: # xmm1 = xmm1[0],mem[0]
; NO-FMA-NEXT: movaps %xmm1, %xmm0
; NO-FMA-NEXT: addq $40, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 8
; NO-FMA-NEXT: retq
;
; HAS-FMA-LABEL: constrained_vector_sin_v3f32:
; HAS-FMA: # %bb.0: # %entry
; HAS-FMA-NEXT: subq $40, %rsp
; HAS-FMA-NEXT: .cfi_def_cfa_offset 48
; HAS-FMA-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; HAS-FMA-NEXT: callq sinf
; HAS-FMA-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; HAS-FMA-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; HAS-FMA-NEXT: callq sinf
; HAS-FMA-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
; HAS-FMA-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; HAS-FMA-NEXT: callq sinf
; HAS-FMA-NEXT: vmovaps (%rsp), %xmm1 # 16-byte Reload
; HAS-FMA-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[2,3]
; HAS-FMA-NEXT: vinsertps $32, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm0 # 16-byte Folded Reload
; HAS-FMA-NEXT: # xmm0 = xmm0[0,1],mem[0],xmm0[3]
; HAS-FMA-NEXT: addq $40, %rsp
; HAS-FMA-NEXT: .cfi_def_cfa_offset 8
; HAS-FMA-NEXT: retq
entry:
%sin = call <3 x float> @llvm.experimental.constrained.sin.v3f32(
<3 x float> <float 42.0, float 43.0, float 44.0>,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <3 x float> %sin
}
define <3 x double> @constrained_vector_sin_v3f64() {
; NO-FMA-LABEL: constrained_vector_sin_v3f64:
; NO-FMA: # %bb.0: # %entry
[X86] Add initial SimplifyDemandedVectorEltsForTargetNode support This patch adds an initial x86 SimplifyDemandedVectorEltsForTargetNode implementation to handle target shuffles. Currently the patch only decodes a target shuffle, calls SimplifyDemandedVectorElts on its input operands and removes any shuffle that reduces to undef/zero/identity. Future work will need to integrate this with combineX86ShufflesRecursively, add support for other x86 ops, etc. NOTE: There is a minor regression that appears to be affecting further (extractelement?) combines which I haven't been able to solve yet - possibly something to do with how nodes are added to the worklist after simplification. Differential Revision: https://reviews.llvm.org/D52140 llvm-svn: 342564
2018-09-20 02:11:34 +08:00
; NO-FMA-NEXT: subq $24, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 32
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: callq sin
[X86] Add initial SimplifyDemandedVectorEltsForTargetNode support This patch adds an initial x86 SimplifyDemandedVectorEltsForTargetNode implementation to handle target shuffles. Currently the patch only decodes a target shuffle, calls SimplifyDemandedVectorElts on its input operands and removes any shuffle that reduces to undef/zero/identity. Future work will need to integrate this with combineX86ShufflesRecursively, add support for other x86 ops, etc. NOTE: There is a minor regression that appears to be affecting further (extractelement?) combines which I haven't been able to solve yet - possibly something to do with how nodes are added to the worklist after simplification. Differential Revision: https://reviews.llvm.org/D52140 llvm-svn: 342564
2018-09-20 02:11:34 +08:00
; NO-FMA-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: callq sin
[X86] Add initial SimplifyDemandedVectorEltsForTargetNode support This patch adds an initial x86 SimplifyDemandedVectorEltsForTargetNode implementation to handle target shuffles. Currently the patch only decodes a target shuffle, calls SimplifyDemandedVectorElts on its input operands and removes any shuffle that reduces to undef/zero/identity. Future work will need to integrate this with combineX86ShufflesRecursively, add support for other x86 ops, etc. NOTE: There is a minor regression that appears to be affecting further (extractelement?) combines which I haven't been able to solve yet - possibly something to do with how nodes are added to the worklist after simplification. Differential Revision: https://reviews.llvm.org/D52140 llvm-svn: 342564
2018-09-20 02:11:34 +08:00
; NO-FMA-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: callq sin
; NO-FMA-NEXT: movsd %xmm0, {{[0-9]+}}(%rsp)
; NO-FMA-NEXT: fldl {{[0-9]+}}(%rsp)
[X86] Add initial SimplifyDemandedVectorEltsForTargetNode support This patch adds an initial x86 SimplifyDemandedVectorEltsForTargetNode implementation to handle target shuffles. Currently the patch only decodes a target shuffle, calls SimplifyDemandedVectorElts on its input operands and removes any shuffle that reduces to undef/zero/identity. Future work will need to integrate this with combineX86ShufflesRecursively, add support for other x86 ops, etc. NOTE: There is a minor regression that appears to be affecting further (extractelement?) combines which I haven't been able to solve yet - possibly something to do with how nodes are added to the worklist after simplification. Differential Revision: https://reviews.llvm.org/D52140 llvm-svn: 342564
2018-09-20 02:11:34 +08:00
; NO-FMA-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload
; NO-FMA-NEXT: # xmm0 = mem[0],zero
; NO-FMA-NEXT: movsd (%rsp), %xmm1 # 8-byte Reload
; NO-FMA-NEXT: # xmm1 = mem[0],zero
; NO-FMA-NEXT: addq $24, %rsp
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
; NO-FMA-NEXT: .cfi_def_cfa_offset 8
; NO-FMA-NEXT: retq
;
; HAS-FMA-LABEL: constrained_vector_sin_v3f64:
; HAS-FMA: # %bb.0: # %entry
; HAS-FMA-NEXT: subq $56, %rsp
; HAS-FMA-NEXT: .cfi_def_cfa_offset 64
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: callq sin
; HAS-FMA-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: callq sin
; HAS-FMA-NEXT: vunpcklpd (%rsp), %xmm0, %xmm0 # 16-byte Folded Reload
; HAS-FMA-NEXT: # xmm0 = xmm0[0],mem[0]
; HAS-FMA-NEXT: vmovups %ymm0, (%rsp) # 32-byte Spill
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: vzeroupper
; HAS-FMA-NEXT: callq sin
; HAS-FMA-NEXT: vmovups (%rsp), %ymm1 # 32-byte Reload
; HAS-FMA-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; HAS-FMA-NEXT: addq $56, %rsp
; HAS-FMA-NEXT: .cfi_def_cfa_offset 8
; HAS-FMA-NEXT: retq
entry:
%sin = call <3 x double> @llvm.experimental.constrained.sin.v3f64(
<3 x double> <double 42.0, double 42.1, double 42.2>,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <3 x double> %sin
}
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
define <4 x double> @constrained_vector_sin_v4f64() {
; NO-FMA-LABEL: constrained_vector_sin_v4f64:
[FPEnv] Expand constrained FP POWI Modify ExpandStrictFPOp(...) to handle nodes that have scalar operands. Also, add a Strict FMA test and do some other light cleanup in the Strict FP code. Differential Revision: https://reviews.llvm.org/D48149 llvm-svn: 334863
2018-06-16 04:57:55 +08:00
; NO-FMA: # %bb.0: # %entry
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
; NO-FMA-NEXT: subq $40, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 48
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: callq sin
; NO-FMA-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: callq sin
; NO-FMA-NEXT: unpcklpd (%rsp), %xmm0 # 16-byte Folded Reload
; NO-FMA-NEXT: # xmm0 = xmm0[0],mem[0]
; NO-FMA-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: callq sin
; NO-FMA-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: callq sin
; NO-FMA-NEXT: movaps %xmm0, %xmm1
; NO-FMA-NEXT: unpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload
; NO-FMA-NEXT: # xmm1 = xmm1[0],mem[0]
; NO-FMA-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; NO-FMA-NEXT: addq $40, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 8
; NO-FMA-NEXT: retq
;
; HAS-FMA-LABEL: constrained_vector_sin_v4f64:
; HAS-FMA: # %bb.0: # %entry
; HAS-FMA-NEXT: subq $40, %rsp
; HAS-FMA-NEXT: .cfi_def_cfa_offset 48
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: callq sin
; HAS-FMA-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: callq sin
; HAS-FMA-NEXT: vunpcklpd (%rsp), %xmm0, %xmm0 # 16-byte Folded Reload
; HAS-FMA-NEXT: # xmm0 = xmm0[0],mem[0]
; HAS-FMA-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: callq sin
; HAS-FMA-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: callq sin
; HAS-FMA-NEXT: vunpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm0 # 16-byte Folded Reload
; HAS-FMA-NEXT: # xmm0 = xmm0[0],mem[0]
; HAS-FMA-NEXT: vinsertf128 $1, (%rsp), %ymm0, %ymm0 # 16-byte Folded Reload
; HAS-FMA-NEXT: addq $40, %rsp
; HAS-FMA-NEXT: .cfi_def_cfa_offset 8
; HAS-FMA-NEXT: retq
entry:
%sin = call <4 x double> @llvm.experimental.constrained.sin.v4f64(
<4 x double> <double 42.0, double 42.1,
double 42.2, double 42.3>,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <4 x double> %sin
}
[FPEnv] Scalarize StrictFP vector operations Add a helper function to scalarize constrained FP operations as needed. Differential Revision: https://reviews.llvm.org/D50720 llvm-svn: 339735
2018-08-15 06:13:11 +08:00
define <1 x float> @constrained_vector_cos_v1f32() {
; NO-FMA-LABEL: constrained_vector_cos_v1f32:
; NO-FMA: # %bb.0: # %entry
; NO-FMA-NEXT: pushq %rax
; NO-FMA-NEXT: .cfi_def_cfa_offset 16
; NO-FMA-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; NO-FMA-NEXT: callq cosf
; NO-FMA-NEXT: popq %rax
; NO-FMA-NEXT: .cfi_def_cfa_offset 8
; NO-FMA-NEXT: retq
;
; HAS-FMA-LABEL: constrained_vector_cos_v1f32:
; HAS-FMA: # %bb.0: # %entry
; HAS-FMA-NEXT: pushq %rax
; HAS-FMA-NEXT: .cfi_def_cfa_offset 16
; HAS-FMA-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; HAS-FMA-NEXT: callq cosf
; HAS-FMA-NEXT: popq %rax
; HAS-FMA-NEXT: .cfi_def_cfa_offset 8
; HAS-FMA-NEXT: retq
entry:
%cos = call <1 x float> @llvm.experimental.constrained.cos.v1f32(
<1 x float> <float 42.0>,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <1 x float> %cos
}
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
define <2 x double> @constrained_vector_cos_v2f64() {
; NO-FMA-LABEL: constrained_vector_cos_v2f64:
; NO-FMA: # %bb.0: # %entry
; NO-FMA-NEXT: subq $24, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 32
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: callq cos
; NO-FMA-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: callq cos
; NO-FMA-NEXT: unpcklpd (%rsp), %xmm0 # 16-byte Folded Reload
; NO-FMA-NEXT: # xmm0 = xmm0[0],mem[0]
; NO-FMA-NEXT: addq $24, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 8
; NO-FMA-NEXT: retq
;
; HAS-FMA-LABEL: constrained_vector_cos_v2f64:
; HAS-FMA: # %bb.0: # %entry
; HAS-FMA-NEXT: subq $24, %rsp
; HAS-FMA-NEXT: .cfi_def_cfa_offset 32
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: callq cos
; HAS-FMA-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: callq cos
; HAS-FMA-NEXT: vunpcklpd (%rsp), %xmm0, %xmm0 # 16-byte Folded Reload
; HAS-FMA-NEXT: # xmm0 = xmm0[0],mem[0]
; HAS-FMA-NEXT: addq $24, %rsp
; HAS-FMA-NEXT: .cfi_def_cfa_offset 8
; HAS-FMA-NEXT: retq
entry:
%cos = call <2 x double> @llvm.experimental.constrained.cos.v2f64(
<2 x double> <double 42.0, double 42.1>,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <2 x double> %cos
}
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
define <3 x float> @constrained_vector_cos_v3f32() {
; NO-FMA-LABEL: constrained_vector_cos_v3f32:
; NO-FMA: # %bb.0: # %entry
; NO-FMA-NEXT: subq $40, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 48
; NO-FMA-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; NO-FMA-NEXT: callq cosf
; NO-FMA-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; NO-FMA-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; NO-FMA-NEXT: callq cosf
; NO-FMA-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; NO-FMA-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; NO-FMA-NEXT: callq cosf
; NO-FMA-NEXT: movaps (%rsp), %xmm1 # 16-byte Reload
; NO-FMA-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; NO-FMA-NEXT: unpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload
; NO-FMA-NEXT: # xmm1 = xmm1[0],mem[0]
; NO-FMA-NEXT: movaps %xmm1, %xmm0
; NO-FMA-NEXT: addq $40, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 8
; NO-FMA-NEXT: retq
;
; HAS-FMA-LABEL: constrained_vector_cos_v3f32:
; HAS-FMA: # %bb.0: # %entry
; HAS-FMA-NEXT: subq $40, %rsp
; HAS-FMA-NEXT: .cfi_def_cfa_offset 48
; HAS-FMA-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; HAS-FMA-NEXT: callq cosf
; HAS-FMA-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; HAS-FMA-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; HAS-FMA-NEXT: callq cosf
; HAS-FMA-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
; HAS-FMA-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; HAS-FMA-NEXT: callq cosf
; HAS-FMA-NEXT: vmovaps (%rsp), %xmm1 # 16-byte Reload
; HAS-FMA-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[2,3]
; HAS-FMA-NEXT: vinsertps $32, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm0 # 16-byte Folded Reload
; HAS-FMA-NEXT: # xmm0 = xmm0[0,1],mem[0],xmm0[3]
; HAS-FMA-NEXT: addq $40, %rsp
; HAS-FMA-NEXT: .cfi_def_cfa_offset 8
; HAS-FMA-NEXT: retq
entry:
%cos = call <3 x float> @llvm.experimental.constrained.cos.v3f32(
<3 x float> <float 42.0, float 43.0, float 44.0>,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <3 x float> %cos
}
define <3 x double> @constrained_vector_cos_v3f64() {
; NO-FMA-LABEL: constrained_vector_cos_v3f64:
; NO-FMA: # %bb.0: # %entry
[X86] Add initial SimplifyDemandedVectorEltsForTargetNode support This patch adds an initial x86 SimplifyDemandedVectorEltsForTargetNode implementation to handle target shuffles. Currently the patch only decodes a target shuffle, calls SimplifyDemandedVectorElts on its input operands and removes any shuffle that reduces to undef/zero/identity. Future work will need to integrate this with combineX86ShufflesRecursively, add support for other x86 ops, etc. NOTE: There is a minor regression that appears to be affecting further (extractelement?) combines which I haven't been able to solve yet - possibly something to do with how nodes are added to the worklist after simplification. Differential Revision: https://reviews.llvm.org/D52140 llvm-svn: 342564
2018-09-20 02:11:34 +08:00
; NO-FMA-NEXT: subq $24, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 32
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: callq cos
[X86] Add initial SimplifyDemandedVectorEltsForTargetNode support This patch adds an initial x86 SimplifyDemandedVectorEltsForTargetNode implementation to handle target shuffles. Currently the patch only decodes a target shuffle, calls SimplifyDemandedVectorElts on its input operands and removes any shuffle that reduces to undef/zero/identity. Future work will need to integrate this with combineX86ShufflesRecursively, add support for other x86 ops, etc. NOTE: There is a minor regression that appears to be affecting further (extractelement?) combines which I haven't been able to solve yet - possibly something to do with how nodes are added to the worklist after simplification. Differential Revision: https://reviews.llvm.org/D52140 llvm-svn: 342564
2018-09-20 02:11:34 +08:00
; NO-FMA-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: callq cos
[X86] Add initial SimplifyDemandedVectorEltsForTargetNode support This patch adds an initial x86 SimplifyDemandedVectorEltsForTargetNode implementation to handle target shuffles. Currently the patch only decodes a target shuffle, calls SimplifyDemandedVectorElts on its input operands and removes any shuffle that reduces to undef/zero/identity. Future work will need to integrate this with combineX86ShufflesRecursively, add support for other x86 ops, etc. NOTE: There is a minor regression that appears to be affecting further (extractelement?) combines which I haven't been able to solve yet - possibly something to do with how nodes are added to the worklist after simplification. Differential Revision: https://reviews.llvm.org/D52140 llvm-svn: 342564
2018-09-20 02:11:34 +08:00
; NO-FMA-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: callq cos
; NO-FMA-NEXT: movsd %xmm0, {{[0-9]+}}(%rsp)
; NO-FMA-NEXT: fldl {{[0-9]+}}(%rsp)
[X86] Add initial SimplifyDemandedVectorEltsForTargetNode support This patch adds an initial x86 SimplifyDemandedVectorEltsForTargetNode implementation to handle target shuffles. Currently the patch only decodes a target shuffle, calls SimplifyDemandedVectorElts on its input operands and removes any shuffle that reduces to undef/zero/identity. Future work will need to integrate this with combineX86ShufflesRecursively, add support for other x86 ops, etc. NOTE: There is a minor regression that appears to be affecting further (extractelement?) combines which I haven't been able to solve yet - possibly something to do with how nodes are added to the worklist after simplification. Differential Revision: https://reviews.llvm.org/D52140 llvm-svn: 342564
2018-09-20 02:11:34 +08:00
; NO-FMA-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload
; NO-FMA-NEXT: # xmm0 = mem[0],zero
; NO-FMA-NEXT: movsd (%rsp), %xmm1 # 8-byte Reload
; NO-FMA-NEXT: # xmm1 = mem[0],zero
; NO-FMA-NEXT: addq $24, %rsp
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
; NO-FMA-NEXT: .cfi_def_cfa_offset 8
; NO-FMA-NEXT: retq
;
; HAS-FMA-LABEL: constrained_vector_cos_v3f64:
; HAS-FMA: # %bb.0: # %entry
; HAS-FMA-NEXT: subq $56, %rsp
; HAS-FMA-NEXT: .cfi_def_cfa_offset 64
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: callq cos
; HAS-FMA-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: callq cos
; HAS-FMA-NEXT: vunpcklpd (%rsp), %xmm0, %xmm0 # 16-byte Folded Reload
; HAS-FMA-NEXT: # xmm0 = xmm0[0],mem[0]
; HAS-FMA-NEXT: vmovups %ymm0, (%rsp) # 32-byte Spill
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: vzeroupper
; HAS-FMA-NEXT: callq cos
; HAS-FMA-NEXT: vmovups (%rsp), %ymm1 # 32-byte Reload
; HAS-FMA-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; HAS-FMA-NEXT: addq $56, %rsp
; HAS-FMA-NEXT: .cfi_def_cfa_offset 8
; HAS-FMA-NEXT: retq
entry:
%cos = call <3 x double> @llvm.experimental.constrained.cos.v3f64(
<3 x double> <double 42.0, double 42.1, double 42.2>,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <3 x double> %cos
}
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
define <4 x double> @constrained_vector_cos_v4f64() {
; NO-FMA-LABEL: constrained_vector_cos_v4f64:
; NO-FMA: # %bb.0: # %entry
; NO-FMA-NEXT: subq $40, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 48
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: callq cos
; NO-FMA-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: callq cos
; NO-FMA-NEXT: unpcklpd (%rsp), %xmm0 # 16-byte Folded Reload
; NO-FMA-NEXT: # xmm0 = xmm0[0],mem[0]
; NO-FMA-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: callq cos
; NO-FMA-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: callq cos
; NO-FMA-NEXT: movaps %xmm0, %xmm1
; NO-FMA-NEXT: unpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload
; NO-FMA-NEXT: # xmm1 = xmm1[0],mem[0]
; NO-FMA-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; NO-FMA-NEXT: addq $40, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 8
; NO-FMA-NEXT: retq
;
; HAS-FMA-LABEL: constrained_vector_cos_v4f64:
; HAS-FMA: # %bb.0: # %entry
; HAS-FMA-NEXT: subq $40, %rsp
; HAS-FMA-NEXT: .cfi_def_cfa_offset 48
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: callq cos
; HAS-FMA-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: callq cos
; HAS-FMA-NEXT: vunpcklpd (%rsp), %xmm0, %xmm0 # 16-byte Folded Reload
; HAS-FMA-NEXT: # xmm0 = xmm0[0],mem[0]
; HAS-FMA-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: callq cos
; HAS-FMA-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: callq cos
; HAS-FMA-NEXT: vunpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm0 # 16-byte Folded Reload
; HAS-FMA-NEXT: # xmm0 = xmm0[0],mem[0]
; HAS-FMA-NEXT: vinsertf128 $1, (%rsp), %ymm0, %ymm0 # 16-byte Folded Reload
; HAS-FMA-NEXT: addq $40, %rsp
; HAS-FMA-NEXT: .cfi_def_cfa_offset 8
; HAS-FMA-NEXT: retq
entry:
%cos = call <4 x double> @llvm.experimental.constrained.cos.v4f64(
<4 x double> <double 42.0, double 42.1,
double 42.2, double 42.3>,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <4 x double> %cos
}
[FPEnv] Scalarize StrictFP vector operations Add a helper function to scalarize constrained FP operations as needed. Differential Revision: https://reviews.llvm.org/D50720 llvm-svn: 339735
2018-08-15 06:13:11 +08:00
define <1 x float> @constrained_vector_exp_v1f32() {
; NO-FMA-LABEL: constrained_vector_exp_v1f32:
; NO-FMA: # %bb.0: # %entry
; NO-FMA-NEXT: pushq %rax
; NO-FMA-NEXT: .cfi_def_cfa_offset 16
; NO-FMA-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; NO-FMA-NEXT: callq expf
; NO-FMA-NEXT: popq %rax
; NO-FMA-NEXT: .cfi_def_cfa_offset 8
; NO-FMA-NEXT: retq
;
; HAS-FMA-LABEL: constrained_vector_exp_v1f32:
; HAS-FMA: # %bb.0: # %entry
; HAS-FMA-NEXT: pushq %rax
; HAS-FMA-NEXT: .cfi_def_cfa_offset 16
; HAS-FMA-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; HAS-FMA-NEXT: callq expf
; HAS-FMA-NEXT: popq %rax
; HAS-FMA-NEXT: .cfi_def_cfa_offset 8
; HAS-FMA-NEXT: retq
entry:
%exp = call <1 x float> @llvm.experimental.constrained.exp.v1f32(
<1 x float> <float 42.0>,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <1 x float> %exp
}
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
define <2 x double> @constrained_vector_exp_v2f64() {
; NO-FMA-LABEL: constrained_vector_exp_v2f64:
; NO-FMA: # %bb.0: # %entry
; NO-FMA-NEXT: subq $24, %rsp
[FPEnv] Expand constrained FP POWI Modify ExpandStrictFPOp(...) to handle nodes that have scalar operands. Also, add a Strict FMA test and do some other light cleanup in the Strict FP code. Differential Revision: https://reviews.llvm.org/D48149 llvm-svn: 334863
2018-06-16 04:57:55 +08:00
; NO-FMA-NEXT: .cfi_def_cfa_offset 32
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: callq exp
; NO-FMA-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: callq exp
; NO-FMA-NEXT: unpcklpd (%rsp), %xmm0 # 16-byte Folded Reload
; NO-FMA-NEXT: # xmm0 = xmm0[0],mem[0]
; NO-FMA-NEXT: addq $24, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 8
; NO-FMA-NEXT: retq
;
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
; HAS-FMA-LABEL: constrained_vector_exp_v2f64:
[FPEnv] Expand constrained FP POWI Modify ExpandStrictFPOp(...) to handle nodes that have scalar operands. Also, add a Strict FMA test and do some other light cleanup in the Strict FP code. Differential Revision: https://reviews.llvm.org/D48149 llvm-svn: 334863
2018-06-16 04:57:55 +08:00
; HAS-FMA: # %bb.0: # %entry
; HAS-FMA-NEXT: subq $24, %rsp
; HAS-FMA-NEXT: .cfi_def_cfa_offset 32
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: callq exp
; HAS-FMA-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: callq exp
; HAS-FMA-NEXT: vunpcklpd (%rsp), %xmm0, %xmm0 # 16-byte Folded Reload
; HAS-FMA-NEXT: # xmm0 = xmm0[0],mem[0]
; HAS-FMA-NEXT: addq $24, %rsp
; HAS-FMA-NEXT: .cfi_def_cfa_offset 8
; HAS-FMA-NEXT: retq
[FPEnv] Expand constrained FP operations Add a helper function to expand constrained FP operations as needed. Note that the Strict POWI operation is not handled in this patch since the format is slightly different from the others. Differential Revision: https://reviews.llvm.org/D47491 llvm-svn: 334603
2018-06-13 22:32:12 +08:00
entry:
%exp = call <2 x double> @llvm.experimental.constrained.exp.v2f64(
<2 x double> <double 42.0, double 42.1>,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <2 x double> %exp
}
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
define <3 x float> @constrained_vector_exp_v3f32() {
; NO-FMA-LABEL: constrained_vector_exp_v3f32:
; NO-FMA: # %bb.0: # %entry
; NO-FMA-NEXT: subq $40, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 48
; NO-FMA-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; NO-FMA-NEXT: callq expf
; NO-FMA-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; NO-FMA-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; NO-FMA-NEXT: callq expf
; NO-FMA-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; NO-FMA-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; NO-FMA-NEXT: callq expf
; NO-FMA-NEXT: movaps (%rsp), %xmm1 # 16-byte Reload
; NO-FMA-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; NO-FMA-NEXT: unpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload
; NO-FMA-NEXT: # xmm1 = xmm1[0],mem[0]
; NO-FMA-NEXT: movaps %xmm1, %xmm0
; NO-FMA-NEXT: addq $40, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 8
; NO-FMA-NEXT: retq
;
; HAS-FMA-LABEL: constrained_vector_exp_v3f32:
; HAS-FMA: # %bb.0: # %entry
; HAS-FMA-NEXT: subq $40, %rsp
; HAS-FMA-NEXT: .cfi_def_cfa_offset 48
; HAS-FMA-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; HAS-FMA-NEXT: callq expf
; HAS-FMA-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; HAS-FMA-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; HAS-FMA-NEXT: callq expf
; HAS-FMA-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
; HAS-FMA-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; HAS-FMA-NEXT: callq expf
; HAS-FMA-NEXT: vmovaps (%rsp), %xmm1 # 16-byte Reload
; HAS-FMA-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[2,3]
; HAS-FMA-NEXT: vinsertps $32, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm0 # 16-byte Folded Reload
; HAS-FMA-NEXT: # xmm0 = xmm0[0,1],mem[0],xmm0[3]
; HAS-FMA-NEXT: addq $40, %rsp
; HAS-FMA-NEXT: .cfi_def_cfa_offset 8
; HAS-FMA-NEXT: retq
entry:
%exp = call <3 x float> @llvm.experimental.constrained.exp.v3f32(
<3 x float> <float 42.0, float 43.0, float 44.0>,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <3 x float> %exp
}
define <3 x double> @constrained_vector_exp_v3f64() {
; NO-FMA-LABEL: constrained_vector_exp_v3f64:
; NO-FMA: # %bb.0: # %entry
[X86] Add initial SimplifyDemandedVectorEltsForTargetNode support This patch adds an initial x86 SimplifyDemandedVectorEltsForTargetNode implementation to handle target shuffles. Currently the patch only decodes a target shuffle, calls SimplifyDemandedVectorElts on its input operands and removes any shuffle that reduces to undef/zero/identity. Future work will need to integrate this with combineX86ShufflesRecursively, add support for other x86 ops, etc. NOTE: There is a minor regression that appears to be affecting further (extractelement?) combines which I haven't been able to solve yet - possibly something to do with how nodes are added to the worklist after simplification. Differential Revision: https://reviews.llvm.org/D52140 llvm-svn: 342564
2018-09-20 02:11:34 +08:00
; NO-FMA-NEXT: subq $24, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 32
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: callq exp
[X86] Add initial SimplifyDemandedVectorEltsForTargetNode support This patch adds an initial x86 SimplifyDemandedVectorEltsForTargetNode implementation to handle target shuffles. Currently the patch only decodes a target shuffle, calls SimplifyDemandedVectorElts on its input operands and removes any shuffle that reduces to undef/zero/identity. Future work will need to integrate this with combineX86ShufflesRecursively, add support for other x86 ops, etc. NOTE: There is a minor regression that appears to be affecting further (extractelement?) combines which I haven't been able to solve yet - possibly something to do with how nodes are added to the worklist after simplification. Differential Revision: https://reviews.llvm.org/D52140 llvm-svn: 342564
2018-09-20 02:11:34 +08:00
; NO-FMA-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: callq exp
[X86] Add initial SimplifyDemandedVectorEltsForTargetNode support This patch adds an initial x86 SimplifyDemandedVectorEltsForTargetNode implementation to handle target shuffles. Currently the patch only decodes a target shuffle, calls SimplifyDemandedVectorElts on its input operands and removes any shuffle that reduces to undef/zero/identity. Future work will need to integrate this with combineX86ShufflesRecursively, add support for other x86 ops, etc. NOTE: There is a minor regression that appears to be affecting further (extractelement?) combines which I haven't been able to solve yet - possibly something to do with how nodes are added to the worklist after simplification. Differential Revision: https://reviews.llvm.org/D52140 llvm-svn: 342564
2018-09-20 02:11:34 +08:00
; NO-FMA-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: callq exp
; NO-FMA-NEXT: movsd %xmm0, {{[0-9]+}}(%rsp)
; NO-FMA-NEXT: fldl {{[0-9]+}}(%rsp)
[X86] Add initial SimplifyDemandedVectorEltsForTargetNode support This patch adds an initial x86 SimplifyDemandedVectorEltsForTargetNode implementation to handle target shuffles. Currently the patch only decodes a target shuffle, calls SimplifyDemandedVectorElts on its input operands and removes any shuffle that reduces to undef/zero/identity. Future work will need to integrate this with combineX86ShufflesRecursively, add support for other x86 ops, etc. NOTE: There is a minor regression that appears to be affecting further (extractelement?) combines which I haven't been able to solve yet - possibly something to do with how nodes are added to the worklist after simplification. Differential Revision: https://reviews.llvm.org/D52140 llvm-svn: 342564
2018-09-20 02:11:34 +08:00
; NO-FMA-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload
; NO-FMA-NEXT: # xmm0 = mem[0],zero
; NO-FMA-NEXT: movsd (%rsp), %xmm1 # 8-byte Reload
; NO-FMA-NEXT: # xmm1 = mem[0],zero
; NO-FMA-NEXT: addq $24, %rsp
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
; NO-FMA-NEXT: .cfi_def_cfa_offset 8
; NO-FMA-NEXT: retq
;
; HAS-FMA-LABEL: constrained_vector_exp_v3f64:
; HAS-FMA: # %bb.0: # %entry
; HAS-FMA-NEXT: subq $56, %rsp
; HAS-FMA-NEXT: .cfi_def_cfa_offset 64
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: callq exp
; HAS-FMA-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: callq exp
; HAS-FMA-NEXT: vunpcklpd (%rsp), %xmm0, %xmm0 # 16-byte Folded Reload
; HAS-FMA-NEXT: # xmm0 = xmm0[0],mem[0]
; HAS-FMA-NEXT: vmovups %ymm0, (%rsp) # 32-byte Spill
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: vzeroupper
; HAS-FMA-NEXT: callq exp
; HAS-FMA-NEXT: vmovups (%rsp), %ymm1 # 32-byte Reload
; HAS-FMA-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; HAS-FMA-NEXT: addq $56, %rsp
; HAS-FMA-NEXT: .cfi_def_cfa_offset 8
; HAS-FMA-NEXT: retq
entry:
%exp = call <3 x double> @llvm.experimental.constrained.exp.v3f64(
<3 x double> <double 42.0, double 42.1, double 42.2>,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <3 x double> %exp
}
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
define <4 x double> @constrained_vector_exp_v4f64() {
; NO-FMA-LABEL: constrained_vector_exp_v4f64:
; NO-FMA: # %bb.0: # %entry
; NO-FMA-NEXT: subq $40, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 48
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: callq exp
; NO-FMA-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: callq exp
; NO-FMA-NEXT: unpcklpd (%rsp), %xmm0 # 16-byte Folded Reload
; NO-FMA-NEXT: # xmm0 = xmm0[0],mem[0]
; NO-FMA-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: callq exp
; NO-FMA-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: callq exp
; NO-FMA-NEXT: movaps %xmm0, %xmm1
; NO-FMA-NEXT: unpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload
; NO-FMA-NEXT: # xmm1 = xmm1[0],mem[0]
; NO-FMA-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; NO-FMA-NEXT: addq $40, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 8
; NO-FMA-NEXT: retq
;
; HAS-FMA-LABEL: constrained_vector_exp_v4f64:
; HAS-FMA: # %bb.0: # %entry
; HAS-FMA-NEXT: subq $40, %rsp
; HAS-FMA-NEXT: .cfi_def_cfa_offset 48
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: callq exp
; HAS-FMA-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: callq exp
; HAS-FMA-NEXT: vunpcklpd (%rsp), %xmm0, %xmm0 # 16-byte Folded Reload
; HAS-FMA-NEXT: # xmm0 = xmm0[0],mem[0]
; HAS-FMA-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: callq exp
; HAS-FMA-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: callq exp
; HAS-FMA-NEXT: vunpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm0 # 16-byte Folded Reload
; HAS-FMA-NEXT: # xmm0 = xmm0[0],mem[0]
; HAS-FMA-NEXT: vinsertf128 $1, (%rsp), %ymm0, %ymm0 # 16-byte Folded Reload
; HAS-FMA-NEXT: addq $40, %rsp
; HAS-FMA-NEXT: .cfi_def_cfa_offset 8
; HAS-FMA-NEXT: retq
entry:
%exp = call <4 x double> @llvm.experimental.constrained.exp.v4f64(
<4 x double> <double 42.0, double 42.1,
double 42.2, double 42.3>,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <4 x double> %exp
}
[FPEnv] Scalarize StrictFP vector operations Add a helper function to scalarize constrained FP operations as needed. Differential Revision: https://reviews.llvm.org/D50720 llvm-svn: 339735
2018-08-15 06:13:11 +08:00
define <1 x float> @constrained_vector_exp2_v1f32() {
; NO-FMA-LABEL: constrained_vector_exp2_v1f32:
; NO-FMA: # %bb.0: # %entry
; NO-FMA-NEXT: pushq %rax
; NO-FMA-NEXT: .cfi_def_cfa_offset 16
; NO-FMA-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; NO-FMA-NEXT: callq exp2f
; NO-FMA-NEXT: popq %rax
; NO-FMA-NEXT: .cfi_def_cfa_offset 8
; NO-FMA-NEXT: retq
;
; HAS-FMA-LABEL: constrained_vector_exp2_v1f32:
; HAS-FMA: # %bb.0: # %entry
; HAS-FMA-NEXT: pushq %rax
; HAS-FMA-NEXT: .cfi_def_cfa_offset 16
; HAS-FMA-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; HAS-FMA-NEXT: callq exp2f
; HAS-FMA-NEXT: popq %rax
; HAS-FMA-NEXT: .cfi_def_cfa_offset 8
; HAS-FMA-NEXT: retq
entry:
%exp2 = call <1 x float> @llvm.experimental.constrained.exp2.v1f32(
<1 x float> <float 42.0>,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <1 x float> %exp2
}
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
define <2 x double> @constrained_vector_exp2_v2f64() {
; NO-FMA-LABEL: constrained_vector_exp2_v2f64:
[FPEnv] Expand constrained FP POWI Modify ExpandStrictFPOp(...) to handle nodes that have scalar operands. Also, add a Strict FMA test and do some other light cleanup in the Strict FP code. Differential Revision: https://reviews.llvm.org/D48149 llvm-svn: 334863
2018-06-16 04:57:55 +08:00
; NO-FMA: # %bb.0: # %entry
; NO-FMA-NEXT: subq $24, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 32
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: callq exp2
; NO-FMA-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: callq exp2
; NO-FMA-NEXT: unpcklpd (%rsp), %xmm0 # 16-byte Folded Reload
; NO-FMA-NEXT: # xmm0 = xmm0[0],mem[0]
; NO-FMA-NEXT: addq $24, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 8
; NO-FMA-NEXT: retq
;
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
; HAS-FMA-LABEL: constrained_vector_exp2_v2f64:
[FPEnv] Expand constrained FP POWI Modify ExpandStrictFPOp(...) to handle nodes that have scalar operands. Also, add a Strict FMA test and do some other light cleanup in the Strict FP code. Differential Revision: https://reviews.llvm.org/D48149 llvm-svn: 334863
2018-06-16 04:57:55 +08:00
; HAS-FMA: # %bb.0: # %entry
; HAS-FMA-NEXT: subq $24, %rsp
; HAS-FMA-NEXT: .cfi_def_cfa_offset 32
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: callq exp2
; HAS-FMA-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: callq exp2
; HAS-FMA-NEXT: vunpcklpd (%rsp), %xmm0, %xmm0 # 16-byte Folded Reload
; HAS-FMA-NEXT: # xmm0 = xmm0[0],mem[0]
; HAS-FMA-NEXT: addq $24, %rsp
; HAS-FMA-NEXT: .cfi_def_cfa_offset 8
; HAS-FMA-NEXT: retq
[FPEnv] Expand constrained FP operations Add a helper function to expand constrained FP operations as needed. Note that the Strict POWI operation is not handled in this patch since the format is slightly different from the others. Differential Revision: https://reviews.llvm.org/D47491 llvm-svn: 334603
2018-06-13 22:32:12 +08:00
entry:
%exp2 = call <2 x double> @llvm.experimental.constrained.exp2.v2f64(
<2 x double> <double 42.1, double 42.0>,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <2 x double> %exp2
}
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
define <3 x float> @constrained_vector_exp2_v3f32() {
; NO-FMA-LABEL: constrained_vector_exp2_v3f32:
; NO-FMA: # %bb.0: # %entry
; NO-FMA-NEXT: subq $40, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 48
; NO-FMA-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; NO-FMA-NEXT: callq exp2f
; NO-FMA-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; NO-FMA-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; NO-FMA-NEXT: callq exp2f
; NO-FMA-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; NO-FMA-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; NO-FMA-NEXT: callq exp2f
; NO-FMA-NEXT: movaps (%rsp), %xmm1 # 16-byte Reload
; NO-FMA-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; NO-FMA-NEXT: unpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload
; NO-FMA-NEXT: # xmm1 = xmm1[0],mem[0]
; NO-FMA-NEXT: movaps %xmm1, %xmm0
; NO-FMA-NEXT: addq $40, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 8
; NO-FMA-NEXT: retq
;
; HAS-FMA-LABEL: constrained_vector_exp2_v3f32:
; HAS-FMA: # %bb.0: # %entry
; HAS-FMA-NEXT: subq $40, %rsp
; HAS-FMA-NEXT: .cfi_def_cfa_offset 48
; HAS-FMA-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; HAS-FMA-NEXT: callq exp2f
; HAS-FMA-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; HAS-FMA-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; HAS-FMA-NEXT: callq exp2f
; HAS-FMA-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
; HAS-FMA-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; HAS-FMA-NEXT: callq exp2f
; HAS-FMA-NEXT: vmovaps (%rsp), %xmm1 # 16-byte Reload
; HAS-FMA-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[2,3]
; HAS-FMA-NEXT: vinsertps $32, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm0 # 16-byte Folded Reload
; HAS-FMA-NEXT: # xmm0 = xmm0[0,1],mem[0],xmm0[3]
; HAS-FMA-NEXT: addq $40, %rsp
; HAS-FMA-NEXT: .cfi_def_cfa_offset 8
; HAS-FMA-NEXT: retq
entry:
%exp2 = call <3 x float> @llvm.experimental.constrained.exp2.v3f32(
<3 x float> <float 42.0, float 43.0, float 44.0>,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <3 x float> %exp2
}
define <3 x double> @constrained_vector_exp2_v3f64() {
; NO-FMA-LABEL: constrained_vector_exp2_v3f64:
; NO-FMA: # %bb.0: # %entry
[X86] Add initial SimplifyDemandedVectorEltsForTargetNode support This patch adds an initial x86 SimplifyDemandedVectorEltsForTargetNode implementation to handle target shuffles. Currently the patch only decodes a target shuffle, calls SimplifyDemandedVectorElts on its input operands and removes any shuffle that reduces to undef/zero/identity. Future work will need to integrate this with combineX86ShufflesRecursively, add support for other x86 ops, etc. NOTE: There is a minor regression that appears to be affecting further (extractelement?) combines which I haven't been able to solve yet - possibly something to do with how nodes are added to the worklist after simplification. Differential Revision: https://reviews.llvm.org/D52140 llvm-svn: 342564
2018-09-20 02:11:34 +08:00
; NO-FMA-NEXT: subq $24, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 32
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: callq exp2
[X86] Add initial SimplifyDemandedVectorEltsForTargetNode support This patch adds an initial x86 SimplifyDemandedVectorEltsForTargetNode implementation to handle target shuffles. Currently the patch only decodes a target shuffle, calls SimplifyDemandedVectorElts on its input operands and removes any shuffle that reduces to undef/zero/identity. Future work will need to integrate this with combineX86ShufflesRecursively, add support for other x86 ops, etc. NOTE: There is a minor regression that appears to be affecting further (extractelement?) combines which I haven't been able to solve yet - possibly something to do with how nodes are added to the worklist after simplification. Differential Revision: https://reviews.llvm.org/D52140 llvm-svn: 342564
2018-09-20 02:11:34 +08:00
; NO-FMA-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: callq exp2
[X86] Add initial SimplifyDemandedVectorEltsForTargetNode support This patch adds an initial x86 SimplifyDemandedVectorEltsForTargetNode implementation to handle target shuffles. Currently the patch only decodes a target shuffle, calls SimplifyDemandedVectorElts on its input operands and removes any shuffle that reduces to undef/zero/identity. Future work will need to integrate this with combineX86ShufflesRecursively, add support for other x86 ops, etc. NOTE: There is a minor regression that appears to be affecting further (extractelement?) combines which I haven't been able to solve yet - possibly something to do with how nodes are added to the worklist after simplification. Differential Revision: https://reviews.llvm.org/D52140 llvm-svn: 342564
2018-09-20 02:11:34 +08:00
; NO-FMA-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: callq exp2
; NO-FMA-NEXT: movsd %xmm0, {{[0-9]+}}(%rsp)
; NO-FMA-NEXT: fldl {{[0-9]+}}(%rsp)
[X86] Add initial SimplifyDemandedVectorEltsForTargetNode support This patch adds an initial x86 SimplifyDemandedVectorEltsForTargetNode implementation to handle target shuffles. Currently the patch only decodes a target shuffle, calls SimplifyDemandedVectorElts on its input operands and removes any shuffle that reduces to undef/zero/identity. Future work will need to integrate this with combineX86ShufflesRecursively, add support for other x86 ops, etc. NOTE: There is a minor regression that appears to be affecting further (extractelement?) combines which I haven't been able to solve yet - possibly something to do with how nodes are added to the worklist after simplification. Differential Revision: https://reviews.llvm.org/D52140 llvm-svn: 342564
2018-09-20 02:11:34 +08:00
; NO-FMA-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload
; NO-FMA-NEXT: # xmm0 = mem[0],zero
; NO-FMA-NEXT: movsd (%rsp), %xmm1 # 8-byte Reload
; NO-FMA-NEXT: # xmm1 = mem[0],zero
; NO-FMA-NEXT: addq $24, %rsp
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
; NO-FMA-NEXT: .cfi_def_cfa_offset 8
; NO-FMA-NEXT: retq
;
; HAS-FMA-LABEL: constrained_vector_exp2_v3f64:
; HAS-FMA: # %bb.0: # %entry
; HAS-FMA-NEXT: subq $56, %rsp
; HAS-FMA-NEXT: .cfi_def_cfa_offset 64
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: callq exp2
; HAS-FMA-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: callq exp2
; HAS-FMA-NEXT: vunpcklpd (%rsp), %xmm0, %xmm0 # 16-byte Folded Reload
; HAS-FMA-NEXT: # xmm0 = xmm0[0],mem[0]
; HAS-FMA-NEXT: vmovups %ymm0, (%rsp) # 32-byte Spill
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: vzeroupper
; HAS-FMA-NEXT: callq exp2
; HAS-FMA-NEXT: vmovups (%rsp), %ymm1 # 32-byte Reload
; HAS-FMA-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; HAS-FMA-NEXT: addq $56, %rsp
; HAS-FMA-NEXT: .cfi_def_cfa_offset 8
; HAS-FMA-NEXT: retq
entry:
%exp2 = call <3 x double> @llvm.experimental.constrained.exp2.v3f64(
<3 x double> <double 42.0, double 42.1, double 42.2>,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <3 x double> %exp2
}
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
define <4 x double> @constrained_vector_exp2_v4f64() {
; NO-FMA-LABEL: constrained_vector_exp2_v4f64:
; NO-FMA: # %bb.0: # %entry
; NO-FMA-NEXT: subq $40, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 48
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: callq exp2
; NO-FMA-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: callq exp2
; NO-FMA-NEXT: unpcklpd (%rsp), %xmm0 # 16-byte Folded Reload
; NO-FMA-NEXT: # xmm0 = xmm0[0],mem[0]
; NO-FMA-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: callq exp2
; NO-FMA-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: callq exp2
; NO-FMA-NEXT: movaps %xmm0, %xmm1
; NO-FMA-NEXT: unpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload
; NO-FMA-NEXT: # xmm1 = xmm1[0],mem[0]
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
; NO-FMA-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; NO-FMA-NEXT: addq $40, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 8
; NO-FMA-NEXT: retq
;
; HAS-FMA-LABEL: constrained_vector_exp2_v4f64:
; HAS-FMA: # %bb.0: # %entry
; HAS-FMA-NEXT: subq $40, %rsp
; HAS-FMA-NEXT: .cfi_def_cfa_offset 48
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: callq exp2
; HAS-FMA-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: callq exp2
; HAS-FMA-NEXT: vunpcklpd (%rsp), %xmm0, %xmm0 # 16-byte Folded Reload
; HAS-FMA-NEXT: # xmm0 = xmm0[0],mem[0]
; HAS-FMA-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: callq exp2
; HAS-FMA-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: callq exp2
; HAS-FMA-NEXT: vunpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm0 # 16-byte Folded Reload
; HAS-FMA-NEXT: # xmm0 = xmm0[0],mem[0]
; HAS-FMA-NEXT: vinsertf128 $1, (%rsp), %ymm0, %ymm0 # 16-byte Folded Reload
; HAS-FMA-NEXT: addq $40, %rsp
; HAS-FMA-NEXT: .cfi_def_cfa_offset 8
; HAS-FMA-NEXT: retq
entry:
%exp2 = call <4 x double> @llvm.experimental.constrained.exp2.v4f64(
<4 x double> <double 42.1, double 42.2,
double 42.3, double 42.4>,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <4 x double> %exp2
}
[FPEnv] Scalarize StrictFP vector operations Add a helper function to scalarize constrained FP operations as needed. Differential Revision: https://reviews.llvm.org/D50720 llvm-svn: 339735
2018-08-15 06:13:11 +08:00
define <1 x float> @constrained_vector_log_v1f32() {
; NO-FMA-LABEL: constrained_vector_log_v1f32:
; NO-FMA: # %bb.0: # %entry
; NO-FMA-NEXT: pushq %rax
; NO-FMA-NEXT: .cfi_def_cfa_offset 16
; NO-FMA-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; NO-FMA-NEXT: callq logf
; NO-FMA-NEXT: popq %rax
; NO-FMA-NEXT: .cfi_def_cfa_offset 8
; NO-FMA-NEXT: retq
;
; HAS-FMA-LABEL: constrained_vector_log_v1f32:
; HAS-FMA: # %bb.0: # %entry
; HAS-FMA-NEXT: pushq %rax
; HAS-FMA-NEXT: .cfi_def_cfa_offset 16
; HAS-FMA-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; HAS-FMA-NEXT: callq logf
; HAS-FMA-NEXT: popq %rax
; HAS-FMA-NEXT: .cfi_def_cfa_offset 8
; HAS-FMA-NEXT: retq
entry:
%log = call <1 x float> @llvm.experimental.constrained.log.v1f32(
<1 x float> <float 42.0>,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <1 x float> %log
}
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
define <2 x double> @constrained_vector_log_v2f64() {
; NO-FMA-LABEL: constrained_vector_log_v2f64:
; NO-FMA: # %bb.0: # %entry
; NO-FMA-NEXT: subq $24, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 32
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: callq log
; NO-FMA-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: callq log
; NO-FMA-NEXT: unpcklpd (%rsp), %xmm0 # 16-byte Folded Reload
; NO-FMA-NEXT: # xmm0 = xmm0[0],mem[0]
; NO-FMA-NEXT: addq $24, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 8
; NO-FMA-NEXT: retq
;
; HAS-FMA-LABEL: constrained_vector_log_v2f64:
; HAS-FMA: # %bb.0: # %entry
; HAS-FMA-NEXT: subq $24, %rsp
; HAS-FMA-NEXT: .cfi_def_cfa_offset 32
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: callq log
; HAS-FMA-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: callq log
; HAS-FMA-NEXT: vunpcklpd (%rsp), %xmm0, %xmm0 # 16-byte Folded Reload
; HAS-FMA-NEXT: # xmm0 = xmm0[0],mem[0]
; HAS-FMA-NEXT: addq $24, %rsp
; HAS-FMA-NEXT: .cfi_def_cfa_offset 8
; HAS-FMA-NEXT: retq
entry:
%log = call <2 x double> @llvm.experimental.constrained.log.v2f64(
<2 x double> <double 42.0, double 42.1>,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <2 x double> %log
}
define <3 x float> @constrained_vector_log_v3f32() {
; NO-FMA-LABEL: constrained_vector_log_v3f32:
; NO-FMA: # %bb.0: # %entry
; NO-FMA-NEXT: subq $40, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 48
; NO-FMA-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; NO-FMA-NEXT: callq logf
; NO-FMA-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; NO-FMA-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; NO-FMA-NEXT: callq logf
; NO-FMA-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; NO-FMA-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; NO-FMA-NEXT: callq logf
; NO-FMA-NEXT: movaps (%rsp), %xmm1 # 16-byte Reload
; NO-FMA-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; NO-FMA-NEXT: unpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload
; NO-FMA-NEXT: # xmm1 = xmm1[0],mem[0]
; NO-FMA-NEXT: movaps %xmm1, %xmm0
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
; NO-FMA-NEXT: addq $40, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 8
; NO-FMA-NEXT: retq
;
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
; HAS-FMA-LABEL: constrained_vector_log_v3f32:
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
; HAS-FMA: # %bb.0: # %entry
; HAS-FMA-NEXT: subq $40, %rsp
; HAS-FMA-NEXT: .cfi_def_cfa_offset 48
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
; HAS-FMA-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; HAS-FMA-NEXT: callq logf
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
; HAS-FMA-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
; HAS-FMA-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; HAS-FMA-NEXT: callq logf
; HAS-FMA-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
; HAS-FMA-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; HAS-FMA-NEXT: callq logf
; HAS-FMA-NEXT: vmovaps (%rsp), %xmm1 # 16-byte Reload
; HAS-FMA-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[2,3]
; HAS-FMA-NEXT: vinsertps $32, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm0 # 16-byte Folded Reload
; HAS-FMA-NEXT: # xmm0 = xmm0[0,1],mem[0],xmm0[3]
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
; HAS-FMA-NEXT: addq $40, %rsp
; HAS-FMA-NEXT: .cfi_def_cfa_offset 8
; HAS-FMA-NEXT: retq
entry:
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
%log = call <3 x float> @llvm.experimental.constrained.log.v3f32(
<3 x float> <float 42.0, float 43.0, float 44.0>,
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
metadata !"round.dynamic",
metadata !"fpexcept.strict")
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
ret <3 x float> %log
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
}
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
define <3 x double> @constrained_vector_log_v3f64() {
; NO-FMA-LABEL: constrained_vector_log_v3f64:
[FPEnv] Expand constrained FP POWI Modify ExpandStrictFPOp(...) to handle nodes that have scalar operands. Also, add a Strict FMA test and do some other light cleanup in the Strict FP code. Differential Revision: https://reviews.llvm.org/D48149 llvm-svn: 334863
2018-06-16 04:57:55 +08:00
; NO-FMA: # %bb.0: # %entry
[X86] Add initial SimplifyDemandedVectorEltsForTargetNode support This patch adds an initial x86 SimplifyDemandedVectorEltsForTargetNode implementation to handle target shuffles. Currently the patch only decodes a target shuffle, calls SimplifyDemandedVectorElts on its input operands and removes any shuffle that reduces to undef/zero/identity. Future work will need to integrate this with combineX86ShufflesRecursively, add support for other x86 ops, etc. NOTE: There is a minor regression that appears to be affecting further (extractelement?) combines which I haven't been able to solve yet - possibly something to do with how nodes are added to the worklist after simplification. Differential Revision: https://reviews.llvm.org/D52140 llvm-svn: 342564
2018-09-20 02:11:34 +08:00
; NO-FMA-NEXT: subq $24, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 32
[FPEnv] Expand constrained FP POWI Modify ExpandStrictFPOp(...) to handle nodes that have scalar operands. Also, add a Strict FMA test and do some other light cleanup in the Strict FP code. Differential Revision: https://reviews.llvm.org/D48149 llvm-svn: 334863
2018-06-16 04:57:55 +08:00
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: callq log
[X86] Add initial SimplifyDemandedVectorEltsForTargetNode support This patch adds an initial x86 SimplifyDemandedVectorEltsForTargetNode implementation to handle target shuffles. Currently the patch only decodes a target shuffle, calls SimplifyDemandedVectorElts on its input operands and removes any shuffle that reduces to undef/zero/identity. Future work will need to integrate this with combineX86ShufflesRecursively, add support for other x86 ops, etc. NOTE: There is a minor regression that appears to be affecting further (extractelement?) combines which I haven't been able to solve yet - possibly something to do with how nodes are added to the worklist after simplification. Differential Revision: https://reviews.llvm.org/D52140 llvm-svn: 342564
2018-09-20 02:11:34 +08:00
; NO-FMA-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
[FPEnv] Expand constrained FP POWI Modify ExpandStrictFPOp(...) to handle nodes that have scalar operands. Also, add a Strict FMA test and do some other light cleanup in the Strict FP code. Differential Revision: https://reviews.llvm.org/D48149 llvm-svn: 334863
2018-06-16 04:57:55 +08:00
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: callq log
[X86] Add initial SimplifyDemandedVectorEltsForTargetNode support This patch adds an initial x86 SimplifyDemandedVectorEltsForTargetNode implementation to handle target shuffles. Currently the patch only decodes a target shuffle, calls SimplifyDemandedVectorElts on its input operands and removes any shuffle that reduces to undef/zero/identity. Future work will need to integrate this with combineX86ShufflesRecursively, add support for other x86 ops, etc. NOTE: There is a minor regression that appears to be affecting further (extractelement?) combines which I haven't been able to solve yet - possibly something to do with how nodes are added to the worklist after simplification. Differential Revision: https://reviews.llvm.org/D52140 llvm-svn: 342564
2018-09-20 02:11:34 +08:00
; NO-FMA-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: callq log
; NO-FMA-NEXT: movsd %xmm0, {{[0-9]+}}(%rsp)
; NO-FMA-NEXT: fldl {{[0-9]+}}(%rsp)
[X86] Add initial SimplifyDemandedVectorEltsForTargetNode support This patch adds an initial x86 SimplifyDemandedVectorEltsForTargetNode implementation to handle target shuffles. Currently the patch only decodes a target shuffle, calls SimplifyDemandedVectorElts on its input operands and removes any shuffle that reduces to undef/zero/identity. Future work will need to integrate this with combineX86ShufflesRecursively, add support for other x86 ops, etc. NOTE: There is a minor regression that appears to be affecting further (extractelement?) combines which I haven't been able to solve yet - possibly something to do with how nodes are added to the worklist after simplification. Differential Revision: https://reviews.llvm.org/D52140 llvm-svn: 342564
2018-09-20 02:11:34 +08:00
; NO-FMA-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload
; NO-FMA-NEXT: # xmm0 = mem[0],zero
; NO-FMA-NEXT: movsd (%rsp), %xmm1 # 8-byte Reload
; NO-FMA-NEXT: # xmm1 = mem[0],zero
; NO-FMA-NEXT: addq $24, %rsp
[FPEnv] Expand constrained FP POWI Modify ExpandStrictFPOp(...) to handle nodes that have scalar operands. Also, add a Strict FMA test and do some other light cleanup in the Strict FP code. Differential Revision: https://reviews.llvm.org/D48149 llvm-svn: 334863
2018-06-16 04:57:55 +08:00
; NO-FMA-NEXT: .cfi_def_cfa_offset 8
; NO-FMA-NEXT: retq
;
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
; HAS-FMA-LABEL: constrained_vector_log_v3f64:
[FPEnv] Expand constrained FP POWI Modify ExpandStrictFPOp(...) to handle nodes that have scalar operands. Also, add a Strict FMA test and do some other light cleanup in the Strict FP code. Differential Revision: https://reviews.llvm.org/D48149 llvm-svn: 334863
2018-06-16 04:57:55 +08:00
; HAS-FMA: # %bb.0: # %entry
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
; HAS-FMA-NEXT: subq $56, %rsp
; HAS-FMA-NEXT: .cfi_def_cfa_offset 64
[FPEnv] Expand constrained FP POWI Modify ExpandStrictFPOp(...) to handle nodes that have scalar operands. Also, add a Strict FMA test and do some other light cleanup in the Strict FP code. Differential Revision: https://reviews.llvm.org/D48149 llvm-svn: 334863
2018-06-16 04:57:55 +08:00
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: callq log
; HAS-FMA-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: callq log
; HAS-FMA-NEXT: vunpcklpd (%rsp), %xmm0, %xmm0 # 16-byte Folded Reload
; HAS-FMA-NEXT: # xmm0 = xmm0[0],mem[0]
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
; HAS-FMA-NEXT: vmovups %ymm0, (%rsp) # 32-byte Spill
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: vzeroupper
; HAS-FMA-NEXT: callq log
; HAS-FMA-NEXT: vmovups (%rsp), %ymm1 # 32-byte Reload
; HAS-FMA-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; HAS-FMA-NEXT: addq $56, %rsp
[FPEnv] Expand constrained FP POWI Modify ExpandStrictFPOp(...) to handle nodes that have scalar operands. Also, add a Strict FMA test and do some other light cleanup in the Strict FP code. Differential Revision: https://reviews.llvm.org/D48149 llvm-svn: 334863
2018-06-16 04:57:55 +08:00
; HAS-FMA-NEXT: .cfi_def_cfa_offset 8
; HAS-FMA-NEXT: retq
[FPEnv] Expand constrained FP operations Add a helper function to expand constrained FP operations as needed. Note that the Strict POWI operation is not handled in this patch since the format is slightly different from the others. Differential Revision: https://reviews.llvm.org/D47491 llvm-svn: 334603
2018-06-13 22:32:12 +08:00
entry:
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
%log = call <3 x double> @llvm.experimental.constrained.log.v3f64(
<3 x double> <double 42.0, double 42.1, double 42.2>,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <3 x double> %log
[FPEnv] Expand constrained FP operations Add a helper function to expand constrained FP operations as needed. Note that the Strict POWI operation is not handled in this patch since the format is slightly different from the others. Differential Revision: https://reviews.llvm.org/D47491 llvm-svn: 334603
2018-06-13 22:32:12 +08:00
}
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
define <4 x double> @constrained_vector_log_v4f64() {
; NO-FMA-LABEL: constrained_vector_log_v4f64:
; NO-FMA: # %bb.0: # %entry
; NO-FMA-NEXT: subq $40, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 48
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: callq log
; NO-FMA-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: callq log
; NO-FMA-NEXT: unpcklpd (%rsp), %xmm0 # 16-byte Folded Reload
; NO-FMA-NEXT: # xmm0 = xmm0[0],mem[0]
; NO-FMA-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: callq log
; NO-FMA-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: callq log
; NO-FMA-NEXT: movaps %xmm0, %xmm1
; NO-FMA-NEXT: unpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload
; NO-FMA-NEXT: # xmm1 = xmm1[0],mem[0]
; NO-FMA-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; NO-FMA-NEXT: addq $40, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 8
; NO-FMA-NEXT: retq
;
; HAS-FMA-LABEL: constrained_vector_log_v4f64:
; HAS-FMA: # %bb.0: # %entry
; HAS-FMA-NEXT: subq $40, %rsp
; HAS-FMA-NEXT: .cfi_def_cfa_offset 48
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: callq log
; HAS-FMA-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: callq log
; HAS-FMA-NEXT: vunpcklpd (%rsp), %xmm0, %xmm0 # 16-byte Folded Reload
; HAS-FMA-NEXT: # xmm0 = xmm0[0],mem[0]
; HAS-FMA-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: callq log
; HAS-FMA-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: callq log
; HAS-FMA-NEXT: vunpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm0 # 16-byte Folded Reload
; HAS-FMA-NEXT: # xmm0 = xmm0[0],mem[0]
; HAS-FMA-NEXT: vinsertf128 $1, (%rsp), %ymm0, %ymm0 # 16-byte Folded Reload
; HAS-FMA-NEXT: addq $40, %rsp
; HAS-FMA-NEXT: .cfi_def_cfa_offset 8
; HAS-FMA-NEXT: retq
entry:
%log = call <4 x double> @llvm.experimental.constrained.log.v4f64(
<4 x double> <double 42.0, double 42.1,
double 42.2, double 42.3>,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <4 x double> %log
}
[FPEnv] Scalarize StrictFP vector operations Add a helper function to scalarize constrained FP operations as needed. Differential Revision: https://reviews.llvm.org/D50720 llvm-svn: 339735
2018-08-15 06:13:11 +08:00
define <1 x float> @constrained_vector_log10_v1f32() {
; NO-FMA-LABEL: constrained_vector_log10_v1f32:
; NO-FMA: # %bb.0: # %entry
; NO-FMA-NEXT: pushq %rax
; NO-FMA-NEXT: .cfi_def_cfa_offset 16
; NO-FMA-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; NO-FMA-NEXT: callq log10f
; NO-FMA-NEXT: popq %rax
; NO-FMA-NEXT: .cfi_def_cfa_offset 8
; NO-FMA-NEXT: retq
;
; HAS-FMA-LABEL: constrained_vector_log10_v1f32:
; HAS-FMA: # %bb.0: # %entry
; HAS-FMA-NEXT: pushq %rax
; HAS-FMA-NEXT: .cfi_def_cfa_offset 16
; HAS-FMA-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; HAS-FMA-NEXT: callq log10f
; HAS-FMA-NEXT: popq %rax
; HAS-FMA-NEXT: .cfi_def_cfa_offset 8
; HAS-FMA-NEXT: retq
entry:
%log10 = call <1 x float> @llvm.experimental.constrained.log10.v1f32(
<1 x float> <float 42.0>,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <1 x float> %log10
}
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
define <2 x double> @constrained_vector_log10_v2f64() {
; NO-FMA-LABEL: constrained_vector_log10_v2f64:
[FPEnv] Expand constrained FP POWI Modify ExpandStrictFPOp(...) to handle nodes that have scalar operands. Also, add a Strict FMA test and do some other light cleanup in the Strict FP code. Differential Revision: https://reviews.llvm.org/D48149 llvm-svn: 334863
2018-06-16 04:57:55 +08:00
; NO-FMA: # %bb.0: # %entry
; NO-FMA-NEXT: subq $24, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 32
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: callq log10
; NO-FMA-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: callq log10
; NO-FMA-NEXT: unpcklpd (%rsp), %xmm0 # 16-byte Folded Reload
; NO-FMA-NEXT: # xmm0 = xmm0[0],mem[0]
; NO-FMA-NEXT: addq $24, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 8
; NO-FMA-NEXT: retq
;
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
; HAS-FMA-LABEL: constrained_vector_log10_v2f64:
[FPEnv] Expand constrained FP POWI Modify ExpandStrictFPOp(...) to handle nodes that have scalar operands. Also, add a Strict FMA test and do some other light cleanup in the Strict FP code. Differential Revision: https://reviews.llvm.org/D48149 llvm-svn: 334863
2018-06-16 04:57:55 +08:00
; HAS-FMA: # %bb.0: # %entry
; HAS-FMA-NEXT: subq $24, %rsp
; HAS-FMA-NEXT: .cfi_def_cfa_offset 32
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: callq log10
; HAS-FMA-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: callq log10
; HAS-FMA-NEXT: vunpcklpd (%rsp), %xmm0, %xmm0 # 16-byte Folded Reload
; HAS-FMA-NEXT: # xmm0 = xmm0[0],mem[0]
; HAS-FMA-NEXT: addq $24, %rsp
; HAS-FMA-NEXT: .cfi_def_cfa_offset 8
; HAS-FMA-NEXT: retq
[FPEnv] Expand constrained FP operations Add a helper function to expand constrained FP operations as needed. Note that the Strict POWI operation is not handled in this patch since the format is slightly different from the others. Differential Revision: https://reviews.llvm.org/D47491 llvm-svn: 334603
2018-06-13 22:32:12 +08:00
entry:
%log10 = call <2 x double> @llvm.experimental.constrained.log10.v2f64(
<2 x double> <double 42.0, double 42.1>,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <2 x double> %log10
}
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
define <3 x float> @constrained_vector_log10_v3f32() {
; NO-FMA-LABEL: constrained_vector_log10_v3f32:
; NO-FMA: # %bb.0: # %entry
; NO-FMA-NEXT: subq $40, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 48
; NO-FMA-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; NO-FMA-NEXT: callq log10f
; NO-FMA-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; NO-FMA-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; NO-FMA-NEXT: callq log10f
; NO-FMA-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; NO-FMA-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; NO-FMA-NEXT: callq log10f
; NO-FMA-NEXT: movaps (%rsp), %xmm1 # 16-byte Reload
; NO-FMA-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; NO-FMA-NEXT: unpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload
; NO-FMA-NEXT: # xmm1 = xmm1[0],mem[0]
; NO-FMA-NEXT: movaps %xmm1, %xmm0
; NO-FMA-NEXT: addq $40, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 8
; NO-FMA-NEXT: retq
;
; HAS-FMA-LABEL: constrained_vector_log10_v3f32:
; HAS-FMA: # %bb.0: # %entry
; HAS-FMA-NEXT: subq $40, %rsp
; HAS-FMA-NEXT: .cfi_def_cfa_offset 48
; HAS-FMA-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; HAS-FMA-NEXT: callq log10f
; HAS-FMA-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; HAS-FMA-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; HAS-FMA-NEXT: callq log10f
; HAS-FMA-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
; HAS-FMA-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; HAS-FMA-NEXT: callq log10f
; HAS-FMA-NEXT: vmovaps (%rsp), %xmm1 # 16-byte Reload
; HAS-FMA-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[2,3]
; HAS-FMA-NEXT: vinsertps $32, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm0 # 16-byte Folded Reload
; HAS-FMA-NEXT: # xmm0 = xmm0[0,1],mem[0],xmm0[3]
; HAS-FMA-NEXT: addq $40, %rsp
; HAS-FMA-NEXT: .cfi_def_cfa_offset 8
; HAS-FMA-NEXT: retq
entry:
%log10 = call <3 x float> @llvm.experimental.constrained.log10.v3f32(
<3 x float> <float 42.0, float 43.0, float 44.0>,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <3 x float> %log10
}
define <3 x double> @constrained_vector_log10_v3f64() {
; NO-FMA-LABEL: constrained_vector_log10_v3f64:
; NO-FMA: # %bb.0: # %entry
[X86] Add initial SimplifyDemandedVectorEltsForTargetNode support This patch adds an initial x86 SimplifyDemandedVectorEltsForTargetNode implementation to handle target shuffles. Currently the patch only decodes a target shuffle, calls SimplifyDemandedVectorElts on its input operands and removes any shuffle that reduces to undef/zero/identity. Future work will need to integrate this with combineX86ShufflesRecursively, add support for other x86 ops, etc. NOTE: There is a minor regression that appears to be affecting further (extractelement?) combines which I haven't been able to solve yet - possibly something to do with how nodes are added to the worklist after simplification. Differential Revision: https://reviews.llvm.org/D52140 llvm-svn: 342564
2018-09-20 02:11:34 +08:00
; NO-FMA-NEXT: subq $24, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 32
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: callq log10
[X86] Add initial SimplifyDemandedVectorEltsForTargetNode support This patch adds an initial x86 SimplifyDemandedVectorEltsForTargetNode implementation to handle target shuffles. Currently the patch only decodes a target shuffle, calls SimplifyDemandedVectorElts on its input operands and removes any shuffle that reduces to undef/zero/identity. Future work will need to integrate this with combineX86ShufflesRecursively, add support for other x86 ops, etc. NOTE: There is a minor regression that appears to be affecting further (extractelement?) combines which I haven't been able to solve yet - possibly something to do with how nodes are added to the worklist after simplification. Differential Revision: https://reviews.llvm.org/D52140 llvm-svn: 342564
2018-09-20 02:11:34 +08:00
; NO-FMA-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: callq log10
[X86] Add initial SimplifyDemandedVectorEltsForTargetNode support This patch adds an initial x86 SimplifyDemandedVectorEltsForTargetNode implementation to handle target shuffles. Currently the patch only decodes a target shuffle, calls SimplifyDemandedVectorElts on its input operands and removes any shuffle that reduces to undef/zero/identity. Future work will need to integrate this with combineX86ShufflesRecursively, add support for other x86 ops, etc. NOTE: There is a minor regression that appears to be affecting further (extractelement?) combines which I haven't been able to solve yet - possibly something to do with how nodes are added to the worklist after simplification. Differential Revision: https://reviews.llvm.org/D52140 llvm-svn: 342564
2018-09-20 02:11:34 +08:00
; NO-FMA-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: callq log10
; NO-FMA-NEXT: movsd %xmm0, {{[0-9]+}}(%rsp)
; NO-FMA-NEXT: fldl {{[0-9]+}}(%rsp)
[X86] Add initial SimplifyDemandedVectorEltsForTargetNode support This patch adds an initial x86 SimplifyDemandedVectorEltsForTargetNode implementation to handle target shuffles. Currently the patch only decodes a target shuffle, calls SimplifyDemandedVectorElts on its input operands and removes any shuffle that reduces to undef/zero/identity. Future work will need to integrate this with combineX86ShufflesRecursively, add support for other x86 ops, etc. NOTE: There is a minor regression that appears to be affecting further (extractelement?) combines which I haven't been able to solve yet - possibly something to do with how nodes are added to the worklist after simplification. Differential Revision: https://reviews.llvm.org/D52140 llvm-svn: 342564
2018-09-20 02:11:34 +08:00
; NO-FMA-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload
; NO-FMA-NEXT: # xmm0 = mem[0],zero
; NO-FMA-NEXT: movsd (%rsp), %xmm1 # 8-byte Reload
; NO-FMA-NEXT: # xmm1 = mem[0],zero
; NO-FMA-NEXT: addq $24, %rsp
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
; NO-FMA-NEXT: .cfi_def_cfa_offset 8
; NO-FMA-NEXT: retq
;
; HAS-FMA-LABEL: constrained_vector_log10_v3f64:
; HAS-FMA: # %bb.0: # %entry
; HAS-FMA-NEXT: subq $56, %rsp
; HAS-FMA-NEXT: .cfi_def_cfa_offset 64
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: callq log10
; HAS-FMA-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: callq log10
; HAS-FMA-NEXT: vunpcklpd (%rsp), %xmm0, %xmm0 # 16-byte Folded Reload
; HAS-FMA-NEXT: # xmm0 = xmm0[0],mem[0]
; HAS-FMA-NEXT: vmovups %ymm0, (%rsp) # 32-byte Spill
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: vzeroupper
; HAS-FMA-NEXT: callq log10
; HAS-FMA-NEXT: vmovups (%rsp), %ymm1 # 32-byte Reload
; HAS-FMA-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; HAS-FMA-NEXT: addq $56, %rsp
; HAS-FMA-NEXT: .cfi_def_cfa_offset 8
; HAS-FMA-NEXT: retq
entry:
%log10 = call <3 x double> @llvm.experimental.constrained.log10.v3f64(
<3 x double> <double 42.0, double 42.1, double 42.2>,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <3 x double> %log10
}
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
define <4 x double> @constrained_vector_log10_v4f64() {
; NO-FMA-LABEL: constrained_vector_log10_v4f64:
; NO-FMA: # %bb.0: # %entry
; NO-FMA-NEXT: subq $40, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 48
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: callq log10
; NO-FMA-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: callq log10
; NO-FMA-NEXT: unpcklpd (%rsp), %xmm0 # 16-byte Folded Reload
; NO-FMA-NEXT: # xmm0 = xmm0[0],mem[0]
; NO-FMA-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: callq log10
; NO-FMA-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: callq log10
; NO-FMA-NEXT: movaps %xmm0, %xmm1
; NO-FMA-NEXT: unpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload
; NO-FMA-NEXT: # xmm1 = xmm1[0],mem[0]
; NO-FMA-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; NO-FMA-NEXT: addq $40, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 8
; NO-FMA-NEXT: retq
;
; HAS-FMA-LABEL: constrained_vector_log10_v4f64:
; HAS-FMA: # %bb.0: # %entry
; HAS-FMA-NEXT: subq $40, %rsp
; HAS-FMA-NEXT: .cfi_def_cfa_offset 48
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: callq log10
; HAS-FMA-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: callq log10
; HAS-FMA-NEXT: vunpcklpd (%rsp), %xmm0, %xmm0 # 16-byte Folded Reload
; HAS-FMA-NEXT: # xmm0 = xmm0[0],mem[0]
; HAS-FMA-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: callq log10
; HAS-FMA-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: callq log10
; HAS-FMA-NEXT: vunpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm0 # 16-byte Folded Reload
; HAS-FMA-NEXT: # xmm0 = xmm0[0],mem[0]
; HAS-FMA-NEXT: vinsertf128 $1, (%rsp), %ymm0, %ymm0 # 16-byte Folded Reload
; HAS-FMA-NEXT: addq $40, %rsp
; HAS-FMA-NEXT: .cfi_def_cfa_offset 8
; HAS-FMA-NEXT: retq
entry:
%log10 = call <4 x double> @llvm.experimental.constrained.log10.v4f64(
<4 x double> <double 42.0, double 42.1,
double 42.2, double 42.3>,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <4 x double> %log10
}
[FPEnv] Scalarize StrictFP vector operations Add a helper function to scalarize constrained FP operations as needed. Differential Revision: https://reviews.llvm.org/D50720 llvm-svn: 339735
2018-08-15 06:13:11 +08:00
define <1 x float> @constrained_vector_log2_v1f32() {
; NO-FMA-LABEL: constrained_vector_log2_v1f32:
; NO-FMA: # %bb.0: # %entry
; NO-FMA-NEXT: pushq %rax
; NO-FMA-NEXT: .cfi_def_cfa_offset 16
; NO-FMA-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; NO-FMA-NEXT: callq log2f
; NO-FMA-NEXT: popq %rax
; NO-FMA-NEXT: .cfi_def_cfa_offset 8
; NO-FMA-NEXT: retq
;
; HAS-FMA-LABEL: constrained_vector_log2_v1f32:
; HAS-FMA: # %bb.0: # %entry
; HAS-FMA-NEXT: pushq %rax
; HAS-FMA-NEXT: .cfi_def_cfa_offset 16
; HAS-FMA-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; HAS-FMA-NEXT: callq log2f
; HAS-FMA-NEXT: popq %rax
; HAS-FMA-NEXT: .cfi_def_cfa_offset 8
; HAS-FMA-NEXT: retq
entry:
%log2 = call <1 x float> @llvm.experimental.constrained.log2.v1f32(
<1 x float> <float 42.0>,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <1 x float> %log2
}
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
define <2 x double> @constrained_vector_log2_v2f64() {
; NO-FMA-LABEL: constrained_vector_log2_v2f64:
[FPEnv] Expand constrained FP POWI Modify ExpandStrictFPOp(...) to handle nodes that have scalar operands. Also, add a Strict FMA test and do some other light cleanup in the Strict FP code. Differential Revision: https://reviews.llvm.org/D48149 llvm-svn: 334863
2018-06-16 04:57:55 +08:00
; NO-FMA: # %bb.0: # %entry
; NO-FMA-NEXT: subq $24, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 32
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: callq log2
; NO-FMA-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: callq log2
; NO-FMA-NEXT: unpcklpd (%rsp), %xmm0 # 16-byte Folded Reload
; NO-FMA-NEXT: # xmm0 = xmm0[0],mem[0]
; NO-FMA-NEXT: addq $24, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 8
; NO-FMA-NEXT: retq
;
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
; HAS-FMA-LABEL: constrained_vector_log2_v2f64:
[FPEnv] Expand constrained FP POWI Modify ExpandStrictFPOp(...) to handle nodes that have scalar operands. Also, add a Strict FMA test and do some other light cleanup in the Strict FP code. Differential Revision: https://reviews.llvm.org/D48149 llvm-svn: 334863
2018-06-16 04:57:55 +08:00
; HAS-FMA: # %bb.0: # %entry
; HAS-FMA-NEXT: subq $24, %rsp
; HAS-FMA-NEXT: .cfi_def_cfa_offset 32
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: callq log2
; HAS-FMA-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: callq log2
; HAS-FMA-NEXT: vunpcklpd (%rsp), %xmm0, %xmm0 # 16-byte Folded Reload
; HAS-FMA-NEXT: # xmm0 = xmm0[0],mem[0]
; HAS-FMA-NEXT: addq $24, %rsp
; HAS-FMA-NEXT: .cfi_def_cfa_offset 8
; HAS-FMA-NEXT: retq
[FPEnv] Expand constrained FP operations Add a helper function to expand constrained FP operations as needed. Note that the Strict POWI operation is not handled in this patch since the format is slightly different from the others. Differential Revision: https://reviews.llvm.org/D47491 llvm-svn: 334603
2018-06-13 22:32:12 +08:00
entry:
%log2 = call <2 x double> @llvm.experimental.constrained.log2.v2f64(
<2 x double> <double 42.0, double 42.1>,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <2 x double> %log2
}
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
define <3 x float> @constrained_vector_log2_v3f32() {
; NO-FMA-LABEL: constrained_vector_log2_v3f32:
; NO-FMA: # %bb.0: # %entry
; NO-FMA-NEXT: subq $40, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 48
; NO-FMA-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; NO-FMA-NEXT: callq log2f
; NO-FMA-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; NO-FMA-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; NO-FMA-NEXT: callq log2f
; NO-FMA-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; NO-FMA-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; NO-FMA-NEXT: callq log2f
; NO-FMA-NEXT: movaps (%rsp), %xmm1 # 16-byte Reload
; NO-FMA-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; NO-FMA-NEXT: unpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload
; NO-FMA-NEXT: # xmm1 = xmm1[0],mem[0]
; NO-FMA-NEXT: movaps %xmm1, %xmm0
; NO-FMA-NEXT: addq $40, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 8
; NO-FMA-NEXT: retq
;
; HAS-FMA-LABEL: constrained_vector_log2_v3f32:
; HAS-FMA: # %bb.0: # %entry
; HAS-FMA-NEXT: subq $40, %rsp
; HAS-FMA-NEXT: .cfi_def_cfa_offset 48
; HAS-FMA-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; HAS-FMA-NEXT: callq log2f
; HAS-FMA-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; HAS-FMA-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; HAS-FMA-NEXT: callq log2f
; HAS-FMA-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
; HAS-FMA-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; HAS-FMA-NEXT: callq log2f
; HAS-FMA-NEXT: vmovaps (%rsp), %xmm1 # 16-byte Reload
; HAS-FMA-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[2,3]
; HAS-FMA-NEXT: vinsertps $32, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm0 # 16-byte Folded Reload
; HAS-FMA-NEXT: # xmm0 = xmm0[0,1],mem[0],xmm0[3]
; HAS-FMA-NEXT: addq $40, %rsp
; HAS-FMA-NEXT: .cfi_def_cfa_offset 8
; HAS-FMA-NEXT: retq
entry:
%log2 = call <3 x float> @llvm.experimental.constrained.log2.v3f32(
<3 x float> <float 42.0, float 43.0, float 44.0>,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <3 x float> %log2
}
define <3 x double> @constrained_vector_log2_v3f64() {
; NO-FMA-LABEL: constrained_vector_log2_v3f64:
; NO-FMA: # %bb.0: # %entry
[X86] Add initial SimplifyDemandedVectorEltsForTargetNode support This patch adds an initial x86 SimplifyDemandedVectorEltsForTargetNode implementation to handle target shuffles. Currently the patch only decodes a target shuffle, calls SimplifyDemandedVectorElts on its input operands and removes any shuffle that reduces to undef/zero/identity. Future work will need to integrate this with combineX86ShufflesRecursively, add support for other x86 ops, etc. NOTE: There is a minor regression that appears to be affecting further (extractelement?) combines which I haven't been able to solve yet - possibly something to do with how nodes are added to the worklist after simplification. Differential Revision: https://reviews.llvm.org/D52140 llvm-svn: 342564
2018-09-20 02:11:34 +08:00
; NO-FMA-NEXT: subq $24, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 32
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: callq log2
[X86] Add initial SimplifyDemandedVectorEltsForTargetNode support This patch adds an initial x86 SimplifyDemandedVectorEltsForTargetNode implementation to handle target shuffles. Currently the patch only decodes a target shuffle, calls SimplifyDemandedVectorElts on its input operands and removes any shuffle that reduces to undef/zero/identity. Future work will need to integrate this with combineX86ShufflesRecursively, add support for other x86 ops, etc. NOTE: There is a minor regression that appears to be affecting further (extractelement?) combines which I haven't been able to solve yet - possibly something to do with how nodes are added to the worklist after simplification. Differential Revision: https://reviews.llvm.org/D52140 llvm-svn: 342564
2018-09-20 02:11:34 +08:00
; NO-FMA-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: callq log2
[X86] Add initial SimplifyDemandedVectorEltsForTargetNode support This patch adds an initial x86 SimplifyDemandedVectorEltsForTargetNode implementation to handle target shuffles. Currently the patch only decodes a target shuffle, calls SimplifyDemandedVectorElts on its input operands and removes any shuffle that reduces to undef/zero/identity. Future work will need to integrate this with combineX86ShufflesRecursively, add support for other x86 ops, etc. NOTE: There is a minor regression that appears to be affecting further (extractelement?) combines which I haven't been able to solve yet - possibly something to do with how nodes are added to the worklist after simplification. Differential Revision: https://reviews.llvm.org/D52140 llvm-svn: 342564
2018-09-20 02:11:34 +08:00
; NO-FMA-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: callq log2
; NO-FMA-NEXT: movsd %xmm0, {{[0-9]+}}(%rsp)
; NO-FMA-NEXT: fldl {{[0-9]+}}(%rsp)
[X86] Add initial SimplifyDemandedVectorEltsForTargetNode support This patch adds an initial x86 SimplifyDemandedVectorEltsForTargetNode implementation to handle target shuffles. Currently the patch only decodes a target shuffle, calls SimplifyDemandedVectorElts on its input operands and removes any shuffle that reduces to undef/zero/identity. Future work will need to integrate this with combineX86ShufflesRecursively, add support for other x86 ops, etc. NOTE: There is a minor regression that appears to be affecting further (extractelement?) combines which I haven't been able to solve yet - possibly something to do with how nodes are added to the worklist after simplification. Differential Revision: https://reviews.llvm.org/D52140 llvm-svn: 342564
2018-09-20 02:11:34 +08:00
; NO-FMA-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload
; NO-FMA-NEXT: # xmm0 = mem[0],zero
; NO-FMA-NEXT: movsd (%rsp), %xmm1 # 8-byte Reload
; NO-FMA-NEXT: # xmm1 = mem[0],zero
; NO-FMA-NEXT: addq $24, %rsp
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
; NO-FMA-NEXT: .cfi_def_cfa_offset 8
; NO-FMA-NEXT: retq
;
; HAS-FMA-LABEL: constrained_vector_log2_v3f64:
; HAS-FMA: # %bb.0: # %entry
; HAS-FMA-NEXT: subq $56, %rsp
; HAS-FMA-NEXT: .cfi_def_cfa_offset 64
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: callq log2
; HAS-FMA-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: callq log2
; HAS-FMA-NEXT: vunpcklpd (%rsp), %xmm0, %xmm0 # 16-byte Folded Reload
; HAS-FMA-NEXT: # xmm0 = xmm0[0],mem[0]
; HAS-FMA-NEXT: vmovups %ymm0, (%rsp) # 32-byte Spill
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: vzeroupper
; HAS-FMA-NEXT: callq log2
; HAS-FMA-NEXT: vmovups (%rsp), %ymm1 # 32-byte Reload
; HAS-FMA-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; HAS-FMA-NEXT: addq $56, %rsp
; HAS-FMA-NEXT: .cfi_def_cfa_offset 8
; HAS-FMA-NEXT: retq
entry:
%log2 = call <3 x double> @llvm.experimental.constrained.log2.v3f64(
<3 x double> <double 42.0, double 42.1, double 42.2>,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <3 x double> %log2
}
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
define <4 x double> @constrained_vector_log2_v4f64() {
; NO-FMA-LABEL: constrained_vector_log2_v4f64:
; NO-FMA: # %bb.0: # %entry
; NO-FMA-NEXT: subq $40, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 48
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: callq log2
; NO-FMA-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: callq log2
; NO-FMA-NEXT: unpcklpd (%rsp), %xmm0 # 16-byte Folded Reload
; NO-FMA-NEXT: # xmm0 = xmm0[0],mem[0]
; NO-FMA-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: callq log2
; NO-FMA-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: callq log2
; NO-FMA-NEXT: movaps %xmm0, %xmm1
; NO-FMA-NEXT: unpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload
; NO-FMA-NEXT: # xmm1 = xmm1[0],mem[0]
; NO-FMA-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; NO-FMA-NEXT: addq $40, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 8
; NO-FMA-NEXT: retq
;
; HAS-FMA-LABEL: constrained_vector_log2_v4f64:
; HAS-FMA: # %bb.0: # %entry
; HAS-FMA-NEXT: subq $40, %rsp
; HAS-FMA-NEXT: .cfi_def_cfa_offset 48
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: callq log2
; HAS-FMA-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: callq log2
; HAS-FMA-NEXT: vunpcklpd (%rsp), %xmm0, %xmm0 # 16-byte Folded Reload
; HAS-FMA-NEXT: # xmm0 = xmm0[0],mem[0]
; HAS-FMA-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: callq log2
; HAS-FMA-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: callq log2
; HAS-FMA-NEXT: vunpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm0 # 16-byte Folded Reload
; HAS-FMA-NEXT: # xmm0 = xmm0[0],mem[0]
; HAS-FMA-NEXT: vinsertf128 $1, (%rsp), %ymm0, %ymm0 # 16-byte Folded Reload
; HAS-FMA-NEXT: addq $40, %rsp
; HAS-FMA-NEXT: .cfi_def_cfa_offset 8
; HAS-FMA-NEXT: retq
entry:
%log2 = call <4 x double> @llvm.experimental.constrained.log2.v4f64(
<4 x double> <double 42.0, double 42.1,
double 42.2, double 42.3>,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <4 x double> %log2
}
[FPEnv] Scalarize StrictFP vector operations Add a helper function to scalarize constrained FP operations as needed. Differential Revision: https://reviews.llvm.org/D50720 llvm-svn: 339735
2018-08-15 06:13:11 +08:00
define <1 x float> @constrained_vector_rint_v1f32() {
; NO-FMA-LABEL: constrained_vector_rint_v1f32:
; NO-FMA: # %bb.0: # %entry
; NO-FMA-NEXT: pushq %rax
; NO-FMA-NEXT: .cfi_def_cfa_offset 16
; NO-FMA-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; NO-FMA-NEXT: callq rintf
; NO-FMA-NEXT: popq %rax
; NO-FMA-NEXT: .cfi_def_cfa_offset 8
; NO-FMA-NEXT: retq
;
; HAS-FMA-LABEL: constrained_vector_rint_v1f32:
; HAS-FMA: # %bb.0: # %entry
; HAS-FMA-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; HAS-FMA-NEXT: vroundss $4, %xmm0, %xmm0, %xmm0
; HAS-FMA-NEXT: retq
entry:
%rint = call <1 x float> @llvm.experimental.constrained.rint.v1f32(
<1 x float> <float 42.0>,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <1 x float> %rint
}
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
define <2 x double> @constrained_vector_rint_v2f64() {
; NO-FMA-LABEL: constrained_vector_rint_v2f64:
[FPEnv] Expand constrained FP POWI Modify ExpandStrictFPOp(...) to handle nodes that have scalar operands. Also, add a Strict FMA test and do some other light cleanup in the Strict FP code. Differential Revision: https://reviews.llvm.org/D48149 llvm-svn: 334863
2018-06-16 04:57:55 +08:00
; NO-FMA: # %bb.0: # %entry
; NO-FMA-NEXT: subq $24, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 32
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: callq rint
; NO-FMA-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: callq rint
; NO-FMA-NEXT: unpcklpd (%rsp), %xmm0 # 16-byte Folded Reload
; NO-FMA-NEXT: # xmm0 = xmm0[0],mem[0]
; NO-FMA-NEXT: addq $24, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 8
; NO-FMA-NEXT: retq
;
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
; HAS-FMA-LABEL: constrained_vector_rint_v2f64:
[FPEnv] Expand constrained FP POWI Modify ExpandStrictFPOp(...) to handle nodes that have scalar operands. Also, add a Strict FMA test and do some other light cleanup in the Strict FP code. Differential Revision: https://reviews.llvm.org/D48149 llvm-svn: 334863
2018-06-16 04:57:55 +08:00
; HAS-FMA: # %bb.0: # %entry
; HAS-FMA-NEXT: vroundpd $4, {{.*}}(%rip), %xmm0
; HAS-FMA-NEXT: retq
[FPEnv] Expand constrained FP operations Add a helper function to expand constrained FP operations as needed. Note that the Strict POWI operation is not handled in this patch since the format is slightly different from the others. Differential Revision: https://reviews.llvm.org/D47491 llvm-svn: 334603
2018-06-13 22:32:12 +08:00
entry:
%rint = call <2 x double> @llvm.experimental.constrained.rint.v2f64(
<2 x double> <double 42.1, double 42.0>,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <2 x double> %rint
}
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
define <3 x float> @constrained_vector_rint_v3f32() {
; NO-FMA-LABEL: constrained_vector_rint_v3f32:
; NO-FMA: # %bb.0: # %entry
; NO-FMA-NEXT: subq $40, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 48
; NO-FMA-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; NO-FMA-NEXT: callq rintf
; NO-FMA-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; NO-FMA-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; NO-FMA-NEXT: callq rintf
; NO-FMA-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; NO-FMA-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; NO-FMA-NEXT: callq rintf
; NO-FMA-NEXT: movaps (%rsp), %xmm1 # 16-byte Reload
; NO-FMA-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; NO-FMA-NEXT: unpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload
; NO-FMA-NEXT: # xmm1 = xmm1[0],mem[0]
; NO-FMA-NEXT: movaps %xmm1, %xmm0
; NO-FMA-NEXT: addq $40, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 8
; NO-FMA-NEXT: retq
;
; HAS-FMA-LABEL: constrained_vector_rint_v3f32:
; HAS-FMA: # %bb.0: # %entry
; HAS-FMA-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; HAS-FMA-NEXT: vroundss $4, %xmm0, %xmm0, %xmm0
; HAS-FMA-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; HAS-FMA-NEXT: vroundss $4, %xmm1, %xmm1, %xmm1
; HAS-FMA-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; HAS-FMA-NEXT: vroundss $4, %xmm2, %xmm2, %xmm2
; HAS-FMA-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[2,3]
; HAS-FMA-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1],xmm0[0],xmm1[3]
; HAS-FMA-NEXT: retq
entry:
%rint = call <3 x float> @llvm.experimental.constrained.rint.v3f32(
<3 x float> <float 42.0, float 43.0, float 44.0>,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <3 x float> %rint
}
define <3 x double> @constrained_vector_rint_v3f64() {
; NO-FMA-LABEL: constrained_vector_rint_v3f64:
; NO-FMA: # %bb.0: # %entry
[X86] Add initial SimplifyDemandedVectorEltsForTargetNode support This patch adds an initial x86 SimplifyDemandedVectorEltsForTargetNode implementation to handle target shuffles. Currently the patch only decodes a target shuffle, calls SimplifyDemandedVectorElts on its input operands and removes any shuffle that reduces to undef/zero/identity. Future work will need to integrate this with combineX86ShufflesRecursively, add support for other x86 ops, etc. NOTE: There is a minor regression that appears to be affecting further (extractelement?) combines which I haven't been able to solve yet - possibly something to do with how nodes are added to the worklist after simplification. Differential Revision: https://reviews.llvm.org/D52140 llvm-svn: 342564
2018-09-20 02:11:34 +08:00
; NO-FMA-NEXT: subq $24, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 32
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: callq rint
[X86] Add initial SimplifyDemandedVectorEltsForTargetNode support This patch adds an initial x86 SimplifyDemandedVectorEltsForTargetNode implementation to handle target shuffles. Currently the patch only decodes a target shuffle, calls SimplifyDemandedVectorElts on its input operands and removes any shuffle that reduces to undef/zero/identity. Future work will need to integrate this with combineX86ShufflesRecursively, add support for other x86 ops, etc. NOTE: There is a minor regression that appears to be affecting further (extractelement?) combines which I haven't been able to solve yet - possibly something to do with how nodes are added to the worklist after simplification. Differential Revision: https://reviews.llvm.org/D52140 llvm-svn: 342564
2018-09-20 02:11:34 +08:00
; NO-FMA-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: callq rint
[X86] Add initial SimplifyDemandedVectorEltsForTargetNode support This patch adds an initial x86 SimplifyDemandedVectorEltsForTargetNode implementation to handle target shuffles. Currently the patch only decodes a target shuffle, calls SimplifyDemandedVectorElts on its input operands and removes any shuffle that reduces to undef/zero/identity. Future work will need to integrate this with combineX86ShufflesRecursively, add support for other x86 ops, etc. NOTE: There is a minor regression that appears to be affecting further (extractelement?) combines which I haven't been able to solve yet - possibly something to do with how nodes are added to the worklist after simplification. Differential Revision: https://reviews.llvm.org/D52140 llvm-svn: 342564
2018-09-20 02:11:34 +08:00
; NO-FMA-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: callq rint
; NO-FMA-NEXT: movsd %xmm0, {{[0-9]+}}(%rsp)
; NO-FMA-NEXT: fldl {{[0-9]+}}(%rsp)
[X86] Add initial SimplifyDemandedVectorEltsForTargetNode support This patch adds an initial x86 SimplifyDemandedVectorEltsForTargetNode implementation to handle target shuffles. Currently the patch only decodes a target shuffle, calls SimplifyDemandedVectorElts on its input operands and removes any shuffle that reduces to undef/zero/identity. Future work will need to integrate this with combineX86ShufflesRecursively, add support for other x86 ops, etc. NOTE: There is a minor regression that appears to be affecting further (extractelement?) combines which I haven't been able to solve yet - possibly something to do with how nodes are added to the worklist after simplification. Differential Revision: https://reviews.llvm.org/D52140 llvm-svn: 342564
2018-09-20 02:11:34 +08:00
; NO-FMA-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload
; NO-FMA-NEXT: # xmm0 = mem[0],zero
; NO-FMA-NEXT: movsd (%rsp), %xmm1 # 8-byte Reload
; NO-FMA-NEXT: # xmm1 = mem[0],zero
; NO-FMA-NEXT: addq $24, %rsp
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
; NO-FMA-NEXT: .cfi_def_cfa_offset 8
; NO-FMA-NEXT: retq
;
; HAS-FMA-LABEL: constrained_vector_rint_v3f64:
; HAS-FMA: # %bb.0: # %entry
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: vroundsd $4, %xmm0, %xmm0, %xmm0
; HAS-FMA-NEXT: vroundpd $4, {{.*}}(%rip), %xmm1
; HAS-FMA-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; HAS-FMA-NEXT: retq
entry:
%rint = call <3 x double> @llvm.experimental.constrained.rint.v3f64(
<3 x double> <double 42.0, double 42.1, double 42.2>,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <3 x double> %rint
}
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
define <4 x double> @constrained_vector_rint_v4f64() {
; NO-FMA-LABEL: constrained_vector_rint_v4f64:
; NO-FMA: # %bb.0: # %entry
; NO-FMA-NEXT: subq $40, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 48
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: callq rint
; NO-FMA-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: callq rint
; NO-FMA-NEXT: unpcklpd (%rsp), %xmm0 # 16-byte Folded Reload
; NO-FMA-NEXT: # xmm0 = xmm0[0],mem[0]
; NO-FMA-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: callq rint
; NO-FMA-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: callq rint
; NO-FMA-NEXT: movaps %xmm0, %xmm1
; NO-FMA-NEXT: unpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload
; NO-FMA-NEXT: # xmm1 = xmm1[0],mem[0]
; NO-FMA-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; NO-FMA-NEXT: addq $40, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 8
; NO-FMA-NEXT: retq
;
; HAS-FMA-LABEL: constrained_vector_rint_v4f64:
; HAS-FMA: # %bb.0: # %entry
; HAS-FMA-NEXT: vroundpd $4, {{.*}}(%rip), %ymm0
; HAS-FMA-NEXT: retq
entry:
%rint = call <4 x double> @llvm.experimental.constrained.rint.v4f64(
<4 x double> <double 42.1, double 42.2,
double 42.3, double 42.4>,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <4 x double> %rint
}
[FPEnv] Scalarize StrictFP vector operations Add a helper function to scalarize constrained FP operations as needed. Differential Revision: https://reviews.llvm.org/D50720 llvm-svn: 339735
2018-08-15 06:13:11 +08:00
define <1 x float> @constrained_vector_nearbyint_v1f32() {
; NO-FMA-LABEL: constrained_vector_nearbyint_v1f32:
; NO-FMA: # %bb.0: # %entry
; NO-FMA-NEXT: pushq %rax
; NO-FMA-NEXT: .cfi_def_cfa_offset 16
; NO-FMA-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; NO-FMA-NEXT: callq nearbyintf
; NO-FMA-NEXT: popq %rax
; NO-FMA-NEXT: .cfi_def_cfa_offset 8
; NO-FMA-NEXT: retq
;
; HAS-FMA-LABEL: constrained_vector_nearbyint_v1f32:
; HAS-FMA: # %bb.0: # %entry
; HAS-FMA-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; HAS-FMA-NEXT: vroundss $12, %xmm0, %xmm0, %xmm0
; HAS-FMA-NEXT: retq
entry:
%nearby = call <1 x float> @llvm.experimental.constrained.nearbyint.v1f32(
<1 x float> <float 42.0>,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <1 x float> %nearby
}
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
define <2 x double> @constrained_vector_nearbyint_v2f64() {
; NO-FMA-LABEL: constrained_vector_nearbyint_v2f64:
[FPEnv] Expand constrained FP POWI Modify ExpandStrictFPOp(...) to handle nodes that have scalar operands. Also, add a Strict FMA test and do some other light cleanup in the Strict FP code. Differential Revision: https://reviews.llvm.org/D48149 llvm-svn: 334863
2018-06-16 04:57:55 +08:00
; NO-FMA: # %bb.0: # %entry
; NO-FMA-NEXT: subq $24, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 32
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: callq nearbyint
; NO-FMA-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: callq nearbyint
; NO-FMA-NEXT: unpcklpd (%rsp), %xmm0 # 16-byte Folded Reload
; NO-FMA-NEXT: # xmm0 = xmm0[0],mem[0]
; NO-FMA-NEXT: addq $24, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 8
; NO-FMA-NEXT: retq
;
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
; HAS-FMA-LABEL: constrained_vector_nearbyint_v2f64:
[FPEnv] Expand constrained FP POWI Modify ExpandStrictFPOp(...) to handle nodes that have scalar operands. Also, add a Strict FMA test and do some other light cleanup in the Strict FP code. Differential Revision: https://reviews.llvm.org/D48149 llvm-svn: 334863
2018-06-16 04:57:55 +08:00
; HAS-FMA: # %bb.0: # %entry
; HAS-FMA-NEXT: vroundpd $12, {{.*}}(%rip), %xmm0
; HAS-FMA-NEXT: retq
[FPEnv] Expand constrained FP operations Add a helper function to expand constrained FP operations as needed. Note that the Strict POWI operation is not handled in this patch since the format is slightly different from the others. Differential Revision: https://reviews.llvm.org/D47491 llvm-svn: 334603
2018-06-13 22:32:12 +08:00
entry:
%nearby = call <2 x double> @llvm.experimental.constrained.nearbyint.v2f64(
<2 x double> <double 42.1, double 42.0>,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <2 x double> %nearby
}
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
define <3 x float> @constrained_vector_nearbyint_v3f32() {
; NO-FMA-LABEL: constrained_vector_nearbyint_v3f32:
; NO-FMA: # %bb.0: # %entry
; NO-FMA-NEXT: subq $40, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 48
; NO-FMA-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; NO-FMA-NEXT: callq nearbyintf
; NO-FMA-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; NO-FMA-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; NO-FMA-NEXT: callq nearbyintf
; NO-FMA-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; NO-FMA-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; NO-FMA-NEXT: callq nearbyintf
; NO-FMA-NEXT: movaps (%rsp), %xmm1 # 16-byte Reload
; NO-FMA-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; NO-FMA-NEXT: unpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload
; NO-FMA-NEXT: # xmm1 = xmm1[0],mem[0]
; NO-FMA-NEXT: movaps %xmm1, %xmm0
; NO-FMA-NEXT: addq $40, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 8
; NO-FMA-NEXT: retq
;
; HAS-FMA-LABEL: constrained_vector_nearbyint_v3f32:
; HAS-FMA: # %bb.0: # %entry
; HAS-FMA-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; HAS-FMA-NEXT: vroundss $12, %xmm0, %xmm0, %xmm0
; HAS-FMA-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; HAS-FMA-NEXT: vroundss $12, %xmm1, %xmm1, %xmm1
; HAS-FMA-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; HAS-FMA-NEXT: vroundss $12, %xmm2, %xmm2, %xmm2
; HAS-FMA-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[2,3]
; HAS-FMA-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1],xmm0[0],xmm1[3]
; HAS-FMA-NEXT: retq
entry:
%nearby = call <3 x float> @llvm.experimental.constrained.nearbyint.v3f32(
<3 x float> <float 42.0, float 43.0, float 44.0>,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <3 x float> %nearby
}
define <3 x double> @constrained_vector_nearby_v3f64() {
; NO-FMA-LABEL: constrained_vector_nearby_v3f64:
; NO-FMA: # %bb.0: # %entry
[X86] Add initial SimplifyDemandedVectorEltsForTargetNode support This patch adds an initial x86 SimplifyDemandedVectorEltsForTargetNode implementation to handle target shuffles. Currently the patch only decodes a target shuffle, calls SimplifyDemandedVectorElts on its input operands and removes any shuffle that reduces to undef/zero/identity. Future work will need to integrate this with combineX86ShufflesRecursively, add support for other x86 ops, etc. NOTE: There is a minor regression that appears to be affecting further (extractelement?) combines which I haven't been able to solve yet - possibly something to do with how nodes are added to the worklist after simplification. Differential Revision: https://reviews.llvm.org/D52140 llvm-svn: 342564
2018-09-20 02:11:34 +08:00
; NO-FMA-NEXT: subq $24, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 32
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: callq nearbyint
[X86] Add initial SimplifyDemandedVectorEltsForTargetNode support This patch adds an initial x86 SimplifyDemandedVectorEltsForTargetNode implementation to handle target shuffles. Currently the patch only decodes a target shuffle, calls SimplifyDemandedVectorElts on its input operands and removes any shuffle that reduces to undef/zero/identity. Future work will need to integrate this with combineX86ShufflesRecursively, add support for other x86 ops, etc. NOTE: There is a minor regression that appears to be affecting further (extractelement?) combines which I haven't been able to solve yet - possibly something to do with how nodes are added to the worklist after simplification. Differential Revision: https://reviews.llvm.org/D52140 llvm-svn: 342564
2018-09-20 02:11:34 +08:00
; NO-FMA-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: callq nearbyint
[X86] Add initial SimplifyDemandedVectorEltsForTargetNode support This patch adds an initial x86 SimplifyDemandedVectorEltsForTargetNode implementation to handle target shuffles. Currently the patch only decodes a target shuffle, calls SimplifyDemandedVectorElts on its input operands and removes any shuffle that reduces to undef/zero/identity. Future work will need to integrate this with combineX86ShufflesRecursively, add support for other x86 ops, etc. NOTE: There is a minor regression that appears to be affecting further (extractelement?) combines which I haven't been able to solve yet - possibly something to do with how nodes are added to the worklist after simplification. Differential Revision: https://reviews.llvm.org/D52140 llvm-svn: 342564
2018-09-20 02:11:34 +08:00
; NO-FMA-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: callq nearbyint
; NO-FMA-NEXT: movsd %xmm0, {{[0-9]+}}(%rsp)
; NO-FMA-NEXT: fldl {{[0-9]+}}(%rsp)
[X86] Add initial SimplifyDemandedVectorEltsForTargetNode support This patch adds an initial x86 SimplifyDemandedVectorEltsForTargetNode implementation to handle target shuffles. Currently the patch only decodes a target shuffle, calls SimplifyDemandedVectorElts on its input operands and removes any shuffle that reduces to undef/zero/identity. Future work will need to integrate this with combineX86ShufflesRecursively, add support for other x86 ops, etc. NOTE: There is a minor regression that appears to be affecting further (extractelement?) combines which I haven't been able to solve yet - possibly something to do with how nodes are added to the worklist after simplification. Differential Revision: https://reviews.llvm.org/D52140 llvm-svn: 342564
2018-09-20 02:11:34 +08:00
; NO-FMA-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload
; NO-FMA-NEXT: # xmm0 = mem[0],zero
; NO-FMA-NEXT: movsd (%rsp), %xmm1 # 8-byte Reload
; NO-FMA-NEXT: # xmm1 = mem[0],zero
; NO-FMA-NEXT: addq $24, %rsp
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
; NO-FMA-NEXT: .cfi_def_cfa_offset 8
; NO-FMA-NEXT: retq
;
; HAS-FMA-LABEL: constrained_vector_nearby_v3f64:
; HAS-FMA: # %bb.0: # %entry
; HAS-FMA-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; HAS-FMA-NEXT: vroundsd $12, %xmm0, %xmm0, %xmm0
; HAS-FMA-NEXT: vroundpd $12, {{.*}}(%rip), %xmm1
; HAS-FMA-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; HAS-FMA-NEXT: retq
entry:
%nearby = call <3 x double> @llvm.experimental.constrained.nearbyint.v3f64(
<3 x double> <double 42.0, double 42.1, double 42.2>,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <3 x double> %nearby
}
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
define <4 x double> @constrained_vector_nearbyint_v4f64() {
; NO-FMA-LABEL: constrained_vector_nearbyint_v4f64:
; NO-FMA: # %bb.0: # %entry
; NO-FMA-NEXT: subq $40, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 48
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: callq nearbyint
; NO-FMA-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: callq nearbyint
; NO-FMA-NEXT: unpcklpd (%rsp), %xmm0 # 16-byte Folded Reload
; NO-FMA-NEXT: # xmm0 = xmm0[0],mem[0]
; NO-FMA-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: callq nearbyint
; NO-FMA-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; NO-FMA-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NO-FMA-NEXT: callq nearbyint
; NO-FMA-NEXT: movaps %xmm0, %xmm1
; NO-FMA-NEXT: unpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload
; NO-FMA-NEXT: # xmm1 = xmm1[0],mem[0]
; NO-FMA-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; NO-FMA-NEXT: addq $40, %rsp
; NO-FMA-NEXT: .cfi_def_cfa_offset 8
; NO-FMA-NEXT: retq
;
; HAS-FMA-LABEL: constrained_vector_nearbyint_v4f64:
; HAS-FMA: # %bb.0: # %entry
; HAS-FMA-NEXT: vroundpd $12, {{.*}}(%rip), %ymm0
; HAS-FMA-NEXT: retq
entry:
%nearby = call <4 x double> @llvm.experimental.constrained.nearbyint.v4f64(
<4 x double> <double 42.1, double 42.2,
double 42.3, double 42.4>,
metadata !"round.dynamic",
metadata !"fpexcept.strict")
ret <4 x double> %nearby
}
[FPEnv] Expand constrained FP operations Add a helper function to expand constrained FP operations as needed. Note that the Strict POWI operation is not handled in this patch since the format is slightly different from the others. Differential Revision: https://reviews.llvm.org/D47491 llvm-svn: 334603
2018-06-13 22:32:12 +08:00
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
; Single width declarations
[FPEnv] Expand constrained FP operations Add a helper function to expand constrained FP operations as needed. Note that the Strict POWI operation is not handled in this patch since the format is slightly different from the others. Differential Revision: https://reviews.llvm.org/D47491 llvm-svn: 334603
2018-06-13 22:32:12 +08:00
declare <2 x double> @llvm.experimental.constrained.fadd.v2f64(<2 x double>, <2 x double>, metadata, metadata)
declare <2 x double> @llvm.experimental.constrained.fsub.v2f64(<2 x double>, <2 x double>, metadata, metadata)
[FPEnv] Support constrained FREM intrinsic Differential Revision: https://reviews.llvm.org/D50975 llvm-svn: 340201
2018-08-21 03:28:56 +08:00
declare <2 x double> @llvm.experimental.constrained.fmul.v2f64(<2 x double>, <2 x double>, metadata, metadata)
declare <2 x double> @llvm.experimental.constrained.fdiv.v2f64(<2 x double>, <2 x double>, metadata, metadata)
declare <2 x double> @llvm.experimental.constrained.frem.v2f64(<2 x double>, <2 x double>, metadata, metadata)
[FPEnv] Expand constrained FP POWI Modify ExpandStrictFPOp(...) to handle nodes that have scalar operands. Also, add a Strict FMA test and do some other light cleanup in the Strict FP code. Differential Revision: https://reviews.llvm.org/D48149 llvm-svn: 334863
2018-06-16 04:57:55 +08:00
declare <2 x double> @llvm.experimental.constrained.fma.v2f64(<2 x double>, <2 x double>, <2 x double>, metadata, metadata)
declare <4 x float> @llvm.experimental.constrained.fma.v4f32(<4 x float>, <4 x float>, <4 x float>, metadata, metadata)
[FPEnv] Expand constrained FP operations Add a helper function to expand constrained FP operations as needed. Note that the Strict POWI operation is not handled in this patch since the format is slightly different from the others. Differential Revision: https://reviews.llvm.org/D47491 llvm-svn: 334603
2018-06-13 22:32:12 +08:00
declare <2 x double> @llvm.experimental.constrained.sqrt.v2f64(<2 x double>, metadata, metadata)
declare <2 x double> @llvm.experimental.constrained.pow.v2f64(<2 x double>, <2 x double>, metadata, metadata)
[FPEnv] Expand constrained FP POWI Modify ExpandStrictFPOp(...) to handle nodes that have scalar operands. Also, add a Strict FMA test and do some other light cleanup in the Strict FP code. Differential Revision: https://reviews.llvm.org/D48149 llvm-svn: 334863
2018-06-16 04:57:55 +08:00
declare <2 x double> @llvm.experimental.constrained.powi.v2f64(<2 x double>, i32, metadata, metadata)
[FPEnv] Expand constrained FP operations Add a helper function to expand constrained FP operations as needed. Note that the Strict POWI operation is not handled in this patch since the format is slightly different from the others. Differential Revision: https://reviews.llvm.org/D47491 llvm-svn: 334603
2018-06-13 22:32:12 +08:00
declare <2 x double> @llvm.experimental.constrained.sin.v2f64(<2 x double>, metadata, metadata)
declare <2 x double> @llvm.experimental.constrained.cos.v2f64(<2 x double>, metadata, metadata)
declare <2 x double> @llvm.experimental.constrained.exp.v2f64(<2 x double>, metadata, metadata)
declare <2 x double> @llvm.experimental.constrained.exp2.v2f64(<2 x double>, metadata, metadata)
declare <2 x double> @llvm.experimental.constrained.log.v2f64(<2 x double>, metadata, metadata)
declare <2 x double> @llvm.experimental.constrained.log10.v2f64(<2 x double>, metadata, metadata)
declare <2 x double> @llvm.experimental.constrained.log2.v2f64(<2 x double>, metadata, metadata)
declare <2 x double> @llvm.experimental.constrained.rint.v2f64(<2 x double>, metadata, metadata)
declare <2 x double> @llvm.experimental.constrained.nearbyint.v2f64(<2 x double>, metadata, metadata)
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
[FPEnv] Scalarize StrictFP vector operations Add a helper function to scalarize constrained FP operations as needed. Differential Revision: https://reviews.llvm.org/D50720 llvm-svn: 339735
2018-08-15 06:13:11 +08:00
; Scalar width declarations
declare <1 x float> @llvm.experimental.constrained.fadd.v1f32(<1 x float>, <1 x float>, metadata, metadata)
declare <1 x float> @llvm.experimental.constrained.fsub.v1f32(<1 x float>, <1 x float>, metadata, metadata)
[FPEnv] Support constrained FREM intrinsic Differential Revision: https://reviews.llvm.org/D50975 llvm-svn: 340201
2018-08-21 03:28:56 +08:00
declare <1 x float> @llvm.experimental.constrained.fmul.v1f32(<1 x float>, <1 x float>, metadata, metadata)
declare <1 x float> @llvm.experimental.constrained.fdiv.v1f32(<1 x float>, <1 x float>, metadata, metadata)
declare <1 x float> @llvm.experimental.constrained.frem.v1f32(<1 x float>, <1 x float>, metadata, metadata)
[FPEnv] Scalarize StrictFP vector operations Add a helper function to scalarize constrained FP operations as needed. Differential Revision: https://reviews.llvm.org/D50720 llvm-svn: 339735
2018-08-15 06:13:11 +08:00
declare <1 x float> @llvm.experimental.constrained.fma.v1f32(<1 x float>, <1 x float>, <1 x float>, metadata, metadata)
declare <1 x float> @llvm.experimental.constrained.sqrt.v1f32(<1 x float>, metadata, metadata)
declare <1 x float> @llvm.experimental.constrained.pow.v1f32(<1 x float>, <1 x float>, metadata, metadata)
declare <1 x float> @llvm.experimental.constrained.powi.v1f32(<1 x float>, i32, metadata, metadata)
declare <1 x float> @llvm.experimental.constrained.sin.v1f32(<1 x float>, metadata, metadata)
declare <1 x float> @llvm.experimental.constrained.cos.v1f32(<1 x float>, metadata, metadata)
declare <1 x float> @llvm.experimental.constrained.exp.v1f32(<1 x float>, metadata, metadata)
declare <1 x float> @llvm.experimental.constrained.exp2.v1f32(<1 x float>, metadata, metadata)
declare <1 x float> @llvm.experimental.constrained.log.v1f32(<1 x float>, metadata, metadata)
declare <1 x float> @llvm.experimental.constrained.log10.v1f32(<1 x float>, metadata, metadata)
declare <1 x float> @llvm.experimental.constrained.log2.v1f32(<1 x float>, metadata, metadata)
declare <1 x float> @llvm.experimental.constrained.rint.v1f32(<1 x float>, metadata, metadata)
declare <1 x float> @llvm.experimental.constrained.nearbyint.v1f32(<1 x float>, metadata, metadata)
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
; Illegal width declarations
declare <3 x float> @llvm.experimental.constrained.fadd.v3f32(<3 x float>, <3 x float>, metadata, metadata)
declare <3 x double> @llvm.experimental.constrained.fadd.v3f64(<3 x double>, <3 x double>, metadata, metadata)
declare <3 x float> @llvm.experimental.constrained.fsub.v3f32(<3 x float>, <3 x float>, metadata, metadata)
declare <3 x double> @llvm.experimental.constrained.fsub.v3f64(<3 x double>, <3 x double>, metadata, metadata)
[FPEnv] Support constrained FREM intrinsic Differential Revision: https://reviews.llvm.org/D50975 llvm-svn: 340201
2018-08-21 03:28:56 +08:00
declare <3 x float> @llvm.experimental.constrained.fmul.v3f32(<3 x float>, <3 x float>, metadata, metadata)
declare <3 x double> @llvm.experimental.constrained.fmul.v3f64(<3 x double>, <3 x double>, metadata, metadata)
declare <3 x float> @llvm.experimental.constrained.fdiv.v3f32(<3 x float>, <3 x float>, metadata, metadata)
declare <3 x double> @llvm.experimental.constrained.fdiv.v3f64(<3 x double>, <3 x double>, metadata, metadata)
declare <3 x float> @llvm.experimental.constrained.frem.v3f32(<3 x float>, <3 x float>, metadata, metadata)
declare <3 x double> @llvm.experimental.constrained.frem.v3f64(<3 x double>, <3 x double>, metadata, metadata)
[FPEnv] Widen illegal width StrictFP vector operations as needed Differential Revision: https://reviews.llvm.org/D49806 llvm-svn: 338562
2018-08-01 22:17:19 +08:00
declare <3 x float> @llvm.experimental.constrained.fma.v3f32(<3 x float>, <3 x float>, <3 x float>, metadata, metadata)
declare <3 x double> @llvm.experimental.constrained.fma.v3f64(<3 x double>, <3 x double>, <3 x double>, metadata, metadata)
declare <3 x float> @llvm.experimental.constrained.sqrt.v3f32(<3 x float>, metadata, metadata)
declare <3 x double> @llvm.experimental.constrained.sqrt.v3f64(<3 x double>, metadata, metadata)
declare <3 x float> @llvm.experimental.constrained.pow.v3f32(<3 x float>, <3 x float>, metadata, metadata)
declare <3 x double> @llvm.experimental.constrained.pow.v3f64(<3 x double>, <3 x double>, metadata, metadata)
declare <3 x float> @llvm.experimental.constrained.powi.v3f32(<3 x float>, i32, metadata, metadata)
declare <3 x double> @llvm.experimental.constrained.powi.v3f64(<3 x double>, i32, metadata, metadata)
declare <3 x float> @llvm.experimental.constrained.sin.v3f32(<3 x float>, metadata, metadata)
declare <3 x double> @llvm.experimental.constrained.sin.v3f64(<3 x double>, metadata, metadata)
declare <3 x float> @llvm.experimental.constrained.cos.v3f32(<3 x float>, metadata, metadata)
declare <3 x double> @llvm.experimental.constrained.cos.v3f64(<3 x double>, metadata, metadata)
declare <3 x float> @llvm.experimental.constrained.exp.v3f32(<3 x float>, metadata, metadata)
declare <3 x double> @llvm.experimental.constrained.exp.v3f64(<3 x double>, metadata, metadata)
declare <3 x float> @llvm.experimental.constrained.exp2.v3f32(<3 x float>, metadata, metadata)
declare <3 x double> @llvm.experimental.constrained.exp2.v3f64(<3 x double>, metadata, metadata)
declare <3 x float> @llvm.experimental.constrained.log.v3f32(<3 x float>, metadata, metadata)
declare <3 x double> @llvm.experimental.constrained.log.v3f64(<3 x double>, metadata, metadata)
declare <3 x float> @llvm.experimental.constrained.log10.v3f32(<3 x float>, metadata, metadata)
declare <3 x double> @llvm.experimental.constrained.log10.v3f64(<3 x double>, metadata, metadata)
declare <3 x float> @llvm.experimental.constrained.log2.v3f32(<3 x float>, metadata, metadata)
declare <3 x double> @llvm.experimental.constrained.log2.v3f64(<3 x double>, metadata, metadata)
declare <3 x float> @llvm.experimental.constrained.rint.v3f32(<3 x float>, metadata, metadata)
declare <3 x double> @llvm.experimental.constrained.rint.v3f64(<3 x double>, metadata, metadata)
declare <3 x float> @llvm.experimental.constrained.nearbyint.v3f32(<3 x float>, metadata, metadata)
declare <3 x double> @llvm.experimental.constrained.nearbyint.v3f64(<3 x double>, metadata, metadata)
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
; Double width declarations
declare <4 x double> @llvm.experimental.constrained.fadd.v4f64(<4 x double>, <4 x double>, metadata, metadata)
declare <4 x double> @llvm.experimental.constrained.fsub.v4f64(<4 x double>, <4 x double>, metadata, metadata)
[FPEnv] Support constrained FREM intrinsic Differential Revision: https://reviews.llvm.org/D50975 llvm-svn: 340201
2018-08-21 03:28:56 +08:00
declare <4 x double> @llvm.experimental.constrained.fmul.v4f64(<4 x double>, <4 x double>, metadata, metadata)
declare <4 x double> @llvm.experimental.constrained.fdiv.v4f64(<4 x double>, <4 x double>, metadata, metadata)
declare <4 x double> @llvm.experimental.constrained.frem.v4f64(<4 x double>, <4 x double>, metadata, metadata)
[FPEnv] Legalize double width StrictFP vector operations Differential Revision: https://reviews.llvm.org/D48809 llvm-svn: 337698
2018-07-23 22:40:17 +08:00
declare <4 x double> @llvm.experimental.constrained.fma.v4f64(<4 x double>, <4 x double>, <4 x double>, metadata, metadata)
declare <8 x float> @llvm.experimental.constrained.fma.v8f32(<8 x float>, <8 x float>, <8 x float>, metadata, metadata)
declare <4 x double> @llvm.experimental.constrained.sqrt.v4f64(<4 x double>, metadata, metadata)
declare <4 x double> @llvm.experimental.constrained.pow.v4f64(<4 x double>, <4 x double>, metadata, metadata)
declare <4 x double> @llvm.experimental.constrained.powi.v4f64(<4 x double>, i32, metadata, metadata)
declare <4 x double> @llvm.experimental.constrained.sin.v4f64(<4 x double>, metadata, metadata)
declare <4 x double> @llvm.experimental.constrained.cos.v4f64(<4 x double>, metadata, metadata)
declare <4 x double> @llvm.experimental.constrained.exp.v4f64(<4 x double>, metadata, metadata)
declare <4 x double> @llvm.experimental.constrained.exp2.v4f64(<4 x double>, metadata, metadata)
declare <4 x double> @llvm.experimental.constrained.log.v4f64(<4 x double>, metadata, metadata)
declare <4 x double> @llvm.experimental.constrained.log10.v4f64(<4 x double>, metadata, metadata)
declare <4 x double> @llvm.experimental.constrained.log2.v4f64(<4 x double>, metadata, metadata)
declare <4 x double> @llvm.experimental.constrained.rint.v4f64(<4 x double>, metadata, metadata)
declare <4 x double> @llvm.experimental.constrained.nearbyint.v4f64(<4 x double>, metadata, metadata)