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llvm-project/llvm/test/CodeGen/X86/inline-asm-mrv.ll

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add support for multiple return values in inline asm. This is a step towards PR2094. It now compiles the attached .ll file to: _sad16_sse2: movslq %ecx, %rax ## InlineAsm Start %ecx %rdx %rax %rax %r8d %rdx %rsi ## InlineAsm End ## InlineAsm Start set %eax ## InlineAsm End ret which is pretty decent for a 3 output, 4 input asm. llvm-svn: 50386
2008-04-29 12:29:54 +08:00
; PR2094
X86: Do not use llc -march in tests. `llc -march` is problematic because it only switches the target architecture, but leaves the operating system unchanged. This occasionally leads to indeterministic tests because the OS from LLVM_DEFAULT_TARGET_TRIPLE is used. However we can simply always use `llc -mtriple` instead. This changes all the tests to do this to avoid people using -march when they copy and paste parts of tests. See also the discussion in https://reviews.llvm.org/D35287 llvm-svn: 309774
2017-08-02 08:28:10 +08:00
; RUN: llc < %s -no-integrated-as | grep movslq
; RUN: llc < %s -no-integrated-as | grep addps
; RUN: llc < %s -no-integrated-as | grep paddd
; RUN: llc < %s -no-integrated-as | not grep movq
add support for multiple return values in inline asm. This is a step towards PR2094. It now compiles the attached .ll file to: _sad16_sse2: movslq %ecx, %rax ## InlineAsm Start %ecx %rdx %rax %rax %r8d %rdx %rsi ## InlineAsm End ## InlineAsm Start set %eax ## InlineAsm End ret which is pretty decent for a 3 output, 4 input asm. llvm-svn: 50386
2008-04-29 12:29:54 +08:00
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
target triple = "x86_64-apple-darwin8"
make the vector conversion magic handle multiple results. We now compile test2/test3 to: _test2: ## InlineAsm Start set %xmm0, %xmm1 ## InlineAsm End addps %xmm1, %xmm0 ret _test3: ## InlineAsm Start set %xmm0, %xmm1 ## InlineAsm End paddd %xmm1, %xmm0 ret as expected. llvm-svn: 50389
2008-04-29 12:48:56 +08:00
define i32 @test1(i8* %v, i8* %blk2, i8* %blk1, i32 %stride, i32 %h) nounwind {
add support for multiple return values in inline asm. This is a step towards PR2094. It now compiles the attached .ll file to: _sad16_sse2: movslq %ecx, %rax ## InlineAsm Start %ecx %rdx %rax %rax %r8d %rdx %rsi ## InlineAsm End ## InlineAsm Start set %eax ## InlineAsm End ret which is pretty decent for a 3 output, 4 input asm. llvm-svn: 50386
2008-04-29 12:29:54 +08:00
%tmp12 = sext i32 %stride to i64 ; <i64> [#uses=1]
%mrv = call {i32, i8*, i8*} asm sideeffect "$0 $1 $2 $3 $4 $5 $6",
"=r,=r,=r,r,r,r,r"( i64 %tmp12, i32 %h, i8* %blk1, i8* %blk2 ) nounwind
remove asmparser support for the old getresult instruction, which has been subsumed by extractvalue. llvm-svn: 133247
2011-06-17 14:57:15 +08:00
%tmp6 = extractvalue {i32, i8*, i8*} %mrv, 0
add support for multiple return values in inline asm. This is a step towards PR2094. It now compiles the attached .ll file to: _sad16_sse2: movslq %ecx, %rax ## InlineAsm Start %ecx %rdx %rax %rax %r8d %rdx %rsi ## InlineAsm End ## InlineAsm Start set %eax ## InlineAsm End ret which is pretty decent for a 3 output, 4 input asm. llvm-svn: 50386
2008-04-29 12:29:54 +08:00
%tmp7 = call i32 asm sideeffect "set $0",
"=r,~{dirflag},~{fpsr},~{flags}"( ) nounwind
ret i32 %tmp7
}
make the vector conversion magic handle multiple results. We now compile test2/test3 to: _test2: ## InlineAsm Start set %xmm0, %xmm1 ## InlineAsm End addps %xmm1, %xmm0 ret _test3: ## InlineAsm Start set %xmm0, %xmm1 ## InlineAsm End paddd %xmm1, %xmm0 ret as expected. llvm-svn: 50389
2008-04-29 12:48:56 +08:00
define <4 x float> @test2() nounwind {
%mrv = call {<4 x float>, <4 x float>} asm "set $0, $1", "=x,=x"()
remove asmparser support for the old getresult instruction, which has been subsumed by extractvalue. llvm-svn: 133247
2011-06-17 14:57:15 +08:00
%a = extractvalue {<4 x float>, <4 x float>} %mrv, 0
%b = extractvalue {<4 x float>, <4 x float>} %mrv, 1
Split the Add, Sub, and Mul instruction opcodes into separate integer and floating-point opcodes, introducing FAdd, FSub, and FMul. For now, the AsmParser, BitcodeReader, and IRBuilder all preserve backwards compatability, and the Core LLVM APIs preserve backwards compatibility for IR producers. Most front-ends won't need to change immediately. This implements the first step of the plan outlined here: http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt llvm-svn: 72897
2009-06-05 06:49:04 +08:00
%c = fadd <4 x float> %a, %b
make the vector conversion magic handle multiple results. We now compile test2/test3 to: _test2: ## InlineAsm Start set %xmm0, %xmm1 ## InlineAsm End addps %xmm1, %xmm0 ret _test3: ## InlineAsm Start set %xmm0, %xmm1 ## InlineAsm End paddd %xmm1, %xmm0 ret as expected. llvm-svn: 50389
2008-04-29 12:48:56 +08:00
ret <4 x float> %c
}
define <4 x i32> @test3() nounwind {
%mrv = call {<4 x i32>, <4 x i32>} asm "set $0, $1", "=x,=x"()
remove asmparser support for the old getresult instruction, which has been subsumed by extractvalue. llvm-svn: 133247
2011-06-17 14:57:15 +08:00
%a = extractvalue {<4 x i32>, <4 x i32>} %mrv, 0
%b = extractvalue {<4 x i32>, <4 x i32>} %mrv, 1
make the vector conversion magic handle multiple results. We now compile test2/test3 to: _test2: ## InlineAsm Start set %xmm0, %xmm1 ## InlineAsm End addps %xmm1, %xmm0 ret _test3: ## InlineAsm Start set %xmm0, %xmm1 ## InlineAsm End paddd %xmm1, %xmm0 ret as expected. llvm-svn: 50389
2008-04-29 12:48:56 +08:00
%c = add <4 x i32> %a, %b
ret <4 x i32> %c
}