2016-10-25 03:49:43 +08:00
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//===-- WebAssemblyUtilities.cpp - WebAssembly Utility Functions ----------===//
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//
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2019-01-19 16:50:56 +08:00
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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2016-10-25 03:49:43 +08:00
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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2018-05-01 23:54:18 +08:00
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/// This file implements several utility functions for WebAssembly.
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2016-10-25 03:49:43 +08:00
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///
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//===----------------------------------------------------------------------===//
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#include "WebAssemblyUtilities.h"
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#include "WebAssemblyMachineFunctionInfo.h"
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#include "llvm/CodeGen/MachineInstr.h"
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2017-02-28 06:38:58 +08:00
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#include "llvm/CodeGen/MachineLoopInfo.h"
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2016-10-25 03:49:43 +08:00
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using namespace llvm;
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2018-06-19 08:32:03 +08:00
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const char *const WebAssembly::ClangCallTerminateFn = "__clang_call_terminate";
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const char *const WebAssembly::CxaBeginCatchFn = "__cxa_begin_catch";
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const char *const WebAssembly::CxaRethrowFn = "__cxa_rethrow";
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const char *const WebAssembly::StdTerminateFn = "_ZSt9terminatev";
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const char *const WebAssembly::PersonalityWrapperFn =
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"_Unwind_Wasm_CallPersonality";
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2016-10-25 03:49:43 +08:00
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bool WebAssembly::isArgument(const MachineInstr &MI) {
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switch (MI.getOpcode()) {
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2018-10-13 15:09:10 +08:00
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case WebAssembly::ARGUMENT_i32:
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case WebAssembly::ARGUMENT_i32_S:
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case WebAssembly::ARGUMENT_i64:
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case WebAssembly::ARGUMENT_i64_S:
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case WebAssembly::ARGUMENT_f32:
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case WebAssembly::ARGUMENT_f32_S:
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case WebAssembly::ARGUMENT_f64:
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case WebAssembly::ARGUMENT_f64_S:
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2016-10-25 03:49:43 +08:00
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case WebAssembly::ARGUMENT_v16i8:
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2018-08-27 23:45:51 +08:00
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case WebAssembly::ARGUMENT_v16i8_S:
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2016-10-25 03:49:43 +08:00
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case WebAssembly::ARGUMENT_v8i16:
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2018-08-27 23:45:51 +08:00
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case WebAssembly::ARGUMENT_v8i16_S:
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2016-10-25 03:49:43 +08:00
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case WebAssembly::ARGUMENT_v4i32:
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2018-08-27 23:45:51 +08:00
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case WebAssembly::ARGUMENT_v4i32_S:
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2018-08-08 05:24:01 +08:00
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case WebAssembly::ARGUMENT_v2i64:
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2018-08-27 23:45:51 +08:00
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case WebAssembly::ARGUMENT_v2i64_S:
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2016-10-25 03:49:43 +08:00
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case WebAssembly::ARGUMENT_v4f32:
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2018-08-27 23:45:51 +08:00
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case WebAssembly::ARGUMENT_v4f32_S:
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2018-08-08 05:24:01 +08:00
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case WebAssembly::ARGUMENT_v2f64:
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2018-08-27 23:45:51 +08:00
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case WebAssembly::ARGUMENT_v2f64_S:
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2016-10-25 03:49:43 +08:00
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return true;
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default:
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return false;
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}
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}
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bool WebAssembly::isCopy(const MachineInstr &MI) {
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switch (MI.getOpcode()) {
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case WebAssembly::COPY_I32:
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2018-08-27 23:45:51 +08:00
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case WebAssembly::COPY_I32_S:
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2016-10-25 03:49:43 +08:00
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case WebAssembly::COPY_I64:
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2018-08-27 23:45:51 +08:00
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case WebAssembly::COPY_I64_S:
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2016-10-25 03:49:43 +08:00
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case WebAssembly::COPY_F32:
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2018-08-27 23:45:51 +08:00
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case WebAssembly::COPY_F32_S:
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2016-10-25 03:49:43 +08:00
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case WebAssembly::COPY_F64:
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2018-08-27 23:45:51 +08:00
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case WebAssembly::COPY_F64_S:
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2018-08-31 06:10:43 +08:00
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case WebAssembly::COPY_V128:
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case WebAssembly::COPY_V128_S:
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2016-10-25 03:49:43 +08:00
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return true;
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default:
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return false;
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}
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}
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bool WebAssembly::isTee(const MachineInstr &MI) {
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switch (MI.getOpcode()) {
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case WebAssembly::TEE_I32:
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2018-08-27 23:45:51 +08:00
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case WebAssembly::TEE_I32_S:
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2016-10-25 03:49:43 +08:00
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case WebAssembly::TEE_I64:
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2018-08-27 23:45:51 +08:00
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case WebAssembly::TEE_I64_S:
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2016-10-25 03:49:43 +08:00
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case WebAssembly::TEE_F32:
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2018-08-27 23:45:51 +08:00
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case WebAssembly::TEE_F32_S:
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2016-10-25 03:49:43 +08:00
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case WebAssembly::TEE_F64:
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2018-08-27 23:45:51 +08:00
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case WebAssembly::TEE_F64_S:
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2018-08-31 06:10:43 +08:00
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case WebAssembly::TEE_V128:
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case WebAssembly::TEE_V128_S:
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2016-10-25 03:49:43 +08:00
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return true;
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default:
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return false;
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}
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}
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/// Test whether MI is a child of some other node in an expression tree.
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bool WebAssembly::isChild(const MachineInstr &MI,
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const WebAssemblyFunctionInfo &MFI) {
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if (MI.getNumOperands() == 0)
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return false;
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const MachineOperand &MO = MI.getOperand(0);
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if (!MO.isReg() || MO.isImplicit() || !MO.isDef())
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return false;
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unsigned Reg = MO.getReg();
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return TargetRegisterInfo::isVirtualRegister(Reg) &&
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MFI.isVRegStackified(Reg);
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}
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2017-02-25 07:18:00 +08:00
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2018-06-19 08:32:03 +08:00
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bool WebAssembly::isCallDirect(const MachineInstr &MI) {
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switch (MI.getOpcode()) {
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case WebAssembly::CALL_VOID:
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2018-08-27 23:45:51 +08:00
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case WebAssembly::CALL_VOID_S:
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2018-06-19 08:32:03 +08:00
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case WebAssembly::CALL_I32:
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2018-08-27 23:45:51 +08:00
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case WebAssembly::CALL_I32_S:
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2018-06-19 08:32:03 +08:00
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case WebAssembly::CALL_I64:
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2018-08-27 23:45:51 +08:00
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case WebAssembly::CALL_I64_S:
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2018-06-19 08:32:03 +08:00
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case WebAssembly::CALL_F32:
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2018-08-27 23:45:51 +08:00
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case WebAssembly::CALL_F32_S:
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2018-06-19 08:32:03 +08:00
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case WebAssembly::CALL_F64:
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2018-08-27 23:45:51 +08:00
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case WebAssembly::CALL_F64_S:
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2018-06-19 08:32:03 +08:00
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case WebAssembly::CALL_v16i8:
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2018-08-27 23:45:51 +08:00
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case WebAssembly::CALL_v16i8_S:
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2018-06-19 08:32:03 +08:00
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case WebAssembly::CALL_v8i16:
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2018-08-27 23:45:51 +08:00
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case WebAssembly::CALL_v8i16_S:
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2018-06-19 08:32:03 +08:00
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case WebAssembly::CALL_v4i32:
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2018-08-27 23:45:51 +08:00
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case WebAssembly::CALL_v4i32_S:
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2018-08-08 05:24:01 +08:00
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case WebAssembly::CALL_v2i64:
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2018-08-27 23:45:51 +08:00
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case WebAssembly::CALL_v2i64_S:
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2018-06-19 08:32:03 +08:00
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case WebAssembly::CALL_v4f32:
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2018-08-27 23:45:51 +08:00
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case WebAssembly::CALL_v4f32_S:
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2018-08-08 05:24:01 +08:00
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case WebAssembly::CALL_v2f64:
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2018-08-27 23:45:51 +08:00
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case WebAssembly::CALL_v2f64_S:
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2018-06-19 08:32:03 +08:00
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case WebAssembly::CALL_EXCEPT_REF:
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2018-08-27 23:45:51 +08:00
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case WebAssembly::CALL_EXCEPT_REF_S:
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2018-06-19 08:32:03 +08:00
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return true;
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default:
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return false;
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}
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}
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2017-02-25 07:18:00 +08:00
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bool WebAssembly::isCallIndirect(const MachineInstr &MI) {
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switch (MI.getOpcode()) {
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case WebAssembly::CALL_INDIRECT_VOID:
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2018-08-27 23:45:51 +08:00
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case WebAssembly::CALL_INDIRECT_VOID_S:
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2017-02-25 07:18:00 +08:00
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case WebAssembly::CALL_INDIRECT_I32:
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2018-08-27 23:45:51 +08:00
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case WebAssembly::CALL_INDIRECT_I32_S:
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2017-02-25 07:18:00 +08:00
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case WebAssembly::CALL_INDIRECT_I64:
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2018-08-27 23:45:51 +08:00
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case WebAssembly::CALL_INDIRECT_I64_S:
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2017-02-25 07:18:00 +08:00
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case WebAssembly::CALL_INDIRECT_F32:
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2018-08-27 23:45:51 +08:00
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case WebAssembly::CALL_INDIRECT_F32_S:
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2017-02-25 07:18:00 +08:00
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case WebAssembly::CALL_INDIRECT_F64:
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2018-08-27 23:45:51 +08:00
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case WebAssembly::CALL_INDIRECT_F64_S:
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2017-02-25 07:18:00 +08:00
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case WebAssembly::CALL_INDIRECT_v16i8:
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2018-08-27 23:45:51 +08:00
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case WebAssembly::CALL_INDIRECT_v16i8_S:
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2017-02-25 07:18:00 +08:00
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case WebAssembly::CALL_INDIRECT_v8i16:
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2018-08-27 23:45:51 +08:00
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case WebAssembly::CALL_INDIRECT_v8i16_S:
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2017-02-25 07:18:00 +08:00
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case WebAssembly::CALL_INDIRECT_v4i32:
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2018-08-27 23:45:51 +08:00
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case WebAssembly::CALL_INDIRECT_v4i32_S:
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2018-08-08 05:24:01 +08:00
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case WebAssembly::CALL_INDIRECT_v2i64:
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2018-08-27 23:45:51 +08:00
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case WebAssembly::CALL_INDIRECT_v2i64_S:
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2017-02-25 07:18:00 +08:00
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case WebAssembly::CALL_INDIRECT_v4f32:
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2018-08-27 23:45:51 +08:00
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case WebAssembly::CALL_INDIRECT_v4f32_S:
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2018-08-08 05:24:01 +08:00
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case WebAssembly::CALL_INDIRECT_v2f64:
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2018-08-27 23:45:51 +08:00
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case WebAssembly::CALL_INDIRECT_v2f64_S:
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2018-06-19 08:32:03 +08:00
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case WebAssembly::CALL_INDIRECT_EXCEPT_REF:
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2018-08-27 23:45:51 +08:00
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case WebAssembly::CALL_INDIRECT_EXCEPT_REF_S:
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2018-06-19 08:32:03 +08:00
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return true;
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default:
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return false;
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}
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}
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unsigned WebAssembly::getCalleeOpNo(const MachineInstr &MI) {
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switch (MI.getOpcode()) {
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case WebAssembly::CALL_VOID:
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2018-08-27 23:45:51 +08:00
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case WebAssembly::CALL_VOID_S:
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2018-06-19 08:32:03 +08:00
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case WebAssembly::CALL_INDIRECT_VOID:
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2018-08-27 23:45:51 +08:00
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case WebAssembly::CALL_INDIRECT_VOID_S:
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2018-06-19 08:32:03 +08:00
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return 0;
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case WebAssembly::CALL_I32:
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2018-08-27 23:45:51 +08:00
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case WebAssembly::CALL_I32_S:
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2018-06-19 08:32:03 +08:00
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case WebAssembly::CALL_I64:
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2018-08-27 23:45:51 +08:00
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case WebAssembly::CALL_I64_S:
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2018-06-19 08:32:03 +08:00
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case WebAssembly::CALL_F32:
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2018-08-27 23:45:51 +08:00
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case WebAssembly::CALL_F32_S:
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2018-06-19 08:32:03 +08:00
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case WebAssembly::CALL_F64:
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2018-08-27 23:45:51 +08:00
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case WebAssembly::CALL_F64_S:
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2018-08-31 06:10:43 +08:00
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case WebAssembly::CALL_v16i8:
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case WebAssembly::CALL_v16i8_S:
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case WebAssembly::CALL_v8i16:
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case WebAssembly::CALL_v8i16_S:
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case WebAssembly::CALL_v4i32:
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case WebAssembly::CALL_v4i32_S:
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case WebAssembly::CALL_v2i64:
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case WebAssembly::CALL_v2i64_S:
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case WebAssembly::CALL_v4f32:
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case WebAssembly::CALL_v4f32_S:
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case WebAssembly::CALL_v2f64:
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case WebAssembly::CALL_v2f64_S:
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2018-06-19 08:32:03 +08:00
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case WebAssembly::CALL_EXCEPT_REF:
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2018-08-27 23:45:51 +08:00
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case WebAssembly::CALL_EXCEPT_REF_S:
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2018-06-19 08:32:03 +08:00
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case WebAssembly::CALL_INDIRECT_I32:
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2018-08-27 23:45:51 +08:00
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case WebAssembly::CALL_INDIRECT_I32_S:
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2018-06-19 08:32:03 +08:00
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case WebAssembly::CALL_INDIRECT_I64:
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2018-08-27 23:45:51 +08:00
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case WebAssembly::CALL_INDIRECT_I64_S:
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2018-06-19 08:32:03 +08:00
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case WebAssembly::CALL_INDIRECT_F32:
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2018-08-27 23:45:51 +08:00
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case WebAssembly::CALL_INDIRECT_F32_S:
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2018-06-19 08:32:03 +08:00
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case WebAssembly::CALL_INDIRECT_F64:
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2018-08-27 23:45:51 +08:00
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case WebAssembly::CALL_INDIRECT_F64_S:
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2018-08-31 06:10:43 +08:00
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case WebAssembly::CALL_INDIRECT_v16i8:
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case WebAssembly::CALL_INDIRECT_v16i8_S:
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case WebAssembly::CALL_INDIRECT_v8i16:
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case WebAssembly::CALL_INDIRECT_v8i16_S:
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case WebAssembly::CALL_INDIRECT_v4i32:
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case WebAssembly::CALL_INDIRECT_v4i32_S:
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case WebAssembly::CALL_INDIRECT_v2i64:
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case WebAssembly::CALL_INDIRECT_v2i64_S:
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case WebAssembly::CALL_INDIRECT_v4f32:
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case WebAssembly::CALL_INDIRECT_v4f32_S:
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case WebAssembly::CALL_INDIRECT_v2f64:
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case WebAssembly::CALL_INDIRECT_v2f64_S:
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2018-06-19 08:32:03 +08:00
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case WebAssembly::CALL_INDIRECT_EXCEPT_REF:
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2018-08-27 23:45:51 +08:00
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case WebAssembly::CALL_INDIRECT_EXCEPT_REF_S:
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2018-06-19 08:32:03 +08:00
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return 1;
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default:
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llvm_unreachable("Not a call instruction");
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}
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}
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bool WebAssembly::isMarker(const MachineInstr &MI) {
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switch (MI.getOpcode()) {
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case WebAssembly::BLOCK:
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2018-08-27 23:45:51 +08:00
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case WebAssembly::BLOCK_S:
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2018-06-19 08:32:03 +08:00
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case WebAssembly::END_BLOCK:
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2018-08-27 23:45:51 +08:00
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case WebAssembly::END_BLOCK_S:
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2018-06-19 08:32:03 +08:00
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case WebAssembly::LOOP:
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2018-08-27 23:45:51 +08:00
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case WebAssembly::LOOP_S:
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2018-06-19 08:32:03 +08:00
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case WebAssembly::END_LOOP:
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2018-08-27 23:45:51 +08:00
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case WebAssembly::END_LOOP_S:
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2018-06-19 08:32:03 +08:00
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case WebAssembly::TRY:
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2018-08-27 23:45:51 +08:00
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case WebAssembly::TRY_S:
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2018-06-19 08:32:03 +08:00
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case WebAssembly::END_TRY:
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2018-08-27 23:45:51 +08:00
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case WebAssembly::END_TRY_S:
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2018-06-19 08:32:03 +08:00
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return true;
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default:
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return false;
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}
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}
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bool WebAssembly::mayThrow(const MachineInstr &MI) {
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switch (MI.getOpcode()) {
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[WebAssembly] Exception handling: Switch to the new proposal
Summary:
This switches the EH implementation to the new proposal:
https://github.com/WebAssembly/exception-handling/blob/master/proposals/Exceptions.md
(The previous proposal was
https://github.com/WebAssembly/exception-handling/blob/master/proposals/old/Exceptions.md)
- Instruction changes
- Now we have one single `catch` instruction that returns a except_ref
value
- `throw` now can take variable number of operations
- `rethrow` does not have 'depth' argument anymore
- `br_on_exn` queries an except_ref to see if it matches the tag and
branches to the given label if true.
- `extract_exception` is a pseudo instruction that simulates popping
values from wasm stack. This is to make `br_on_exn`, a very special
instruction, work: `br_on_exn` puts values onto the stack only if it
is taken, and the # of values can vay depending on the tag.
- Now there's only one `catch` per `try`, this patch removes all special
handling for terminate pad with a call to `__clang_call_terminate`.
Before it was the only case there are two catch clauses (a normal
`catch` and `catch_all` per `try`).
- Make `rethrow` act as a terminator like `throw`. This splits BB after
`rethrow` in WasmEHPrepare, and deletes an unnecessary `unreachable`
after `rethrow` in LateEHPrepare.
- Now we stop at all catchpads (because we add wasm `catch` instruction
that catches all exceptions), this creates new
`findWasmUnwindDestinations` function in SelectionDAGBuilder.
- Now we use `br_on_exn` instrution to figure out if an except_ref
matches the current tag or not, LateEHPrepare generates this sequence
for catch pads:
```
catch
block i32
br_on_exn $__cpp_exception
end_block
extract_exception
```
- Branch analysis for `br_on_exn` in WebAssemblyInstrInfo
- Other various misc. changes to switch to the new proposal.
Reviewers: dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D57134
llvm-svn: 352598
2019-01-30 11:21:57 +08:00
|
|
|
case WebAssembly::THROW:
|
|
|
|
case WebAssembly::THROW_S:
|
2018-06-19 08:32:03 +08:00
|
|
|
case WebAssembly::RETHROW:
|
2018-08-27 23:45:51 +08:00
|
|
|
case WebAssembly::RETHROW_S:
|
2018-06-19 08:32:03 +08:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
if (isCallIndirect(MI))
|
|
|
|
return true;
|
|
|
|
if (!MI.isCall())
|
|
|
|
return false;
|
|
|
|
|
|
|
|
const MachineOperand &MO = MI.getOperand(getCalleeOpNo(MI));
|
|
|
|
assert(MO.isGlobal());
|
|
|
|
const auto *F = dyn_cast<Function>(MO.getGlobal());
|
|
|
|
if (!F)
|
|
|
|
return true;
|
|
|
|
if (F->doesNotThrow())
|
|
|
|
return false;
|
|
|
|
// These functions never throw
|
|
|
|
if (F->getName() == CxaBeginCatchFn || F->getName() == PersonalityWrapperFn ||
|
|
|
|
F->getName() == ClangCallTerminateFn || F->getName() == StdTerminateFn)
|
|
|
|
return false;
|
|
|
|
return true;
|
|
|
|
}
|