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llvm-project/llvm/test/CodeGen/Mips/llvm-ir/sub.ll

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[mips] Add tests for bitwise binary and integer arithmetic operators. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7125 llvm-svn: 227087
2015-01-26 20:04:40 +08:00
; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \
Reland "[mips] Fix multiprecision arithmetic." For multiprecision arithmetic on MIPS, rather than using ISD::ADDE / ISD::ADDC, get SelectionDAG to break down the operation into ISD::ADDs and ISD::SETCCs. For MIPS, only the DSP ASE has a carry flag, so in the general case it is not useful to directly support ISD::{ADDE, ADDC, SUBE, SUBC} nodes. Also improve the generation code in such cases for targets with TargetLoweringBase::ZeroOrOneBooleanContent by directly using the result of the comparison node rather than using it in selects. Similarly for ISD::SUBE / ISD::SUBC. Address optimization breakage by moving the generation of MIPS specific integer multiply-accumulate nodes to before legalization. This revolves PR32713 and PR33424. Thanks to Simonas Kazlauskas and Pirama Arumuga Nainar for reporting the issue! Reviewers: slthakur Differential Revision: https://reviews.llvm.org/D33494 The previous version of this patch was too aggressive in producing fused integer multiple-addition instructions. llvm-svn: 307906
2017-07-13 19:28:05 +08:00
; RUN: -check-prefixes=NOT-R2-R6,GP32,GP32-NOT-MM,NOT-MM,PRE4
[mips] Add tests for bitwise binary and integer arithmetic operators. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7125 llvm-svn: 227087
2015-01-26 20:04:40 +08:00
; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
[mips] Use --check-prefixes where appropriate. NFC. llvm-svn: 273669
2016-06-24 20:23:17 +08:00
; RUN: -check-prefixes=NOT-R2-R6,GP32,GP32-NOT-MM,NOT-MM
[mips] Add tests for bitwise binary and integer arithmetic operators. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7125 llvm-svn: 227087
2015-01-26 20:04:40 +08:00
; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
[mips] Use --check-prefixes where appropriate. NFC. llvm-svn: 273669
2016-06-24 20:23:17 +08:00
; RUN: -check-prefixes=R2-R6,GP32,GP32-NOT-MM,NOT-MM
[mips] Add backend support for Mips32r[35] and Mips64r[35]. Summary: These ISA's didn't add any instructions so they are almost identical to Mips32r2 and Mips64r2. Even the ELF e_flags are the same, However the ISA revision in .MIPS.abiflags is 3 or 5 respectively instead of 2. Reviewers: vmedic Reviewed By: vmedic Subscribers: tomatabacu, llvm-commits, atanasyan Differential Revision: http://reviews.llvm.org/D7381 llvm-svn: 229695
2015-02-19 00:24:50 +08:00
; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \
[mips] Use --check-prefixes where appropriate. NFC. llvm-svn: 273669
2016-06-24 20:23:17 +08:00
; RUN: -check-prefixes=R2-R6,GP32,GP32-NOT-MM,NOT-MM
[mips] Add backend support for Mips32r[35] and Mips64r[35]. Summary: These ISA's didn't add any instructions so they are almost identical to Mips32r2 and Mips64r2. Even the ELF e_flags are the same, However the ISA revision in .MIPS.abiflags is 3 or 5 respectively instead of 2. Reviewers: vmedic Reviewed By: vmedic Subscribers: tomatabacu, llvm-commits, atanasyan Differential Revision: http://reviews.llvm.org/D7381 llvm-svn: 229695
2015-02-19 00:24:50 +08:00
; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \
[mips] Use --check-prefixes where appropriate. NFC. llvm-svn: 273669
2016-06-24 20:23:17 +08:00
; RUN: -check-prefixes=R2-R6,GP32,GP32-NOT-MM,NOT-MM
[mips] Add tests for bitwise binary and integer arithmetic operators. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7125 llvm-svn: 227087
2015-01-26 20:04:40 +08:00
; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
[mips] Use --check-prefixes where appropriate. NFC. llvm-svn: 273669
2016-06-24 20:23:17 +08:00
; RUN: -check-prefixes=R2-R6,GP32,GP32-NOT-MM,NOT-MM
[mips][microMIPS] Adding code size reduction pass for MicroMIPS Author: milena.vujosevic.janicic Reviewers: sdardis The code implements size reduction pass for MicroMIPS. Load and store instructions are examined and transformed, if possible. lw32 instruction is transformed into 16-bit instruction lwsp sw32 instruction is transformed into 16-bit instruction swsp Arithmetic instrcutions are examined and transformed, if possible. addu32 instruction is transformed into 16-bit instruction addu16 subu32 instruction is transformed into 16-bit instruction subu16 Differential Revision: https://reviews.llvm.org/D15144 llvm-svn: 301540
2017-04-27 21:10:48 +08:00
; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -verify-machineinstrs | FileCheck %s \
Reland "[mips] Fix multiprecision arithmetic." For multiprecision arithmetic on MIPS, rather than using ISD::ADDE / ISD::ADDC, get SelectionDAG to break down the operation into ISD::ADDs and ISD::SETCCs. For MIPS, only the DSP ASE has a carry flag, so in the general case it is not useful to directly support ISD::{ADDE, ADDC, SUBE, SUBC} nodes. Also improve the generation code in such cases for targets with TargetLoweringBase::ZeroOrOneBooleanContent by directly using the result of the comparison node rather than using it in selects. Similarly for ISD::SUBE / ISD::SUBC. Address optimization breakage by moving the generation of MIPS specific integer multiply-accumulate nodes to before legalization. This revolves PR32713 and PR33424. Thanks to Simonas Kazlauskas and Pirama Arumuga Nainar for reporting the issue! Reviewers: slthakur Differential Revision: https://reviews.llvm.org/D33494 The previous version of this patch was too aggressive in producing fused integer multiple-addition instructions. llvm-svn: 307906
2017-07-13 19:28:05 +08:00
; RUN: -check-prefixes=GP32-MM,GP32,MM32,MMR3
[mips][microMIPS] Add CodeGen support for SUBU16, SUB, SUBU, DSUB and DSUBU instructions Differential Revision: http://reviews.llvm.org/D16676 llvm-svn: 267694
2016-04-27 19:31:44 +08:00
; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \
Reland "[mips] Fix multiprecision arithmetic." For multiprecision arithmetic on MIPS, rather than using ISD::ADDE / ISD::ADDC, get SelectionDAG to break down the operation into ISD::ADDs and ISD::SETCCs. For MIPS, only the DSP ASE has a carry flag, so in the general case it is not useful to directly support ISD::{ADDE, ADDC, SUBE, SUBC} nodes. Also improve the generation code in such cases for targets with TargetLoweringBase::ZeroOrOneBooleanContent by directly using the result of the comparison node rather than using it in selects. Similarly for ISD::SUBE / ISD::SUBC. Address optimization breakage by moving the generation of MIPS specific integer multiply-accumulate nodes to before legalization. This revolves PR32713 and PR33424. Thanks to Simonas Kazlauskas and Pirama Arumuga Nainar for reporting the issue! Reviewers: slthakur Differential Revision: https://reviews.llvm.org/D33494 The previous version of this patch was too aggressive in producing fused integer multiple-addition instructions. llvm-svn: 307906
2017-07-13 19:28:05 +08:00
; RUN: -check-prefixes=GP32-MM,GP32,MM32,MMR6
[mips] Add tests for bitwise binary and integer arithmetic operators. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7125 llvm-svn: 227087
2015-01-26 20:04:40 +08:00
; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
Reland "[mips] Fix multiprecision arithmetic." For multiprecision arithmetic on MIPS, rather than using ISD::ADDE / ISD::ADDC, get SelectionDAG to break down the operation into ISD::ADDs and ISD::SETCCs. For MIPS, only the DSP ASE has a carry flag, so in the general case it is not useful to directly support ISD::{ADDE, ADDC, SUBE, SUBC} nodes. Also improve the generation code in such cases for targets with TargetLoweringBase::ZeroOrOneBooleanContent by directly using the result of the comparison node rather than using it in selects. Similarly for ISD::SUBE / ISD::SUBC. Address optimization breakage by moving the generation of MIPS specific integer multiply-accumulate nodes to before legalization. This revolves PR32713 and PR33424. Thanks to Simonas Kazlauskas and Pirama Arumuga Nainar for reporting the issue! Reviewers: slthakur Differential Revision: https://reviews.llvm.org/D33494 The previous version of this patch was too aggressive in producing fused integer multiple-addition instructions. llvm-svn: 307906
2017-07-13 19:28:05 +08:00
; RUN: -check-prefixes=NOT-R2-R6,GP64,NOT-MM,GP64-NOT-R2
[mips] Add tests for bitwise binary and integer arithmetic operators. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7125 llvm-svn: 227087
2015-01-26 20:04:40 +08:00
; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \
Reland "[mips] Fix multiprecision arithmetic." For multiprecision arithmetic on MIPS, rather than using ISD::ADDE / ISD::ADDC, get SelectionDAG to break down the operation into ISD::ADDs and ISD::SETCCs. For MIPS, only the DSP ASE has a carry flag, so in the general case it is not useful to directly support ISD::{ADDE, ADDC, SUBE, SUBC} nodes. Also improve the generation code in such cases for targets with TargetLoweringBase::ZeroOrOneBooleanContent by directly using the result of the comparison node rather than using it in selects. Similarly for ISD::SUBE / ISD::SUBC. Address optimization breakage by moving the generation of MIPS specific integer multiply-accumulate nodes to before legalization. This revolves PR32713 and PR33424. Thanks to Simonas Kazlauskas and Pirama Arumuga Nainar for reporting the issue! Reviewers: slthakur Differential Revision: https://reviews.llvm.org/D33494 The previous version of this patch was too aggressive in producing fused integer multiple-addition instructions. llvm-svn: 307906
2017-07-13 19:28:05 +08:00
; RUN: -check-prefixes=NOT-R2-R6,GP64,NOT-MM,GP64-NOT-R2
[mips] Add tests for bitwise binary and integer arithmetic operators. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7125 llvm-svn: 227087
2015-01-26 20:04:40 +08:00
; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
Reland "[mips] Fix multiprecision arithmetic." For multiprecision arithmetic on MIPS, rather than using ISD::ADDE / ISD::ADDC, get SelectionDAG to break down the operation into ISD::ADDs and ISD::SETCCs. For MIPS, only the DSP ASE has a carry flag, so in the general case it is not useful to directly support ISD::{ADDE, ADDC, SUBE, SUBC} nodes. Also improve the generation code in such cases for targets with TargetLoweringBase::ZeroOrOneBooleanContent by directly using the result of the comparison node rather than using it in selects. Similarly for ISD::SUBE / ISD::SUBC. Address optimization breakage by moving the generation of MIPS specific integer multiply-accumulate nodes to before legalization. This revolves PR32713 and PR33424. Thanks to Simonas Kazlauskas and Pirama Arumuga Nainar for reporting the issue! Reviewers: slthakur Differential Revision: https://reviews.llvm.org/D33494 The previous version of this patch was too aggressive in producing fused integer multiple-addition instructions. llvm-svn: 307906
2017-07-13 19:28:05 +08:00
; RUN: -check-prefixes=NOT-R2-R6,GP64,NOT-MM,GP64-NOT-R2
[mips] Add tests for bitwise binary and integer arithmetic operators. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7125 llvm-svn: 227087
2015-01-26 20:04:40 +08:00
; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
Reland "[mips] Fix multiprecision arithmetic." For multiprecision arithmetic on MIPS, rather than using ISD::ADDE / ISD::ADDC, get SelectionDAG to break down the operation into ISD::ADDs and ISD::SETCCs. For MIPS, only the DSP ASE has a carry flag, so in the general case it is not useful to directly support ISD::{ADDE, ADDC, SUBE, SUBC} nodes. Also improve the generation code in such cases for targets with TargetLoweringBase::ZeroOrOneBooleanContent by directly using the result of the comparison node rather than using it in selects. Similarly for ISD::SUBE / ISD::SUBC. Address optimization breakage by moving the generation of MIPS specific integer multiply-accumulate nodes to before legalization. This revolves PR32713 and PR33424. Thanks to Simonas Kazlauskas and Pirama Arumuga Nainar for reporting the issue! Reviewers: slthakur Differential Revision: https://reviews.llvm.org/D33494 The previous version of this patch was too aggressive in producing fused integer multiple-addition instructions. llvm-svn: 307906
2017-07-13 19:28:05 +08:00
; RUN: -check-prefixes=R2-R6,GP64,NOT-MM,GP64-R2
[mips] Add backend support for Mips32r[35] and Mips64r[35]. Summary: These ISA's didn't add any instructions so they are almost identical to Mips32r2 and Mips64r2. Even the ELF e_flags are the same, However the ISA revision in .MIPS.abiflags is 3 or 5 respectively instead of 2. Reviewers: vmedic Reviewed By: vmedic Subscribers: tomatabacu, llvm-commits, atanasyan Differential Revision: http://reviews.llvm.org/D7381 llvm-svn: 229695
2015-02-19 00:24:50 +08:00
; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
Reland "[mips] Fix multiprecision arithmetic." For multiprecision arithmetic on MIPS, rather than using ISD::ADDE / ISD::ADDC, get SelectionDAG to break down the operation into ISD::ADDs and ISD::SETCCs. For MIPS, only the DSP ASE has a carry flag, so in the general case it is not useful to directly support ISD::{ADDE, ADDC, SUBE, SUBC} nodes. Also improve the generation code in such cases for targets with TargetLoweringBase::ZeroOrOneBooleanContent by directly using the result of the comparison node rather than using it in selects. Similarly for ISD::SUBE / ISD::SUBC. Address optimization breakage by moving the generation of MIPS specific integer multiply-accumulate nodes to before legalization. This revolves PR32713 and PR33424. Thanks to Simonas Kazlauskas and Pirama Arumuga Nainar for reporting the issue! Reviewers: slthakur Differential Revision: https://reviews.llvm.org/D33494 The previous version of this patch was too aggressive in producing fused integer multiple-addition instructions. llvm-svn: 307906
2017-07-13 19:28:05 +08:00
; RUN: -check-prefixes=R2-R6,GP64,NOT-MM,GP64-R2
[mips] Add backend support for Mips32r[35] and Mips64r[35]. Summary: These ISA's didn't add any instructions so they are almost identical to Mips32r2 and Mips64r2. Even the ELF e_flags are the same, However the ISA revision in .MIPS.abiflags is 3 or 5 respectively instead of 2. Reviewers: vmedic Reviewed By: vmedic Subscribers: tomatabacu, llvm-commits, atanasyan Differential Revision: http://reviews.llvm.org/D7381 llvm-svn: 229695
2015-02-19 00:24:50 +08:00
; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
Reland "[mips] Fix multiprecision arithmetic." For multiprecision arithmetic on MIPS, rather than using ISD::ADDE / ISD::ADDC, get SelectionDAG to break down the operation into ISD::ADDs and ISD::SETCCs. For MIPS, only the DSP ASE has a carry flag, so in the general case it is not useful to directly support ISD::{ADDE, ADDC, SUBE, SUBC} nodes. Also improve the generation code in such cases for targets with TargetLoweringBase::ZeroOrOneBooleanContent by directly using the result of the comparison node rather than using it in selects. Similarly for ISD::SUBE / ISD::SUBC. Address optimization breakage by moving the generation of MIPS specific integer multiply-accumulate nodes to before legalization. This revolves PR32713 and PR33424. Thanks to Simonas Kazlauskas and Pirama Arumuga Nainar for reporting the issue! Reviewers: slthakur Differential Revision: https://reviews.llvm.org/D33494 The previous version of this patch was too aggressive in producing fused integer multiple-addition instructions. llvm-svn: 307906
2017-07-13 19:28:05 +08:00
; RUN: -check-prefixes=R2-R6,GP64,NOT-MM,GP64-R2
[mips] Add tests for bitwise binary and integer arithmetic operators. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7125 llvm-svn: 227087
2015-01-26 20:04:40 +08:00
; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
Reland "[mips] Fix multiprecision arithmetic." For multiprecision arithmetic on MIPS, rather than using ISD::ADDE / ISD::ADDC, get SelectionDAG to break down the operation into ISD::ADDs and ISD::SETCCs. For MIPS, only the DSP ASE has a carry flag, so in the general case it is not useful to directly support ISD::{ADDE, ADDC, SUBE, SUBC} nodes. Also improve the generation code in such cases for targets with TargetLoweringBase::ZeroOrOneBooleanContent by directly using the result of the comparison node rather than using it in selects. Similarly for ISD::SUBE / ISD::SUBC. Address optimization breakage by moving the generation of MIPS specific integer multiply-accumulate nodes to before legalization. This revolves PR32713 and PR33424. Thanks to Simonas Kazlauskas and Pirama Arumuga Nainar for reporting the issue! Reviewers: slthakur Differential Revision: https://reviews.llvm.org/D33494 The previous version of this patch was too aggressive in producing fused integer multiple-addition instructions. llvm-svn: 307906
2017-07-13 19:28:05 +08:00
; RUN: -check-prefixes=R2-R6,GP64,NOT-MM,GP64-R2
[mips] Add tests for bitwise binary and integer arithmetic operators. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7125 llvm-svn: 227087
2015-01-26 20:04:40 +08:00
define signext i1 @sub_i1(i1 signext %a, i1 signext %b) {
entry:
; ALL-LABEL: sub_i1:
[mips][microMIPS] Add CodeGen support for SUBU16, SUB, SUBU, DSUB and DSUBU instructions Differential Revision: http://reviews.llvm.org/D16676 llvm-svn: 267694
2016-04-27 19:31:44 +08:00
; NOT-MM: subu $[[T0:[0-9]+]], $4, $5
[DAG] optimize negation of bool Use mask and negate for legalization of i1 source type with SIGN_EXTEND_INREG. With the mask, this should be no worse than 2 shifts. The mask can be eliminated in some cases, so that should be better than 2 shifts. This change exposed some missing folds related to negation: https://reviews.llvm.org/rL284239 https://reviews.llvm.org/rL284395 There may be others, so please let me know if you see any regressions. Differential Revision: https://reviews.llvm.org/D25485 llvm-svn: 284611
2016-10-20 00:58:59 +08:00
; NOT-MM: andi $[[T0]], $[[T0]], 1
; NOT-MM: negu $2, $[[T0]]
[mips][microMIPS] Add CodeGen support for SUBU16, SUB, SUBU, DSUB and DSUBU instructions Differential Revision: http://reviews.llvm.org/D16676 llvm-svn: 267694
2016-04-27 19:31:44 +08:00
; MM: subu16 $[[T0:[0-9]+]], $4, $5
[DAG] optimize negation of bool Use mask and negate for legalization of i1 source type with SIGN_EXTEND_INREG. With the mask, this should be no worse than 2 shifts. The mask can be eliminated in some cases, so that should be better than 2 shifts. This change exposed some missing folds related to negation: https://reviews.llvm.org/rL284239 https://reviews.llvm.org/rL284395 There may be others, so please let me know if you see any regressions. Differential Revision: https://reviews.llvm.org/D25485 llvm-svn: 284611
2016-10-20 00:58:59 +08:00
; MM: andi16 $[[T0]], $[[T0]], 1
; MM: li16 $[[T1:[0-9]+]], 0
; MM: subu16 $2, $[[T1]], $[[T0]]
[mips] Add tests for bitwise binary and integer arithmetic operators. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7125 llvm-svn: 227087
2015-01-26 20:04:40 +08:00
%r = sub i1 %a, %b
ret i1 %r
}
define signext i8 @sub_i8(i8 signext %a, i8 signext %b) {
entry:
; ALL-LABEL: sub_i8:
; NOT-R2-R6: subu $[[T0:[0-9]+]], $4, $5
; NOT-R2-R6: sll $[[T0]], $[[T0]], 24
; NOT-R2-R6: sra $2, $[[T0]], 24
; R2-R6: subu $[[T0:[0-9]+]], $4, $5
; R2-R6: seb $2, $[[T0:[0-9]+]]
[mips][microMIPS] Add CodeGen support for SUBU16, SUB, SUBU, DSUB and DSUBU instructions Differential Revision: http://reviews.llvm.org/D16676 llvm-svn: 267694
2016-04-27 19:31:44 +08:00
; MM: subu16 $[[T0:[0-9]+]], $4, $5
; MM: seb $[[T0]], $[[T0]]
[mips] Add tests for bitwise binary and integer arithmetic operators. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7125 llvm-svn: 227087
2015-01-26 20:04:40 +08:00
%r = sub i8 %a, %b
ret i8 %r
}
define signext i16 @sub_i16(i16 signext %a, i16 signext %b) {
entry:
; ALL-LABEL: sub_i16:
; NOT-R2-R6: subu $[[T0:[0-9]+]], $4, $5
; NOT-R2-R6: sll $[[T0]], $[[T0]], 16
; NOT-R2-R6: sra $2, $[[T0]], 16
; R2-R6: subu $[[T0:[0-9]+]], $4, $5
; R2-R6: seh $2, $[[T0:[0-9]+]]
[mips][microMIPS] Add CodeGen support for SUBU16, SUB, SUBU, DSUB and DSUBU instructions Differential Revision: http://reviews.llvm.org/D16676 llvm-svn: 267694
2016-04-27 19:31:44 +08:00
; MM: subu16 $[[T0:[0-9]+]], $4, $5
; MM: seh $[[T0]], $[[T0]]
[mips] Add tests for bitwise binary and integer arithmetic operators. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7125 llvm-svn: 227087
2015-01-26 20:04:40 +08:00
%r = sub i16 %a, %b
ret i16 %r
}
define signext i32 @sub_i32(i32 signext %a, i32 signext %b) {
entry:
; ALL-LABEL: sub_i32:
[mips][microMIPS] Add CodeGen support for SUBU16, SUB, SUBU, DSUB and DSUBU instructions Differential Revision: http://reviews.llvm.org/D16676 llvm-svn: 267694
2016-04-27 19:31:44 +08:00
; NOT-MM: subu $2, $4, $5
; MM: subu16 $2, $4, $5
[mips] Add tests for bitwise binary and integer arithmetic operators. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7125 llvm-svn: 227087
2015-01-26 20:04:40 +08:00
%r = sub i32 %a, %b
ret i32 %r
}
define signext i64 @sub_i64(i64 signext %a, i64 signext %b) {
entry:
; ALL-LABEL: sub_i64:
Reland "[mips] Fix multiprecision arithmetic." For multiprecision arithmetic on MIPS, rather than using ISD::ADDE / ISD::ADDC, get SelectionDAG to break down the operation into ISD::ADDs and ISD::SETCCs. For MIPS, only the DSP ASE has a carry flag, so in the general case it is not useful to directly support ISD::{ADDE, ADDC, SUBE, SUBC} nodes. Also improve the generation code in such cases for targets with TargetLoweringBase::ZeroOrOneBooleanContent by directly using the result of the comparison node rather than using it in selects. Similarly for ISD::SUBE / ISD::SUBC. Address optimization breakage by moving the generation of MIPS specific integer multiply-accumulate nodes to before legalization. This revolves PR32713 and PR33424. Thanks to Simonas Kazlauskas and Pirama Arumuga Nainar for reporting the issue! Reviewers: slthakur Differential Revision: https://reviews.llvm.org/D33494 The previous version of this patch was too aggressive in producing fused integer multiple-addition instructions. llvm-svn: 307906
2017-07-13 19:28:05 +08:00
; GP32-NOT-MM: sltu $[[T0:[0-9]+]], $5, $7
; GP32-NOT-MM: subu $2, $4, $6
; GP32-NOT-MM: subu $2, $2, $[[T0]]
; GP32-NOT-MM: subu $3, $5, $7
; MM32: sltu $[[T0:[0-9]+]], $5, $7
; MM32: subu16 $3, $4, $6
; MM32: subu16 $2, $3, $[[T0]]
; MM32: subu16 $3, $5, $7
[mips] Add tests for bitwise binary and integer arithmetic operators. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7125 llvm-svn: 227087
2015-01-26 20:04:40 +08:00
; GP64: dsubu $2, $4, $5
%r = sub i64 %a, %b
ret i64 %r
}
[mips] Enable arithmetic and binary operations for the i128 data type. Summary: This patch adds support for some operations that were missing from 128-bit integer types (add/sub/mul/sdiv/udiv... etc.). With these changes we can support the __int128_t and __uint128_t data types from C/C++. Depends on D7125 Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7143 llvm-svn: 227089
2015-01-26 20:33:22 +08:00
define signext i128 @sub_i128(i128 signext %a, i128 signext %b) {
entry:
; ALL-LABEL: sub_i128:
Reland "[mips] Fix multiprecision arithmetic." For multiprecision arithmetic on MIPS, rather than using ISD::ADDE / ISD::ADDC, get SelectionDAG to break down the operation into ISD::ADDs and ISD::SETCCs. For MIPS, only the DSP ASE has a carry flag, so in the general case it is not useful to directly support ISD::{ADDE, ADDC, SUBE, SUBC} nodes. Also improve the generation code in such cases for targets with TargetLoweringBase::ZeroOrOneBooleanContent by directly using the result of the comparison node rather than using it in selects. Similarly for ISD::SUBE / ISD::SUBC. Address optimization breakage by moving the generation of MIPS specific integer multiply-accumulate nodes to before legalization. This revolves PR32713 and PR33424. Thanks to Simonas Kazlauskas and Pirama Arumuga Nainar for reporting the issue! Reviewers: slthakur Differential Revision: https://reviews.llvm.org/D33494 The previous version of this patch was too aggressive in producing fused integer multiple-addition instructions. llvm-svn: 307906
2017-07-13 19:28:05 +08:00
; PRE4: lw $[[T0:[0-9]+]], 24($sp)
; PRE4: lw $[[T1:[0-9]+]], 28($sp)
; PRE4: sltu $[[T2:[0-9]+]], $7, $[[T1]]
; PRE4: xor $[[T3:[0-9]+]], $6, $[[T0]]
; PRE4: sltiu $[[T4:[0-9]+]], $[[T3]], 1
; PRE4: bnez $[[T4]]
; PRE4: move $[[T5:[0-9]+]], $[[T2]]
; PRE4: sltu $[[T5]], $6, $[[T0]]
; PRE4: lw $[[T6:[0-9]+]], 20($sp)
; PRE4: subu $[[T7:[0-9]+]], $5, $[[T6]]
; PRE4: subu $[[T8:[0-9]+]], $[[T7]], $[[T5]]
; PRE4: sltu $[[T9:[0-9]+]], $[[T7]], $[[T5]]
; PRE4: sltu $[[T10:[0-9]+]], $5, $[[T6]]
; PRE4: lw $[[T11:[0-9]+]], 16($sp)
; PRE4: subu $[[T12:[0-9]+]], $4, $[[T11]]
; PRE4: subu $[[T13:[0-9]+]], $[[T12]], $[[T10]]
; PRE4: subu $[[T14:[0-9]+]], $[[T13]], $[[T9]]
; PRE4: subu $[[T15:[0-9]+]], $6, $[[T0]]
; PRE4: subu $[[T16:[0-9]+]], $[[T15]], $[[T2]]
; PRE4: subu $5, $7, $[[T1]]
; MMR3: lw $[[T1:[0-9]+]], 48($sp)
; MMR3: sltu $[[T2:[0-9]+]], $6, $[[T1]]
; MMR3: xor $[[T3:[0-9]+]], $6, $[[T1]]
; MMR3: lw $[[T4:[0-9]+]], 52($sp)
; MMR3: sltu $[[T5:[0-9]+]], $7, $[[T4]]
; MMR3: movz $[[T6:[0-9]+]], $[[T5]], $[[T3]]
; MMR3: lw $[[T7:[0-8]+]], 44($sp)
; MMR3: subu16 $[[T8:[0-9]+]], $5, $[[T7]]
; MMR3: subu16 $[[T9:[0-9]+]], $[[T8]], $[[T6]]
; MMR3: sltu $[[T10:[0-9]+]], $[[T8]], $[[T2]]
; MMR3: sltu $[[T11:[0-9]+]], $5, $[[T7]]
; MMR3: lw $[[T12:[0-9]+]], 40($sp)
; MMR3: lw $[[T13:[0-9]+]], 12($sp)
; MMR3: subu16 $[[T14:[0-9]+]], $[[T13]], $[[T12]]
; MMR3: subu16 $[[T15:[0-9]+]], $[[T14]], $[[T11]]
; MMR3: subu16 $[[T16:[0-9]+]], $[[T15]], $[[T10]]
; MMR3: subu16 $[[T17:[0-9]+]], $6, $[[T1]]
; MMR3: subu16 $[[T18:[0-9]+]], $[[T17]], $7
; MMR3: lw $[[T19:[0-9]+]], 8($sp)
; MMR3: lw $[[T20:[0-9]+]], 0($sp)
; MMR3: subu16 $5, $[[T19]], $[[T20]]
; MMR6: move $[[T0:[0-9]+]], $7
Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding" Re-enable commit r323991 now that r325931 has been committed to make MachineOperand::isRenamable() check more conservative w.r.t. code changes and opt-in on a per-target basis. llvm-svn: 326208
2018-02-28 00:59:10 +08:00
; MMR6: sw $7, 8($sp)
Reland "[mips] Fix multiprecision arithmetic." For multiprecision arithmetic on MIPS, rather than using ISD::ADDE / ISD::ADDC, get SelectionDAG to break down the operation into ISD::ADDs and ISD::SETCCs. For MIPS, only the DSP ASE has a carry flag, so in the general case it is not useful to directly support ISD::{ADDE, ADDC, SUBE, SUBC} nodes. Also improve the generation code in such cases for targets with TargetLoweringBase::ZeroOrOneBooleanContent by directly using the result of the comparison node rather than using it in selects. Similarly for ISD::SUBE / ISD::SUBC. Address optimization breakage by moving the generation of MIPS specific integer multiply-accumulate nodes to before legalization. This revolves PR32713 and PR33424. Thanks to Simonas Kazlauskas and Pirama Arumuga Nainar for reporting the issue! Reviewers: slthakur Differential Revision: https://reviews.llvm.org/D33494 The previous version of this patch was too aggressive in producing fused integer multiple-addition instructions. llvm-svn: 307906
2017-07-13 19:28:05 +08:00
; MMR6: move $[[T1:[0-9]+]], $5
; MMR6: sw $4, 12($sp)
; MMR6: lw $[[T2:[0-9]+]], 48($sp)
; MMR6: sltu $[[T3:[0-9]+]], $6, $[[T2]]
; MMR6: xor $[[T4:[0-9]+]], $6, $[[T2]]
; MMR6: sltiu $[[T5:[0-9]+]], $[[T4]], 1
; MMR6: seleqz $[[T6:[0-9]+]], $[[T3]], $[[T5]]
; MMR6: lw $[[T7:[0-9]+]], 52($sp)
; MMR6: sltu $[[T8:[0-9]+]], $[[T0]], $[[T7]]
; MMR6: selnez $[[T9:[0-9]+]], $[[T8]], $[[T5]]
; MMR6: or $[[T10:[0-9]+]], $[[T9]], $[[T6]]
; MMR6: lw $[[T11:[0-9]+]], 44($sp)
; MMR6: subu16 $[[T12:[0-9]+]], $[[T1]], $[[T11]]
; MMR6: subu16 $[[T13:[0-9]+]], $[[T12]], $[[T7]]
; MMR6: sltu $[[T16:[0-9]+]], $[[T12]], $[[T7]]
; MMR6: sltu $[[T17:[0-9]+]], $[[T1]], $[[T11]]
; MMR6: lw $[[T18:[0-9]+]], 40($sp)
; MMR6: lw $[[T19:[0-9]+]], 12($sp)
; MMR6: subu16 $[[T20:[0-9]+]], $[[T19]], $[[T18]]
; MMR6: subu16 $[[T21:[0-9]+]], $[[T20]], $[[T17]]
; MMR6: subu16 $[[T22:[0-9]+]], $[[T21]], $[[T16]]
; MMR6: subu16 $[[T23:[0-9]+]], $6, $[[T2]]
; MMR6: subu16 $4, $[[T23]], $5
; MMR6: lw $[[T24:[0-9]+]], 8($sp)
; MMR6: lw $[[T25:[0-9]+]], 0($sp)
; MMR6: subu16 $5, $[[T24]], $[[T25]]
; MMR6: lw $3, 4($sp)
; FIXME: The sltu, dsll, dsrl pattern here occurs when an i32 is zero
; extended to 64 bits. Fortunately slt(i)(u) actually gives an i1.
; These should be combined away.
; GP64-NOT-R2: dsubu $1, $4, $6
; GP64-NOT-R2: sltu $[[T0:[0-9]+]], $5, $7
; GP64-NOT-R2: dsll $[[T1:[0-9]+]], $[[T0]], 32
; GP64-NOT-R2: dsrl $[[T2:[0-9]+]], $[[T1]], 32
; GP64-NOT-R2: dsubu $2, $1, $[[T2]]
; GP64-NOT-R2: dsubu $3, $5, $7
; FIXME: Likewise for the sltu, dext here.
; GP64-R2: dsubu $1, $4, $6
; GP64-R2: sltu $[[T0:[0-9]+]], $5, $7
; GP64-R2: dext $[[T1:[0-9]+]], $[[T0]], 0, 32
; GP64-R2: dsubu $2, $1, $[[T1]]
; GP64-R2: dsubu $3, $5, $7
[mips] Enable arithmetic and binary operations for the i128 data type. Summary: This patch adds support for some operations that were missing from 128-bit integer types (add/sub/mul/sdiv/udiv... etc.). With these changes we can support the __int128_t and __uint128_t data types from C/C++. Depends on D7125 Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7143 llvm-svn: 227089
2015-01-26 20:33:22 +08:00
%r = sub i128 %a, %b
ret i128 %r
}