Initial commit of the machine code LICM pass. It successfully hoists this:
_foo:
li r2, 0
LBB1_1: ; bb
li r5, 0
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
to:
_foo:
li r2, 0
li r5, 0
LBB1_1: ; bb
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
ZOMG!! :-)
Moar to come...
llvm-svn: 44687
2007-12-08 05:42:31 +08:00
|
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|
//===-- MachineLICM.cpp - Machine Loop Invariant Code Motion Pass ---------===//
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//
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// The LLVM Compiler Infrastructure
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//
|
2007-12-30 04:36:04 +08:00
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|
// This file is distributed under the University of Illinois Open Source
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|
// License. See LICENSE.TXT for details.
|
Initial commit of the machine code LICM pass. It successfully hoists this:
_foo:
li r2, 0
LBB1_1: ; bb
li r5, 0
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
to:
_foo:
li r2, 0
li r5, 0
LBB1_1: ; bb
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
ZOMG!! :-)
Moar to come...
llvm-svn: 44687
2007-12-08 05:42:31 +08:00
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//
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//===----------------------------------------------------------------------===//
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//
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// This pass performs loop invariant code motion on machine instructions. We
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// attempt to remove as much code from the body of a loop as possible.
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//
|
2009-01-16 06:01:38 +08:00
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// This pass does not attempt to throttle itself to limit register pressure.
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// The register allocation phases are expected to perform rematerialization
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// to recover when register pressure is high.
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//
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// This pass is not intended to be a replacement or a complete alternative
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// for the LLVM-IR-level LICM pass. It is only designed to hoist simple
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// constructs that are not exposed before lowering and instruction selection.
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//
|
Initial commit of the machine code LICM pass. It successfully hoists this:
_foo:
li r2, 0
LBB1_1: ; bb
li r5, 0
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
to:
_foo:
li r2, 0
li r5, 0
LBB1_1: ; bb
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
ZOMG!! :-)
Moar to come...
llvm-svn: 44687
2007-12-08 05:42:31 +08:00
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "machine-licm"
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2008-01-04 14:41:45 +08:00
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#include "llvm/CodeGen/Passes.h"
|
Initial commit of the machine code LICM pass. It successfully hoists this:
_foo:
li r2, 0
LBB1_1: ; bb
li r5, 0
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
to:
_foo:
li r2, 0
li r5, 0
LBB1_1: ; bb
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
ZOMG!! :-)
Moar to come...
llvm-svn: 44687
2007-12-08 05:42:31 +08:00
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#include "llvm/CodeGen/MachineDominators.h"
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2010-04-07 08:41:17 +08:00
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#include "llvm/CodeGen/MachineFrameInfo.h"
|
Initial commit of the machine code LICM pass. It successfully hoists this:
_foo:
li r2, 0
LBB1_1: ; bb
li r5, 0
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
to:
_foo:
li r2, 0
li r5, 0
LBB1_1: ; bb
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
ZOMG!! :-)
Moar to come...
llvm-svn: 44687
2007-12-08 05:42:31 +08:00
|
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#include "llvm/CodeGen/MachineLoopInfo.h"
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2009-10-28 11:21:57 +08:00
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#include "llvm/CodeGen/MachineMemOperand.h"
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2008-01-03 03:32:43 +08:00
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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2009-10-28 11:21:57 +08:00
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#include "llvm/CodeGen/PseudoSourceValue.h"
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2008-02-11 02:45:23 +08:00
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#include "llvm/Target/TargetRegisterInfo.h"
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2007-12-12 07:27:51 +08:00
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#include "llvm/Target/TargetInstrInfo.h"
|
Initial commit of the machine code LICM pass. It successfully hoists this:
_foo:
li r2, 0
LBB1_1: ; bb
li r5, 0
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
to:
_foo:
li r2, 0
li r5, 0
LBB1_1: ; bb
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
ZOMG!! :-)
Moar to come...
llvm-svn: 44687
2007-12-08 05:42:31 +08:00
|
|
|
#include "llvm/Target/TargetMachine.h"
|
2009-10-08 01:38:06 +08:00
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|
#include "llvm/Analysis/AliasAnalysis.h"
|
2009-02-05 16:45:46 +08:00
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|
#include "llvm/ADT/DenseMap.h"
|
2010-04-07 08:41:17 +08:00
|
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|
#include "llvm/ADT/SmallSet.h"
|
2008-01-04 14:41:45 +08:00
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#include "llvm/ADT/Statistic.h"
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#include "llvm/Support/Debug.h"
|
2009-07-25 08:23:56 +08:00
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|
#include "llvm/Support/raw_ostream.h"
|
Initial commit of the machine code LICM pass. It successfully hoists this:
_foo:
li r2, 0
LBB1_1: ; bb
li r5, 0
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
to:
_foo:
li r2, 0
li r5, 0
LBB1_1: ; bb
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
ZOMG!! :-)
Moar to come...
llvm-svn: 44687
2007-12-08 05:42:31 +08:00
|
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|
using namespace llvm;
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|
2007-12-09 07:58:46 +08:00
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STATISTIC(NumHoisted, "Number of machine instructions hoisted out of loops");
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2009-02-05 16:45:46 +08:00
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|
STATISTIC(NumCSEed, "Number of hoisted machine instructions CSEed");
|
2010-04-07 08:41:17 +08:00
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|
STATISTIC(NumPostRAHoisted,
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|
"Number of machine instructions hoisted out of loops post regalloc");
|
2007-12-08 09:47:01 +08:00
|
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|
|
Initial commit of the machine code LICM pass. It successfully hoists this:
_foo:
li r2, 0
LBB1_1: ; bb
li r5, 0
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
to:
_foo:
li r2, 0
li r5, 0
LBB1_1: ; bb
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
ZOMG!! :-)
Moar to come...
llvm-svn: 44687
2007-12-08 05:42:31 +08:00
|
|
|
namespace {
|
2009-10-25 14:33:48 +08:00
|
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|
class MachineLICM : public MachineFunctionPass {
|
2010-04-07 08:41:17 +08:00
|
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|
bool PreRegAlloc;
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|
|
|
|
2008-01-03 03:32:43 +08:00
|
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|
const TargetMachine *TM;
|
2007-12-12 07:27:51 +08:00
|
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|
const TargetInstrInfo *TII;
|
2009-09-26 07:58:45 +08:00
|
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|
const TargetRegisterInfo *TRI;
|
2010-04-07 08:41:17 +08:00
|
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|
const MachineFrameInfo *MFI;
|
|
|
|
MachineRegisterInfo *RegInfo;
|
2007-12-12 03:40:06 +08:00
|
|
|
|
Initial commit of the machine code LICM pass. It successfully hoists this:
_foo:
li r2, 0
LBB1_1: ; bb
li r5, 0
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
to:
_foo:
li r2, 0
li r5, 0
LBB1_1: ; bb
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
ZOMG!! :-)
Moar to come...
llvm-svn: 44687
2007-12-08 05:42:31 +08:00
|
|
|
// Various analyses that we use...
|
2009-10-08 01:38:06 +08:00
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|
AliasAnalysis *AA; // Alias analysis info.
|
2010-04-08 09:03:47 +08:00
|
|
|
MachineLoopInfo *MLI; // Current MachineLoopInfo
|
2008-05-13 03:38:32 +08:00
|
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|
MachineDominatorTree *DT; // Machine dominator tree for the cur loop
|
Initial commit of the machine code LICM pass. It successfully hoists this:
_foo:
li r2, 0
LBB1_1: ; bb
li r5, 0
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
to:
_foo:
li r2, 0
li r5, 0
LBB1_1: ; bb
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
ZOMG!! :-)
Moar to come...
llvm-svn: 44687
2007-12-08 05:42:31 +08:00
|
|
|
|
|
|
|
// State that is updated as we process loops
|
2008-05-13 03:38:32 +08:00
|
|
|
bool Changed; // True if a loop is changed.
|
|
|
|
MachineLoop *CurLoop; // The current loop we are working on.
|
2009-01-16 06:01:38 +08:00
|
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|
MachineBasicBlock *CurPreheader; // The preheader for CurLoop.
|
2009-02-05 16:45:46 +08:00
|
|
|
|
2010-04-07 08:41:17 +08:00
|
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|
BitVector AllocatableSet;
|
|
|
|
|
2009-11-04 05:40:02 +08:00
|
|
|
// For each opcode, keep a list of potentail CSE instructions.
|
|
|
|
DenseMap<unsigned, std::vector<const MachineInstr*> > CSEMap;
|
2010-04-07 08:41:17 +08:00
|
|
|
|
Initial commit of the machine code LICM pass. It successfully hoists this:
_foo:
li r2, 0
LBB1_1: ; bb
li r5, 0
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
to:
_foo:
li r2, 0
li r5, 0
LBB1_1: ; bb
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
ZOMG!! :-)
Moar to come...
llvm-svn: 44687
2007-12-08 05:42:31 +08:00
|
|
|
public:
|
|
|
|
static char ID; // Pass identification, replacement for typeid
|
2010-04-07 08:41:17 +08:00
|
|
|
MachineLICM() :
|
|
|
|
MachineFunctionPass(&ID), PreRegAlloc(true) {}
|
|
|
|
|
|
|
|
explicit MachineLICM(bool PreRA) :
|
|
|
|
MachineFunctionPass(&ID), PreRegAlloc(PreRA) {}
|
Initial commit of the machine code LICM pass. It successfully hoists this:
_foo:
li r2, 0
LBB1_1: ; bb
li r5, 0
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
to:
_foo:
li r2, 0
li r5, 0
LBB1_1: ; bb
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
ZOMG!! :-)
Moar to come...
llvm-svn: 44687
2007-12-08 05:42:31 +08:00
|
|
|
|
|
|
|
virtual bool runOnMachineFunction(MachineFunction &MF);
|
|
|
|
|
2008-12-18 09:37:56 +08:00
|
|
|
const char *getPassName() const { return "Machine Instruction LICM"; }
|
|
|
|
|
2008-03-10 16:13:01 +08:00
|
|
|
// FIXME: Loop preheaders?
|
Initial commit of the machine code LICM pass. It successfully hoists this:
_foo:
li r2, 0
LBB1_1: ; bb
li r5, 0
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
to:
_foo:
li r2, 0
li r5, 0
LBB1_1: ; bb
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
ZOMG!! :-)
Moar to come...
llvm-svn: 44687
2007-12-08 05:42:31 +08:00
|
|
|
virtual void getAnalysisUsage(AnalysisUsage &AU) const {
|
|
|
|
AU.setPreservesCFG();
|
|
|
|
AU.addRequired<MachineLoopInfo>();
|
|
|
|
AU.addRequired<MachineDominatorTree>();
|
2009-10-08 01:38:06 +08:00
|
|
|
AU.addRequired<AliasAnalysis>();
|
2008-01-04 16:48:49 +08:00
|
|
|
AU.addPreserved<MachineLoopInfo>();
|
|
|
|
AU.addPreserved<MachineDominatorTree>();
|
|
|
|
MachineFunctionPass::getAnalysisUsage(AU);
|
Initial commit of the machine code LICM pass. It successfully hoists this:
_foo:
li r2, 0
LBB1_1: ; bb
li r5, 0
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
to:
_foo:
li r2, 0
li r5, 0
LBB1_1: ; bb
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
ZOMG!! :-)
Moar to come...
llvm-svn: 44687
2007-12-08 05:42:31 +08:00
|
|
|
}
|
2009-02-05 16:45:46 +08:00
|
|
|
|
|
|
|
virtual void releaseMemory() {
|
|
|
|
CSEMap.clear();
|
|
|
|
}
|
|
|
|
|
Initial commit of the machine code LICM pass. It successfully hoists this:
_foo:
li r2, 0
LBB1_1: ; bb
li r5, 0
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
to:
_foo:
li r2, 0
li r5, 0
LBB1_1: ; bb
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
ZOMG!! :-)
Moar to come...
llvm-svn: 44687
2007-12-08 05:42:31 +08:00
|
|
|
private:
|
2010-04-08 09:03:47 +08:00
|
|
|
/// CandidateInfo - Keep track of information about hoisting candidates.
|
|
|
|
struct CandidateInfo {
|
|
|
|
MachineInstr *MI;
|
|
|
|
unsigned Def;
|
2010-04-14 02:16:00 +08:00
|
|
|
int FI;
|
|
|
|
CandidateInfo(MachineInstr *mi, unsigned def, int fi)
|
|
|
|
: MI(mi), Def(def), FI(fi) {}
|
2010-04-08 09:03:47 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
/// HoistRegionPostRA - Walk the specified region of the CFG and hoist loop
|
|
|
|
/// invariants out to the preheader.
|
|
|
|
void HoistRegionPostRA(MachineDomTreeNode *N);
|
|
|
|
|
|
|
|
/// HoistPostRA - When an instruction is found to only use loop invariant
|
|
|
|
/// operands that is safe to hoist, this instruction is called to do the
|
|
|
|
/// dirty work.
|
|
|
|
void HoistPostRA(MachineInstr *MI, unsigned Def);
|
|
|
|
|
|
|
|
/// ProcessMI - Examine the instruction for potentai LICM candidate. Also
|
|
|
|
/// gather register def and frame object update information.
|
|
|
|
void ProcessMI(MachineInstr *MI, unsigned *PhysRegDefs,
|
|
|
|
SmallSet<int, 32> &StoredFIs,
|
|
|
|
SmallVector<CandidateInfo, 32> &Candidates);
|
|
|
|
|
|
|
|
/// AddToLiveIns - Add 'Reg' to the livein sets of BBs in the backedge path
|
|
|
|
/// from MBB to LoopHeader (inclusive).
|
|
|
|
void AddToLiveIns(unsigned Reg,
|
|
|
|
MachineBasicBlock *MBB, MachineBasicBlock *LoopHeader);
|
|
|
|
|
2010-04-14 02:16:00 +08:00
|
|
|
/// IsLICMCandidate - Returns true if the instruction may be a suitable
|
|
|
|
/// candidate for LICM. e.g. If the instruction is a call, then it's obviously
|
|
|
|
/// not safe to hoist it.
|
|
|
|
bool IsLICMCandidate(MachineInstr &I);
|
|
|
|
|
2007-12-09 07:58:46 +08:00
|
|
|
/// IsLoopInvariantInst - Returns true if the instruction is loop
|
Initial commit of the machine code LICM pass. It successfully hoists this:
_foo:
li r2, 0
LBB1_1: ; bb
li r5, 0
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
to:
_foo:
li r2, 0
li r5, 0
LBB1_1: ; bb
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
ZOMG!! :-)
Moar to come...
llvm-svn: 44687
2007-12-08 05:42:31 +08:00
|
|
|
/// invariant. I.e., all virtual register operands are defined outside of
|
|
|
|
/// the loop, physical registers aren't accessed (explicitly or implicitly),
|
|
|
|
/// and the instruction is hoistable.
|
|
|
|
///
|
2007-12-09 07:58:46 +08:00
|
|
|
bool IsLoopInvariantInst(MachineInstr &I);
|
Initial commit of the machine code LICM pass. It successfully hoists this:
_foo:
li r2, 0
LBB1_1: ; bb
li r5, 0
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
to:
_foo:
li r2, 0
li r5, 0
LBB1_1: ; bb
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
ZOMG!! :-)
Moar to come...
llvm-svn: 44687
2007-12-08 05:42:31 +08:00
|
|
|
|
2009-02-04 17:19:56 +08:00
|
|
|
/// IsProfitableToHoist - Return true if it is potentially profitable to
|
|
|
|
/// hoist the given loop invariant.
|
2009-11-21 07:31:34 +08:00
|
|
|
bool IsProfitableToHoist(MachineInstr &MI);
|
2009-02-04 17:19:56 +08:00
|
|
|
|
Initial commit of the machine code LICM pass. It successfully hoists this:
_foo:
li r2, 0
LBB1_1: ; bb
li r5, 0
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
to:
_foo:
li r2, 0
li r5, 0
LBB1_1: ; bb
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
ZOMG!! :-)
Moar to come...
llvm-svn: 44687
2007-12-08 05:42:31 +08:00
|
|
|
/// HoistRegion - Walk the specified region of the CFG (defined by all
|
|
|
|
/// blocks dominated by the specified block, and that are in the current
|
|
|
|
/// loop) in depth first order w.r.t the DominatorTree. This allows us to
|
|
|
|
/// visit definitions before uses, allowing us to hoist a loop body in one
|
|
|
|
/// pass without iteration.
|
|
|
|
///
|
|
|
|
void HoistRegion(MachineDomTreeNode *N);
|
|
|
|
|
2009-11-21 03:55:37 +08:00
|
|
|
/// isLoadFromConstantMemory - Return true if the given instruction is a
|
|
|
|
/// load from constant memory.
|
|
|
|
bool isLoadFromConstantMemory(MachineInstr *MI);
|
|
|
|
|
2009-10-30 01:47:20 +08:00
|
|
|
/// ExtractHoistableLoad - Unfold a load from the given machineinstr if
|
|
|
|
/// the load itself could be hoisted. Return the unfolded and hoistable
|
|
|
|
/// load, or null if the load couldn't be unfolded or if it wouldn't
|
|
|
|
/// be hoistable.
|
|
|
|
MachineInstr *ExtractHoistableLoad(MachineInstr *MI);
|
|
|
|
|
2009-11-07 11:52:02 +08:00
|
|
|
/// LookForDuplicate - Find an instruction amount PrevMIs that is a
|
|
|
|
/// duplicate of MI. Return this instruction if it's found.
|
|
|
|
const MachineInstr *LookForDuplicate(const MachineInstr *MI,
|
|
|
|
std::vector<const MachineInstr*> &PrevMIs);
|
|
|
|
|
2009-11-05 08:51:13 +08:00
|
|
|
/// EliminateCSE - Given a LICM'ed instruction, look for an instruction on
|
|
|
|
/// the preheader that compute the same value. If it's found, do a RAU on
|
|
|
|
/// with the definition of the existing instruction rather than hoisting
|
|
|
|
/// the instruction to the preheader.
|
|
|
|
bool EliminateCSE(MachineInstr *MI,
|
|
|
|
DenseMap<unsigned, std::vector<const MachineInstr*> >::iterator &CI);
|
|
|
|
|
Initial commit of the machine code LICM pass. It successfully hoists this:
_foo:
li r2, 0
LBB1_1: ; bb
li r5, 0
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
to:
_foo:
li r2, 0
li r5, 0
LBB1_1: ; bb
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
ZOMG!! :-)
Moar to come...
llvm-svn: 44687
2007-12-08 05:42:31 +08:00
|
|
|
/// Hoist - When an instruction is found to only use loop invariant operands
|
|
|
|
/// that is safe to hoist, this instruction is called to do the dirty work.
|
|
|
|
///
|
2009-10-28 11:21:57 +08:00
|
|
|
void Hoist(MachineInstr *MI);
|
2009-11-04 05:40:02 +08:00
|
|
|
|
|
|
|
/// InitCSEMap - Initialize the CSE map with instructions that are in the
|
|
|
|
/// current loop preheader that may become duplicates of instructions that
|
|
|
|
/// are hoisted out of the loop.
|
|
|
|
void InitCSEMap(MachineBasicBlock *BB);
|
Initial commit of the machine code LICM pass. It successfully hoists this:
_foo:
li r2, 0
LBB1_1: ; bb
li r5, 0
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
to:
_foo:
li r2, 0
li r5, 0
LBB1_1: ; bb
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
ZOMG!! :-)
Moar to come...
llvm-svn: 44687
2007-12-08 05:42:31 +08:00
|
|
|
};
|
|
|
|
} // end anonymous namespace
|
|
|
|
|
2008-05-13 08:00:25 +08:00
|
|
|
char MachineLICM::ID = 0;
|
|
|
|
static RegisterPass<MachineLICM>
|
2008-07-07 13:42:27 +08:00
|
|
|
X("machinelicm", "Machine Loop Invariant Code Motion");
|
2008-05-13 08:00:25 +08:00
|
|
|
|
2010-04-07 08:41:17 +08:00
|
|
|
FunctionPass *llvm::createMachineLICMPass(bool PreRegAlloc) {
|
|
|
|
return new MachineLICM(PreRegAlloc);
|
|
|
|
}
|
Initial commit of the machine code LICM pass. It successfully hoists this:
_foo:
li r2, 0
LBB1_1: ; bb
li r5, 0
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
to:
_foo:
li r2, 0
li r5, 0
LBB1_1: ; bb
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
ZOMG!! :-)
Moar to come...
llvm-svn: 44687
2007-12-08 05:42:31 +08:00
|
|
|
|
2009-01-16 06:01:38 +08:00
|
|
|
/// LoopIsOuterMostWithPreheader - Test if the given loop is the outer-most
|
|
|
|
/// loop that has a preheader.
|
|
|
|
static bool LoopIsOuterMostWithPreheader(MachineLoop *CurLoop) {
|
|
|
|
for (MachineLoop *L = CurLoop->getParentLoop(); L; L = L->getParentLoop())
|
|
|
|
if (L->getLoopPreheader())
|
|
|
|
return false;
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
Initial commit of the machine code LICM pass. It successfully hoists this:
_foo:
li r2, 0
LBB1_1: ; bb
li r5, 0
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
to:
_foo:
li r2, 0
li r5, 0
LBB1_1: ; bb
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
ZOMG!! :-)
Moar to come...
llvm-svn: 44687
2007-12-08 05:42:31 +08:00
|
|
|
bool MachineLICM::runOnMachineFunction(MachineFunction &MF) {
|
2010-04-07 08:41:17 +08:00
|
|
|
if (PreRegAlloc)
|
|
|
|
DEBUG(dbgs() << "******** Pre-regalloc Machine LICM ********\n");
|
|
|
|
else
|
|
|
|
DEBUG(dbgs() << "******** Post-regalloc Machine LICM ********\n");
|
2007-12-12 06:22:22 +08:00
|
|
|
|
2010-04-08 09:03:47 +08:00
|
|
|
Changed = false;
|
2008-08-31 10:30:23 +08:00
|
|
|
TM = &MF.getTarget();
|
2008-01-03 03:32:43 +08:00
|
|
|
TII = TM->getInstrInfo();
|
2009-09-26 07:58:45 +08:00
|
|
|
TRI = TM->getRegisterInfo();
|
2010-04-07 08:41:17 +08:00
|
|
|
MFI = MF.getFrameInfo();
|
2008-08-31 10:30:23 +08:00
|
|
|
RegInfo = &MF.getRegInfo();
|
2009-09-26 10:34:00 +08:00
|
|
|
AllocatableSet = TRI->getAllocatableSet(MF);
|
Initial commit of the machine code LICM pass. It successfully hoists this:
_foo:
li r2, 0
LBB1_1: ; bb
li r5, 0
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
to:
_foo:
li r2, 0
li r5, 0
LBB1_1: ; bb
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
ZOMG!! :-)
Moar to come...
llvm-svn: 44687
2007-12-08 05:42:31 +08:00
|
|
|
|
|
|
|
// Get our Loop information...
|
2010-04-08 09:03:47 +08:00
|
|
|
MLI = &getAnalysis<MachineLoopInfo>();
|
|
|
|
DT = &getAnalysis<MachineDominatorTree>();
|
|
|
|
AA = &getAnalysis<AliasAnalysis>();
|
Initial commit of the machine code LICM pass. It successfully hoists this:
_foo:
li r2, 0
LBB1_1: ; bb
li r5, 0
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
to:
_foo:
li r2, 0
li r5, 0
LBB1_1: ; bb
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
ZOMG!! :-)
Moar to come...
llvm-svn: 44687
2007-12-08 05:42:31 +08:00
|
|
|
|
2010-04-08 09:03:47 +08:00
|
|
|
for (MachineLoopInfo::iterator I = MLI->begin(), E = MLI->end(); I != E; ++I){
|
2007-12-12 06:22:22 +08:00
|
|
|
CurLoop = *I;
|
Initial commit of the machine code LICM pass. It successfully hoists this:
_foo:
li r2, 0
LBB1_1: ; bb
li r5, 0
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
to:
_foo:
li r2, 0
li r5, 0
LBB1_1: ; bb
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
ZOMG!! :-)
Moar to come...
llvm-svn: 44687
2007-12-08 05:42:31 +08:00
|
|
|
|
2010-04-08 09:03:47 +08:00
|
|
|
// If this is done before regalloc, only visit outer-most preheader-sporting
|
|
|
|
// loops.
|
|
|
|
if (PreRegAlloc && !LoopIsOuterMostWithPreheader(CurLoop))
|
2009-01-16 06:01:38 +08:00
|
|
|
continue;
|
|
|
|
|
|
|
|
// Determine the block to which to hoist instructions. If we can't find a
|
|
|
|
// suitable loop preheader, we can't do any hoisting.
|
|
|
|
//
|
|
|
|
// FIXME: We are only hoisting if the basic block coming into this loop
|
|
|
|
// has only one successor. This isn't the case in general because we haven't
|
|
|
|
// broken critical edges or added preheaders.
|
|
|
|
CurPreheader = CurLoop->getLoopPreheader();
|
|
|
|
if (!CurPreheader)
|
|
|
|
continue;
|
|
|
|
|
2009-11-04 05:40:02 +08:00
|
|
|
// CSEMap is initialized for loop header when the first instruction is
|
|
|
|
// being hoisted.
|
2010-04-07 08:41:17 +08:00
|
|
|
MachineDomTreeNode *N = DT->getNode(CurLoop->getHeader());
|
|
|
|
if (!PreRegAlloc)
|
|
|
|
HoistRegionPostRA(N);
|
|
|
|
else {
|
|
|
|
HoistRegion(N);
|
|
|
|
CSEMap.clear();
|
|
|
|
}
|
Initial commit of the machine code LICM pass. It successfully hoists this:
_foo:
li r2, 0
LBB1_1: ; bb
li r5, 0
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
to:
_foo:
li r2, 0
li r5, 0
LBB1_1: ; bb
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
ZOMG!! :-)
Moar to come...
llvm-svn: 44687
2007-12-08 05:42:31 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
return Changed;
|
|
|
|
}
|
|
|
|
|
2010-04-08 09:03:47 +08:00
|
|
|
/// InstructionStoresToFI - Return true if instruction stores to the
|
|
|
|
/// specified frame.
|
|
|
|
static bool InstructionStoresToFI(const MachineInstr *MI, int FI) {
|
|
|
|
for (MachineInstr::mmo_iterator o = MI->memoperands_begin(),
|
|
|
|
oe = MI->memoperands_end(); o != oe; ++o) {
|
|
|
|
if (!(*o)->isStore() || !(*o)->getValue())
|
|
|
|
continue;
|
|
|
|
if (const FixedStackPseudoSourceValue *Value =
|
|
|
|
dyn_cast<const FixedStackPseudoSourceValue>((*o)->getValue())) {
|
|
|
|
if (Value->getFrameIndex() == FI)
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
/// ProcessMI - Examine the instruction for potentai LICM candidate. Also
|
|
|
|
/// gather register def and frame object update information.
|
|
|
|
void MachineLICM::ProcessMI(MachineInstr *MI,
|
|
|
|
unsigned *PhysRegDefs,
|
|
|
|
SmallSet<int, 32> &StoredFIs,
|
|
|
|
SmallVector<CandidateInfo, 32> &Candidates) {
|
|
|
|
bool RuledOut = false;
|
2010-04-14 04:21:05 +08:00
|
|
|
bool HasNonInvariantUse = false;
|
2010-04-08 09:03:47 +08:00
|
|
|
unsigned Def = 0;
|
|
|
|
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
|
|
|
const MachineOperand &MO = MI->getOperand(i);
|
|
|
|
if (MO.isFI()) {
|
|
|
|
// Remember if the instruction stores to the frame index.
|
|
|
|
int FI = MO.getIndex();
|
|
|
|
if (!StoredFIs.count(FI) &&
|
|
|
|
MFI->isSpillSlotObjectIndex(FI) &&
|
|
|
|
InstructionStoresToFI(MI, FI))
|
|
|
|
StoredFIs.insert(FI);
|
2010-04-14 04:21:05 +08:00
|
|
|
HasNonInvariantUse = true;
|
2010-04-08 09:03:47 +08:00
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!MO.isReg())
|
|
|
|
continue;
|
|
|
|
unsigned Reg = MO.getReg();
|
|
|
|
if (!Reg)
|
|
|
|
continue;
|
|
|
|
assert(TargetRegisterInfo::isPhysicalRegister(Reg) &&
|
|
|
|
"Not expecting virtual register!");
|
|
|
|
|
2010-04-14 02:16:00 +08:00
|
|
|
if (!MO.isDef()) {
|
2010-04-14 06:13:34 +08:00
|
|
|
if (Reg && PhysRegDefs[Reg])
|
2010-04-14 04:21:05 +08:00
|
|
|
// If it's using a non-loop-invariant register, then it's obviously not
|
|
|
|
// safe to hoist.
|
|
|
|
HasNonInvariantUse = true;
|
2010-04-08 09:03:47 +08:00
|
|
|
continue;
|
2010-04-14 02:16:00 +08:00
|
|
|
}
|
2010-04-08 09:03:47 +08:00
|
|
|
|
|
|
|
if (MO.isImplicit()) {
|
|
|
|
++PhysRegDefs[Reg];
|
|
|
|
for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS)
|
|
|
|
++PhysRegDefs[*AS];
|
|
|
|
if (!MO.isDead())
|
|
|
|
// Non-dead implicit def? This cannot be hoisted.
|
|
|
|
RuledOut = true;
|
|
|
|
// No need to check if a dead implicit def is also defined by
|
|
|
|
// another instruction.
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
// FIXME: For now, avoid instructions with multiple defs, unless
|
|
|
|
// it's a dead implicit def.
|
|
|
|
if (Def)
|
|
|
|
RuledOut = true;
|
|
|
|
else
|
|
|
|
Def = Reg;
|
|
|
|
|
|
|
|
// If we have already seen another instruction that defines the same
|
|
|
|
// register, then this is not safe.
|
|
|
|
if (++PhysRegDefs[Reg] > 1)
|
|
|
|
// MI defined register is seen defined by another instruction in
|
|
|
|
// the loop, it cannot be a LICM candidate.
|
|
|
|
RuledOut = true;
|
|
|
|
for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS)
|
|
|
|
if (++PhysRegDefs[*AS] > 1)
|
|
|
|
RuledOut = true;
|
|
|
|
}
|
|
|
|
|
2010-04-14 02:16:00 +08:00
|
|
|
// Only consider reloads for now and remats which do not have register
|
|
|
|
// operands. FIXME: Consider unfold load folding instructions.
|
2010-04-08 09:03:47 +08:00
|
|
|
if (Def && !RuledOut) {
|
2010-04-14 02:16:00 +08:00
|
|
|
int FI = INT_MIN;
|
2010-04-14 04:21:05 +08:00
|
|
|
if ((!HasNonInvariantUse && IsLICMCandidate(*MI)) ||
|
2010-04-14 02:16:00 +08:00
|
|
|
(TII->isLoadFromStackSlot(MI, FI) && MFI->isSpillSlotObjectIndex(FI)))
|
|
|
|
Candidates.push_back(CandidateInfo(MI, Def, FI));
|
2010-04-08 09:03:47 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/// HoistRegionPostRA - Walk the specified region of the CFG and hoist loop
|
|
|
|
/// invariants out to the preheader.
|
2010-04-07 08:41:17 +08:00
|
|
|
void MachineLICM::HoistRegionPostRA(MachineDomTreeNode *N) {
|
|
|
|
assert(N != 0 && "Null dominator tree node?");
|
|
|
|
|
|
|
|
unsigned NumRegs = TRI->getNumRegs();
|
|
|
|
unsigned *PhysRegDefs = new unsigned[NumRegs];
|
|
|
|
std::fill(PhysRegDefs, PhysRegDefs + NumRegs, 0);
|
|
|
|
|
2010-04-08 09:03:47 +08:00
|
|
|
SmallVector<CandidateInfo, 32> Candidates;
|
2010-04-07 08:41:17 +08:00
|
|
|
SmallSet<int, 32> StoredFIs;
|
|
|
|
|
|
|
|
// Walk the entire region, count number of defs for each register, and
|
|
|
|
// return potential LICM candidates.
|
|
|
|
SmallVector<MachineDomTreeNode*, 8> WorkList;
|
|
|
|
WorkList.push_back(N);
|
|
|
|
do {
|
|
|
|
N = WorkList.pop_back_val();
|
|
|
|
MachineBasicBlock *BB = N->getBlock();
|
|
|
|
|
2010-04-08 09:03:47 +08:00
|
|
|
if (!CurLoop->contains(MLI->getLoopFor(BB)))
|
2010-04-07 08:41:17 +08:00
|
|
|
continue;
|
|
|
|
// Conservatively treat live-in's as an external def.
|
2010-04-08 09:03:47 +08:00
|
|
|
// FIXME: That means a reload that're reused in successor block(s) will not
|
|
|
|
// be LICM'ed.
|
2010-04-14 00:57:55 +08:00
|
|
|
for (MachineBasicBlock::livein_iterator I = BB->livein_begin(),
|
2010-04-07 08:41:17 +08:00
|
|
|
E = BB->livein_end(); I != E; ++I) {
|
|
|
|
unsigned Reg = *I;
|
|
|
|
++PhysRegDefs[Reg];
|
2010-04-08 09:03:47 +08:00
|
|
|
for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS)
|
|
|
|
++PhysRegDefs[*AS];
|
2010-04-07 08:41:17 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
for (MachineBasicBlock::iterator
|
|
|
|
MII = BB->begin(), E = BB->end(); MII != E; ++MII) {
|
|
|
|
MachineInstr *MI = &*MII;
|
2010-04-08 09:03:47 +08:00
|
|
|
ProcessMI(MI, PhysRegDefs, StoredFIs, Candidates);
|
2010-04-07 08:41:17 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
const std::vector<MachineDomTreeNode*> &Children = N->getChildren();
|
|
|
|
for (unsigned I = 0, E = Children.size(); I != E; ++I)
|
|
|
|
WorkList.push_back(Children[I]);
|
|
|
|
} while (!WorkList.empty());
|
|
|
|
|
|
|
|
// Now evaluate whether the potential candidates qualify.
|
|
|
|
// 1. Check if the candidate defined register is defined by another
|
|
|
|
// instruction in the loop.
|
|
|
|
// 2. If the candidate is a load from stack slot (always true for now),
|
|
|
|
// check if the slot is stored anywhere in the loop.
|
|
|
|
for (unsigned i = 0, e = Candidates.size(); i != e; ++i) {
|
2010-04-14 02:16:00 +08:00
|
|
|
if (Candidates[i].FI != INT_MIN &&
|
|
|
|
StoredFIs.count(Candidates[i].FI))
|
2010-04-07 08:41:17 +08:00
|
|
|
continue;
|
|
|
|
|
2010-04-14 04:21:05 +08:00
|
|
|
if (PhysRegDefs[Candidates[i].Def] == 1) {
|
|
|
|
bool Safe = true;
|
|
|
|
MachineInstr *MI = Candidates[i].MI;
|
2010-04-14 04:25:29 +08:00
|
|
|
for (unsigned j = 0, ee = MI->getNumOperands(); j != ee; ++j) {
|
|
|
|
const MachineOperand &MO = MI->getOperand(j);
|
2010-04-14 06:13:34 +08:00
|
|
|
if (!MO.isReg() || MO.isDef() || !MO.getReg())
|
2010-04-14 04:21:05 +08:00
|
|
|
continue;
|
|
|
|
if (PhysRegDefs[MO.getReg()]) {
|
|
|
|
// If it's using a non-loop-invariant register, then it's obviously
|
|
|
|
// not safe to hoist.
|
|
|
|
Safe = false;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (Safe)
|
|
|
|
HoistPostRA(MI, Candidates[i].Def);
|
|
|
|
}
|
2010-04-07 08:41:17 +08:00
|
|
|
}
|
2010-04-12 19:38:35 +08:00
|
|
|
|
|
|
|
delete[] PhysRegDefs;
|
2010-04-07 08:41:17 +08:00
|
|
|
}
|
|
|
|
|
2010-04-08 09:03:47 +08:00
|
|
|
/// AddToLiveIns - Add register 'Reg' to the livein sets of BBs in the
|
|
|
|
/// backedge path from MBB to LoopHeader.
|
|
|
|
void MachineLICM::AddToLiveIns(unsigned Reg, MachineBasicBlock *MBB,
|
|
|
|
MachineBasicBlock *LoopHeader) {
|
|
|
|
SmallPtrSet<MachineBasicBlock*, 4> Visited;
|
|
|
|
SmallVector<MachineBasicBlock*, 4> WorkList;
|
|
|
|
WorkList.push_back(MBB);
|
|
|
|
do {
|
|
|
|
MBB = WorkList.pop_back_val();
|
|
|
|
if (!Visited.insert(MBB))
|
|
|
|
continue;
|
|
|
|
MBB->addLiveIn(Reg);
|
|
|
|
if (MBB == LoopHeader)
|
|
|
|
continue;
|
|
|
|
for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(),
|
|
|
|
E = MBB->pred_end(); PI != E; ++PI)
|
|
|
|
WorkList.push_back(*PI);
|
|
|
|
} while (!WorkList.empty());
|
|
|
|
}
|
|
|
|
|
|
|
|
/// HoistPostRA - When an instruction is found to only use loop invariant
|
|
|
|
/// operands that is safe to hoist, this instruction is called to do the
|
|
|
|
/// dirty work.
|
|
|
|
void MachineLICM::HoistPostRA(MachineInstr *MI, unsigned Def) {
|
2010-04-07 08:41:17 +08:00
|
|
|
// Now move the instructions to the predecessor, inserting it before any
|
|
|
|
// terminator instructions.
|
|
|
|
DEBUG({
|
|
|
|
dbgs() << "Hoisting " << *MI;
|
|
|
|
if (CurPreheader->getBasicBlock())
|
|
|
|
dbgs() << " to MachineBasicBlock "
|
|
|
|
<< CurPreheader->getName();
|
|
|
|
if (MI->getParent()->getBasicBlock())
|
|
|
|
dbgs() << " from MachineBasicBlock "
|
|
|
|
<< MI->getParent()->getName();
|
|
|
|
dbgs() << "\n";
|
|
|
|
});
|
|
|
|
|
|
|
|
// Splice the instruction to the preheader.
|
2010-04-08 09:03:47 +08:00
|
|
|
MachineBasicBlock *MBB = MI->getParent();
|
|
|
|
CurPreheader->splice(CurPreheader->getFirstTerminator(), MBB, MI);
|
|
|
|
|
|
|
|
// Add register to livein list to BBs in the path from loop header to original
|
|
|
|
// BB. Note, currently it's not necessary to worry about adding it to all BB's
|
|
|
|
// with uses. Reload that're reused in successor block(s) are not being
|
|
|
|
// hoisted.
|
|
|
|
AddToLiveIns(Def, MBB, CurLoop->getHeader());
|
2010-04-07 08:41:17 +08:00
|
|
|
|
|
|
|
++NumPostRAHoisted;
|
|
|
|
Changed = true;
|
|
|
|
}
|
|
|
|
|
Initial commit of the machine code LICM pass. It successfully hoists this:
_foo:
li r2, 0
LBB1_1: ; bb
li r5, 0
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
to:
_foo:
li r2, 0
li r5, 0
LBB1_1: ; bb
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
ZOMG!! :-)
Moar to come...
llvm-svn: 44687
2007-12-08 05:42:31 +08:00
|
|
|
/// HoistRegion - Walk the specified region of the CFG (defined by all blocks
|
|
|
|
/// dominated by the specified block, and that are in the current loop) in depth
|
|
|
|
/// first order w.r.t the DominatorTree. This allows us to visit definitions
|
|
|
|
/// before uses, allowing us to hoist a loop body in one pass without iteration.
|
|
|
|
///
|
|
|
|
void MachineLICM::HoistRegion(MachineDomTreeNode *N) {
|
|
|
|
assert(N != 0 && "Null dominator tree node?");
|
|
|
|
MachineBasicBlock *BB = N->getBlock();
|
|
|
|
|
|
|
|
// If this subregion is not in the top level loop at all, exit.
|
|
|
|
if (!CurLoop->contains(BB)) return;
|
|
|
|
|
2009-01-16 06:01:38 +08:00
|
|
|
for (MachineBasicBlock::iterator
|
2009-02-05 16:45:46 +08:00
|
|
|
MII = BB->begin(), E = BB->end(); MII != E; ) {
|
|
|
|
MachineBasicBlock::iterator NextMII = MII; ++NextMII;
|
2009-11-04 05:40:02 +08:00
|
|
|
Hoist(&*MII);
|
2009-02-05 16:45:46 +08:00
|
|
|
MII = NextMII;
|
2009-01-16 06:01:38 +08:00
|
|
|
}
|
Initial commit of the machine code LICM pass. It successfully hoists this:
_foo:
li r2, 0
LBB1_1: ; bb
li r5, 0
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
to:
_foo:
li r2, 0
li r5, 0
LBB1_1: ; bb
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
ZOMG!! :-)
Moar to come...
llvm-svn: 44687
2007-12-08 05:42:31 +08:00
|
|
|
|
|
|
|
const std::vector<MachineDomTreeNode*> &Children = N->getChildren();
|
|
|
|
for (unsigned I = 0, E = Children.size(); I != E; ++I)
|
|
|
|
HoistRegion(Children[I]);
|
|
|
|
}
|
|
|
|
|
2010-04-14 02:16:00 +08:00
|
|
|
/// IsLICMCandidate - Returns true if the instruction may be a suitable
|
|
|
|
/// candidate for LICM. e.g. If the instruction is a call, then it's obviously
|
|
|
|
/// not safe to hoist it.
|
|
|
|
bool MachineLICM::IsLICMCandidate(MachineInstr &I) {
|
2010-04-14 06:13:34 +08:00
|
|
|
if (I.isImplicitDef())
|
|
|
|
return false;
|
|
|
|
|
2008-01-11 07:08:24 +08:00
|
|
|
const TargetInstrDesc &TID = I.getDesc();
|
|
|
|
|
|
|
|
// Ignore stuff that we obviously can't hoist.
|
2008-12-24 01:28:50 +08:00
|
|
|
if (TID.mayStore() || TID.isCall() || TID.isTerminator() ||
|
2008-01-11 07:08:24 +08:00
|
|
|
TID.hasUnmodeledSideEffects())
|
|
|
|
return false;
|
2009-02-04 15:17:49 +08:00
|
|
|
|
2008-01-11 07:08:24 +08:00
|
|
|
if (TID.mayLoad()) {
|
2008-05-13 03:38:32 +08:00
|
|
|
// Okay, this instruction does a load. As a refinement, we allow the target
|
|
|
|
// to decide whether the loaded value is actually a constant. If so, we can
|
|
|
|
// actually use it as a load.
|
2009-10-08 01:38:06 +08:00
|
|
|
if (!I.isInvariantLoad(AA))
|
2009-11-18 03:19:01 +08:00
|
|
|
// FIXME: we should be able to hoist loads with no other side effects if
|
|
|
|
// there are no other instructions which can change memory in this loop.
|
|
|
|
// This is a trivial form of alias analysis.
|
2008-01-11 07:08:24 +08:00
|
|
|
return false;
|
|
|
|
}
|
2010-04-14 02:16:00 +08:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
/// IsLoopInvariantInst - Returns true if the instruction is loop
|
|
|
|
/// invariant. I.e., all virtual register operands are defined outside of the
|
|
|
|
/// loop, physical registers aren't accessed explicitly, and there are no side
|
|
|
|
/// effects that aren't captured by the operands or other flags.
|
|
|
|
///
|
|
|
|
bool MachineLICM::IsLoopInvariantInst(MachineInstr &I) {
|
|
|
|
if (!IsLICMCandidate(I))
|
|
|
|
return false;
|
2008-03-10 16:13:01 +08:00
|
|
|
|
2008-05-13 03:38:32 +08:00
|
|
|
// The instruction is loop invariant if all of its operands are.
|
Initial commit of the machine code LICM pass. It successfully hoists this:
_foo:
li r2, 0
LBB1_1: ; bb
li r5, 0
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
to:
_foo:
li r2, 0
li r5, 0
LBB1_1: ; bb
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
ZOMG!! :-)
Moar to come...
llvm-svn: 44687
2007-12-08 05:42:31 +08:00
|
|
|
for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
|
|
|
|
const MachineOperand &MO = I.getOperand(i);
|
|
|
|
|
2008-10-03 23:45:36 +08:00
|
|
|
if (!MO.isReg())
|
2008-08-21 04:32:05 +08:00
|
|
|
continue;
|
|
|
|
|
Initial commit of the machine code LICM pass. It successfully hoists this:
_foo:
li r2, 0
LBB1_1: ; bb
li r5, 0
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
to:
_foo:
li r2, 0
li r5, 0
LBB1_1: ; bb
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
ZOMG!! :-)
Moar to come...
llvm-svn: 44687
2007-12-08 05:42:31 +08:00
|
|
|
unsigned Reg = MO.getReg();
|
2008-03-10 16:13:01 +08:00
|
|
|
if (Reg == 0) continue;
|
Initial commit of the machine code LICM pass. It successfully hoists this:
_foo:
li r2, 0
LBB1_1: ; bb
li r5, 0
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
to:
_foo:
li r2, 0
li r5, 0
LBB1_1: ; bb
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
ZOMG!! :-)
Moar to come...
llvm-svn: 44687
2007-12-08 05:42:31 +08:00
|
|
|
|
2009-01-16 06:01:38 +08:00
|
|
|
// Don't hoist an instruction that uses or defines a physical register.
|
2009-09-26 07:58:45 +08:00
|
|
|
if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
|
|
|
|
if (MO.isUse()) {
|
|
|
|
// If the physreg has no defs anywhere, it's just an ambient register
|
2009-09-26 10:34:00 +08:00
|
|
|
// and we can freely move its uses. Alternatively, if it's allocatable,
|
|
|
|
// it could get allocated to something with a def during allocation.
|
2009-09-26 07:58:45 +08:00
|
|
|
if (!RegInfo->def_empty(Reg))
|
|
|
|
return false;
|
2009-09-26 10:34:00 +08:00
|
|
|
if (AllocatableSet.test(Reg))
|
|
|
|
return false;
|
2009-09-26 07:58:45 +08:00
|
|
|
// Check for a def among the register's aliases too.
|
2009-09-26 10:34:00 +08:00
|
|
|
for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
|
|
|
|
unsigned AliasReg = *Alias;
|
|
|
|
if (!RegInfo->def_empty(AliasReg))
|
|
|
|
return false;
|
|
|
|
if (AllocatableSet.test(AliasReg))
|
2009-09-26 07:58:45 +08:00
|
|
|
return false;
|
2009-09-26 10:34:00 +08:00
|
|
|
}
|
2009-09-26 07:58:45 +08:00
|
|
|
// Otherwise it's safe to move.
|
|
|
|
continue;
|
|
|
|
} else if (!MO.isDead()) {
|
|
|
|
// A def that isn't dead. We can't move it.
|
|
|
|
return false;
|
2010-02-28 08:08:44 +08:00
|
|
|
} else if (CurLoop->getHeader()->isLiveIn(Reg)) {
|
|
|
|
// If the reg is live into the loop, we can't hoist an instruction
|
|
|
|
// which would clobber it.
|
|
|
|
return false;
|
2009-09-26 07:58:45 +08:00
|
|
|
}
|
|
|
|
}
|
Initial commit of the machine code LICM pass. It successfully hoists this:
_foo:
li r2, 0
LBB1_1: ; bb
li r5, 0
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
to:
_foo:
li r2, 0
li r5, 0
LBB1_1: ; bb
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
ZOMG!! :-)
Moar to come...
llvm-svn: 44687
2007-12-08 05:42:31 +08:00
|
|
|
|
2009-01-16 06:01:38 +08:00
|
|
|
if (!MO.isUse())
|
|
|
|
continue;
|
|
|
|
|
2008-05-13 03:38:32 +08:00
|
|
|
assert(RegInfo->getVRegDef(Reg) &&
|
|
|
|
"Machine instr not mapped for this vreg?!");
|
Initial commit of the machine code LICM pass. It successfully hoists this:
_foo:
li r2, 0
LBB1_1: ; bb
li r5, 0
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
to:
_foo:
li r2, 0
li r5, 0
LBB1_1: ; bb
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
ZOMG!! :-)
Moar to come...
llvm-svn: 44687
2007-12-08 05:42:31 +08:00
|
|
|
|
|
|
|
// If the loop contains the definition of an operand, then the instruction
|
|
|
|
// isn't loop invariant.
|
2009-12-18 09:24:09 +08:00
|
|
|
if (CurLoop->contains(RegInfo->getVRegDef(Reg)))
|
Initial commit of the machine code LICM pass. It successfully hoists this:
_foo:
li r2, 0
LBB1_1: ; bb
li r5, 0
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
to:
_foo:
li r2, 0
li r5, 0
LBB1_1: ; bb
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
ZOMG!! :-)
Moar to come...
llvm-svn: 44687
2007-12-08 05:42:31 +08:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
// If we got this far, the instruction is loop invariant!
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2009-02-05 16:45:46 +08:00
|
|
|
|
|
|
|
/// HasPHIUses - Return true if the specified register has any PHI use.
|
|
|
|
static bool HasPHIUses(unsigned Reg, MachineRegisterInfo *RegInfo) {
|
2009-02-04 17:19:56 +08:00
|
|
|
for (MachineRegisterInfo::use_iterator UI = RegInfo->use_begin(Reg),
|
|
|
|
UE = RegInfo->use_end(); UI != UE; ++UI) {
|
|
|
|
MachineInstr *UseMI = &*UI;
|
2010-02-10 03:54:29 +08:00
|
|
|
if (UseMI->isPHI())
|
2009-02-05 16:45:46 +08:00
|
|
|
return true;
|
2009-02-04 17:19:56 +08:00
|
|
|
}
|
2009-02-05 16:45:46 +08:00
|
|
|
return false;
|
2009-02-04 17:19:56 +08:00
|
|
|
}
|
|
|
|
|
2009-11-21 03:55:37 +08:00
|
|
|
/// isLoadFromConstantMemory - Return true if the given instruction is a
|
|
|
|
/// load from constant memory. Machine LICM will hoist these even if they are
|
|
|
|
/// not re-materializable.
|
|
|
|
bool MachineLICM::isLoadFromConstantMemory(MachineInstr *MI) {
|
|
|
|
if (!MI->getDesc().mayLoad()) return false;
|
|
|
|
if (!MI->hasOneMemOperand()) return false;
|
|
|
|
MachineMemOperand *MMO = *MI->memoperands_begin();
|
|
|
|
if (MMO->isVolatile()) return false;
|
|
|
|
if (!MMO->getValue()) return false;
|
|
|
|
const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(MMO->getValue());
|
|
|
|
if (PSV) {
|
|
|
|
MachineFunction &MF = *MI->getParent()->getParent();
|
|
|
|
return PSV->isConstant(MF.getFrameInfo());
|
|
|
|
} else {
|
|
|
|
return AA->pointsToConstantMemory(MMO->getValue());
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2009-02-04 17:19:56 +08:00
|
|
|
/// IsProfitableToHoist - Return true if it is potentially profitable to hoist
|
|
|
|
/// the given loop invariant.
|
2009-11-21 07:31:34 +08:00
|
|
|
bool MachineLICM::IsProfitableToHoist(MachineInstr &MI) {
|
2009-02-04 17:19:56 +08:00
|
|
|
// FIXME: For now, only hoist re-materilizable instructions. LICM will
|
|
|
|
// increase register pressure. We want to make sure it doesn't increase
|
|
|
|
// spilling.
|
2009-11-21 03:55:37 +08:00
|
|
|
// Also hoist loads from constant memory, e.g. load from stubs, GOT. Hoisting
|
|
|
|
// these tend to help performance in low register pressure situation. The
|
|
|
|
// trade off is it may cause spill in high pressure situation. It will end up
|
|
|
|
// adding a store in the loop preheader. But the reload is no more expensive.
|
|
|
|
// The side benefit is these loads are frequently CSE'ed.
|
|
|
|
if (!TII->isTriviallyReMaterializable(&MI, AA)) {
|
2009-11-21 07:31:34 +08:00
|
|
|
if (!isLoadFromConstantMemory(&MI))
|
2009-11-21 03:55:37 +08:00
|
|
|
return false;
|
|
|
|
}
|
2009-02-04 17:19:56 +08:00
|
|
|
|
2009-02-05 16:45:46 +08:00
|
|
|
// If result(s) of this instruction is used by PHIs, then don't hoist it.
|
|
|
|
// The presence of joins makes it difficult for current register allocator
|
|
|
|
// implementation to perform remat.
|
2009-02-04 17:19:56 +08:00
|
|
|
for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
|
|
|
|
const MachineOperand &MO = MI.getOperand(i);
|
|
|
|
if (!MO.isReg() || !MO.isDef())
|
|
|
|
continue;
|
2009-02-05 16:45:46 +08:00
|
|
|
if (HasPHIUses(MO.getReg(), RegInfo))
|
|
|
|
return false;
|
2009-02-04 17:19:56 +08:00
|
|
|
}
|
2009-02-05 16:45:46 +08:00
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2009-10-30 01:47:20 +08:00
|
|
|
MachineInstr *MachineLICM::ExtractHoistableLoad(MachineInstr *MI) {
|
|
|
|
// If not, we may be able to unfold a load and hoist that.
|
|
|
|
// First test whether the instruction is loading from an amenable
|
|
|
|
// memory location.
|
2009-11-21 03:55:37 +08:00
|
|
|
if (!isLoadFromConstantMemory(MI))
|
|
|
|
return 0;
|
|
|
|
|
2009-10-30 01:47:20 +08:00
|
|
|
// Next determine the register class for a temporary register.
|
2009-10-31 06:18:41 +08:00
|
|
|
unsigned LoadRegIndex;
|
2009-10-30 01:47:20 +08:00
|
|
|
unsigned NewOpc =
|
|
|
|
TII->getOpcodeAfterMemoryUnfold(MI->getOpcode(),
|
|
|
|
/*UnfoldLoad=*/true,
|
2009-10-31 06:18:41 +08:00
|
|
|
/*UnfoldStore=*/false,
|
|
|
|
&LoadRegIndex);
|
2009-10-30 01:47:20 +08:00
|
|
|
if (NewOpc == 0) return 0;
|
|
|
|
const TargetInstrDesc &TID = TII->get(NewOpc);
|
|
|
|
if (TID.getNumDefs() != 1) return 0;
|
2009-10-31 06:18:41 +08:00
|
|
|
const TargetRegisterClass *RC = TID.OpInfo[LoadRegIndex].getRegClass(TRI);
|
2009-10-30 01:47:20 +08:00
|
|
|
// Ok, we're unfolding. Create a temporary register and do the unfold.
|
|
|
|
unsigned Reg = RegInfo->createVirtualRegister(RC);
|
2009-11-21 03:55:37 +08:00
|
|
|
|
|
|
|
MachineFunction &MF = *MI->getParent()->getParent();
|
2009-10-30 01:47:20 +08:00
|
|
|
SmallVector<MachineInstr *, 2> NewMIs;
|
|
|
|
bool Success =
|
|
|
|
TII->unfoldMemoryOperand(MF, MI, Reg,
|
|
|
|
/*UnfoldLoad=*/true, /*UnfoldStore=*/false,
|
|
|
|
NewMIs);
|
|
|
|
(void)Success;
|
|
|
|
assert(Success &&
|
|
|
|
"unfoldMemoryOperand failed when getOpcodeAfterMemoryUnfold "
|
|
|
|
"succeeded!");
|
|
|
|
assert(NewMIs.size() == 2 &&
|
|
|
|
"Unfolded a load into multiple instructions!");
|
|
|
|
MachineBasicBlock *MBB = MI->getParent();
|
|
|
|
MBB->insert(MI, NewMIs[0]);
|
|
|
|
MBB->insert(MI, NewMIs[1]);
|
|
|
|
// If unfolding produced a load that wasn't loop-invariant or profitable to
|
|
|
|
// hoist, discard the new instructions and bail.
|
2009-11-21 07:31:34 +08:00
|
|
|
if (!IsLoopInvariantInst(*NewMIs[0]) || !IsProfitableToHoist(*NewMIs[0])) {
|
2009-10-30 01:47:20 +08:00
|
|
|
NewMIs[0]->eraseFromParent();
|
|
|
|
NewMIs[1]->eraseFromParent();
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
// Otherwise we successfully unfolded a load that we can hoist.
|
|
|
|
MI->eraseFromParent();
|
|
|
|
return NewMIs[0];
|
|
|
|
}
|
|
|
|
|
2009-11-04 05:40:02 +08:00
|
|
|
void MachineLICM::InitCSEMap(MachineBasicBlock *BB) {
|
|
|
|
for (MachineBasicBlock::iterator I = BB->begin(),E = BB->end(); I != E; ++I) {
|
|
|
|
const MachineInstr *MI = &*I;
|
|
|
|
// FIXME: For now, only hoist re-materilizable instructions. LICM will
|
|
|
|
// increase register pressure. We want to make sure it doesn't increase
|
|
|
|
// spilling.
|
|
|
|
if (TII->isTriviallyReMaterializable(MI, AA)) {
|
|
|
|
unsigned Opcode = MI->getOpcode();
|
|
|
|
DenseMap<unsigned, std::vector<const MachineInstr*> >::iterator
|
|
|
|
CI = CSEMap.find(Opcode);
|
|
|
|
if (CI != CSEMap.end())
|
|
|
|
CI->second.push_back(MI);
|
|
|
|
else {
|
|
|
|
std::vector<const MachineInstr*> CSEMIs;
|
|
|
|
CSEMIs.push_back(MI);
|
|
|
|
CSEMap.insert(std::make_pair(Opcode, CSEMIs));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2009-11-07 11:52:02 +08:00
|
|
|
const MachineInstr*
|
|
|
|
MachineLICM::LookForDuplicate(const MachineInstr *MI,
|
|
|
|
std::vector<const MachineInstr*> &PrevMIs) {
|
2009-11-05 08:51:13 +08:00
|
|
|
for (unsigned i = 0, e = PrevMIs.size(); i != e; ++i) {
|
|
|
|
const MachineInstr *PrevMI = PrevMIs[i];
|
2010-03-03 09:44:33 +08:00
|
|
|
if (TII->produceSameValue(MI, PrevMI))
|
2009-11-05 08:51:13 +08:00
|
|
|
return PrevMI;
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool MachineLICM::EliminateCSE(MachineInstr *MI,
|
|
|
|
DenseMap<unsigned, std::vector<const MachineInstr*> >::iterator &CI) {
|
2009-11-07 11:52:02 +08:00
|
|
|
if (CI == CSEMap.end())
|
|
|
|
return false;
|
|
|
|
|
|
|
|
if (const MachineInstr *Dup = LookForDuplicate(MI, CI->second)) {
|
2010-01-05 08:03:48 +08:00
|
|
|
DEBUG(dbgs() << "CSEing " << *MI << " with " << *Dup);
|
2010-02-28 09:33:43 +08:00
|
|
|
|
|
|
|
// Replace virtual registers defined by MI by their counterparts defined
|
|
|
|
// by Dup.
|
2009-11-07 11:52:02 +08:00
|
|
|
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
|
|
|
const MachineOperand &MO = MI->getOperand(i);
|
2010-02-28 09:33:43 +08:00
|
|
|
|
|
|
|
// Physical registers may not differ here.
|
|
|
|
assert((!MO.isReg() || MO.getReg() == 0 ||
|
|
|
|
!TargetRegisterInfo::isPhysicalRegister(MO.getReg()) ||
|
|
|
|
MO.getReg() == Dup->getOperand(i).getReg()) &&
|
|
|
|
"Instructions with different phys regs are not identical!");
|
|
|
|
|
|
|
|
if (MO.isReg() && MO.isDef() &&
|
|
|
|
!TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
|
2009-11-07 11:52:02 +08:00
|
|
|
RegInfo->replaceRegWith(MO.getReg(), Dup->getOperand(i).getReg());
|
2009-11-05 08:51:13 +08:00
|
|
|
}
|
2009-11-07 11:52:02 +08:00
|
|
|
MI->eraseFromParent();
|
|
|
|
++NumCSEed;
|
|
|
|
return true;
|
2009-11-05 08:51:13 +08:00
|
|
|
}
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2008-05-13 03:38:32 +08:00
|
|
|
/// Hoist - When an instruction is found to use only loop invariant operands
|
|
|
|
/// that are safe to hoist, this instruction is called to do the dirty work.
|
Initial commit of the machine code LICM pass. It successfully hoists this:
_foo:
li r2, 0
LBB1_1: ; bb
li r5, 0
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
to:
_foo:
li r2, 0
li r5, 0
LBB1_1: ; bb
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
ZOMG!! :-)
Moar to come...
llvm-svn: 44687
2007-12-08 05:42:31 +08:00
|
|
|
///
|
2009-10-28 11:21:57 +08:00
|
|
|
void MachineLICM::Hoist(MachineInstr *MI) {
|
|
|
|
// First check whether we should hoist this instruction.
|
2009-11-21 07:31:34 +08:00
|
|
|
if (!IsLoopInvariantInst(*MI) || !IsProfitableToHoist(*MI)) {
|
2009-10-30 01:47:20 +08:00
|
|
|
// If not, try unfolding a hoistable load.
|
|
|
|
MI = ExtractHoistableLoad(MI);
|
|
|
|
if (!MI) return;
|
2009-10-28 11:21:57 +08:00
|
|
|
}
|
Initial commit of the machine code LICM pass. It successfully hoists this:
_foo:
li r2, 0
LBB1_1: ; bb
li r5, 0
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
to:
_foo:
li r2, 0
li r5, 0
LBB1_1: ; bb
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
ZOMG!! :-)
Moar to come...
llvm-svn: 44687
2007-12-08 05:42:31 +08:00
|
|
|
|
2009-01-16 06:01:38 +08:00
|
|
|
// Now move the instructions to the predecessor, inserting it before any
|
|
|
|
// terminator instructions.
|
|
|
|
DEBUG({
|
2010-01-05 08:03:48 +08:00
|
|
|
dbgs() << "Hoisting " << *MI;
|
2009-01-16 06:01:38 +08:00
|
|
|
if (CurPreheader->getBasicBlock())
|
2010-01-05 08:03:48 +08:00
|
|
|
dbgs() << " to MachineBasicBlock "
|
2009-11-20 09:17:03 +08:00
|
|
|
<< CurPreheader->getName();
|
2009-10-28 11:21:57 +08:00
|
|
|
if (MI->getParent()->getBasicBlock())
|
2010-01-05 08:03:48 +08:00
|
|
|
dbgs() << " from MachineBasicBlock "
|
2009-11-20 09:17:03 +08:00
|
|
|
<< MI->getParent()->getName();
|
2010-01-05 08:03:48 +08:00
|
|
|
dbgs() << "\n";
|
2009-01-16 06:01:38 +08:00
|
|
|
});
|
2007-12-08 09:47:01 +08:00
|
|
|
|
2009-11-04 05:40:02 +08:00
|
|
|
// If this is the first instruction being hoisted to the preheader,
|
|
|
|
// initialize the CSE map with potential common expressions.
|
|
|
|
InitCSEMap(CurPreheader);
|
|
|
|
|
2009-02-05 16:45:46 +08:00
|
|
|
// Look for opportunity to CSE the hoisted instruction.
|
2009-11-04 05:40:02 +08:00
|
|
|
unsigned Opcode = MI->getOpcode();
|
|
|
|
DenseMap<unsigned, std::vector<const MachineInstr*> >::iterator
|
|
|
|
CI = CSEMap.find(Opcode);
|
2009-11-05 08:51:13 +08:00
|
|
|
if (!EliminateCSE(MI, CI)) {
|
|
|
|
// Otherwise, splice the instruction to the preheader.
|
2009-11-04 05:40:02 +08:00
|
|
|
CurPreheader->splice(CurPreheader->getFirstTerminator(),MI->getParent(),MI);
|
|
|
|
|
2009-02-05 16:45:46 +08:00
|
|
|
// Add to the CSE map.
|
|
|
|
if (CI != CSEMap.end())
|
2009-10-28 11:21:57 +08:00
|
|
|
CI->second.push_back(MI);
|
2009-02-05 16:45:46 +08:00
|
|
|
else {
|
|
|
|
std::vector<const MachineInstr*> CSEMIs;
|
2009-10-28 11:21:57 +08:00
|
|
|
CSEMIs.push_back(MI);
|
2009-11-04 05:40:02 +08:00
|
|
|
CSEMap.insert(std::make_pair(Opcode, CSEMIs));
|
2009-02-05 16:45:46 +08:00
|
|
|
}
|
|
|
|
}
|
2007-12-08 09:47:01 +08:00
|
|
|
|
2009-01-16 06:01:38 +08:00
|
|
|
++NumHoisted;
|
Initial commit of the machine code LICM pass. It successfully hoists this:
_foo:
li r2, 0
LBB1_1: ; bb
li r5, 0
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
to:
_foo:
li r2, 0
li r5, 0
LBB1_1: ; bb
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
ZOMG!! :-)
Moar to come...
llvm-svn: 44687
2007-12-08 05:42:31 +08:00
|
|
|
Changed = true;
|
|
|
|
}
|