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llvm-project/llvm/test/CodeGen/ARM/ldrd.ll

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Fix ARM tests to be register allocator independent. llvm-svn: 128680
2011-04-01 06:14:03 +08:00
; RUN: llc < %s -mtriple=armv6-apple-darwin -regalloc=linearscan | FileCheck %s -check-prefix=V6
Weekly fix of register allocation dependent unit tests. llvm-svn: 130567
2011-04-30 09:37:52 +08:00
; RUN: llc < %s -mtriple=armv5-apple-darwin -regalloc=linearscan | FileCheck %s -check-prefix=V5
; RUN: llc < %s -mtriple=armv6-eabi -regalloc=linearscan | FileCheck %s -check-prefix=EABI
Part 1. - Change register allocation hint to a pair of unsigned integers. The hint type is zero (which means prefer the register specified as second part of the pair) or entirely target dependent. - Allow targets to specify alternative register allocation orders based on allocation hint. Part 2. - Use the register allocation hint system to implement more aggressive load / store multiple formation. - Aggressively form LDRD / STRD. These are formed *before* register allocation. It has to be done this way to shorten live interval of base and offset registers. e.g. v1025 = LDR v1024, 0 v1026 = LDR v1024, 0 => v1025,v1026 = LDRD v1024, 0 If this transformation isn't done before allocation, v1024 will overlap v1025 which means it more difficult to allocate a register pair. - Even with the register allocation hint, it may not be possible to get the desired allocation. In that case, the post-allocation load / store multiple pass must fix the ldrd / strd instructions. They can either become ldm / stm instructions or back to a pair of ldr / str instructions. This is work in progress, not yet enabled. llvm-svn: 73381
2009-06-15 16:28:29 +08:00
; rdar://r6949835
Fix ARM tests to be register allocator independent. llvm-svn: 128680
2011-04-01 06:14:03 +08:00
; Magic ARM pair hints works best with linearscan.
Part 1. - Change register allocation hint to a pair of unsigned integers. The hint type is zero (which means prefer the register specified as second part of the pair) or entirely target dependent. - Allow targets to specify alternative register allocation orders based on allocation hint. Part 2. - Use the register allocation hint system to implement more aggressive load / store multiple formation. - Aggressively form LDRD / STRD. These are formed *before* register allocation. It has to be done this way to shorten live interval of base and offset registers. e.g. v1025 = LDR v1024, 0 v1026 = LDR v1024, 0 => v1025,v1026 = LDRD v1024, 0 If this transformation isn't done before allocation, v1024 will overlap v1025 which means it more difficult to allocate a register pair. - Even with the register allocation hint, it may not be possible to get the desired allocation. In that case, the post-allocation load / store multiple pass must fix the ldrd / strd instructions. They can either become ldm / stm instructions or back to a pair of ldr / str instructions. This is work in progress, not yet enabled. llvm-svn: 73381
2009-06-15 16:28:29 +08:00
@b = external global i64*
define i64 @t(i64 %a) nounwind readonly {
entry:
LDRD/STRD instructions should print both Rt and Rt2 in the asm string. llvm-svn: 128736
2011-04-02 04:26:57 +08:00
;V6: ldrd r2, r3, [r2]
Convert test to filecheck. llvm-svn: 82835
2009-09-26 10:41:17 +08:00
Fix ARM tests to be register allocator independent. llvm-svn: 128680
2011-04-01 06:14:03 +08:00
;V5: ldr r{{[0-9]+}}, [r2]
;V5: ldr r{{[0-9]+}}, [r2, #4]
Convert test to filecheck. llvm-svn: 82835
2009-09-26 10:41:17 +08:00
Fix ARM tests to be register allocator independent. llvm-svn: 128680
2011-04-01 06:14:03 +08:00
;EABI: ldr r{{[0-9]+}}, [r2]
;EABI: ldr r{{[0-9]+}}, [r2, #4]
Convert test to filecheck. llvm-svn: 82835
2009-09-26 10:41:17 +08:00
Part 1. - Change register allocation hint to a pair of unsigned integers. The hint type is zero (which means prefer the register specified as second part of the pair) or entirely target dependent. - Allow targets to specify alternative register allocation orders based on allocation hint. Part 2. - Use the register allocation hint system to implement more aggressive load / store multiple formation. - Aggressively form LDRD / STRD. These are formed *before* register allocation. It has to be done this way to shorten live interval of base and offset registers. e.g. v1025 = LDR v1024, 0 v1026 = LDR v1024, 0 => v1025,v1026 = LDRD v1024, 0 If this transformation isn't done before allocation, v1024 will overlap v1025 which means it more difficult to allocate a register pair. - Even with the register allocation hint, it may not be possible to get the desired allocation. In that case, the post-allocation load / store multiple pass must fix the ldrd / strd instructions. They can either become ldm / stm instructions or back to a pair of ldr / str instructions. This is work in progress, not yet enabled. llvm-svn: 73381
2009-06-15 16:28:29 +08:00
%0 = load i64** @b, align 4
%1 = load i64* %0, align 4
%2 = mul i64 %1, %a
ret i64 %2
}