2019-11-12 07:42:25 +08:00
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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2019-11-20 07:51:19 +08:00
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; RUN: llc -O3 -mtriple=i686-pc-linux -mattr=+cmov < %s | FileCheck %s --check-prefix=COMMON --check-prefix=X87
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2019-11-18 11:58:11 +08:00
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; RUN: llc -O3 -mtriple=i686-pc-linux -mattr=sse2 < %s | FileCheck %s --check-prefix=COMMON --check-prefix=X86-SSE
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2019-11-12 07:42:25 +08:00
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; RUN: llc -O3 -mtriple=x86_64-pc-linux < %s | FileCheck %s --check-prefix=COMMON --check-prefix=SSE
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; RUN: llc -O3 -mtriple=x86_64-pc-linux -mattr=+avx < %s | FileCheck %s --check-prefix=COMMON --check-prefix=AVX --check-prefix=AVX1
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; RUN: llc -O3 -mtriple=x86_64-pc-linux -mattr=+avx512f < %s | FileCheck %s --check-prefix=COMMON --check-prefix=AVX --check-prefix=AVX512 --check-prefix=AVX512F
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; RUN: llc -O3 -mtriple=x86_64-pc-linux -mattr=+avx512dq < %s | FileCheck %s --check-prefix=COMMON --check-prefix=AVX --check-prefix=AVX512 --check-prefix=AVX512DQ
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2017-01-27 07:27:59 +08:00
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; Verify that constants aren't folded to inexact results when the rounding mode
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; is unknown.
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;
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; double f1() {
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; // Because 0.1 cannot be represented exactly, this shouldn't be folded.
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; return 1.0/10.0;
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; }
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;
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2019-10-05 01:03:46 +08:00
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define double @f1() #0 {
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2019-11-20 07:51:19 +08:00
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; X87-LABEL: f1:
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; X87: # %bb.0: # %entry
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; X87-NEXT: fld1
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; X87-NEXT: fdivs {{\.LCPI.*}}
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; X87-NEXT: retl
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;
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2019-11-18 11:58:11 +08:00
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; X86-SSE-LABEL: f1:
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; X86-SSE: # %bb.0: # %entry
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; X86-SSE-NEXT: subl $12, %esp
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; X86-SSE-NEXT: .cfi_def_cfa_offset 16
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; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
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; X86-SSE-NEXT: divsd {{\.LCPI.*}}, %xmm0
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; X86-SSE-NEXT: movsd %xmm0, (%esp)
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; X86-SSE-NEXT: fldl (%esp)
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; X86-SSE-NEXT: addl $12, %esp
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; X86-SSE-NEXT: .cfi_def_cfa_offset 4
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; X86-SSE-NEXT: retl
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;
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2019-11-12 07:42:25 +08:00
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; SSE-LABEL: f1:
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; SSE: # %bb.0: # %entry
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; SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
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; SSE-NEXT: divsd {{.*}}(%rip), %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: f1:
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; AVX: # %bb.0: # %entry
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; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
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; AVX-NEXT: vdivsd {{.*}}(%rip), %xmm0, %xmm0
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; AVX-NEXT: retq
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2017-01-27 07:27:59 +08:00
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entry:
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%div = call double @llvm.experimental.constrained.fdiv.f64(
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double 1.000000e+00,
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double 1.000000e+01,
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metadata !"round.dynamic",
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2019-10-05 01:03:46 +08:00
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metadata !"fpexcept.strict") #0
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2017-01-27 07:27:59 +08:00
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ret double %div
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}
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; Verify that 'a - 0' isn't simplified to 'a' when the rounding mode is unknown.
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;
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; double f2(double a) {
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; // Because the result of '0 - 0' is negative zero if rounding mode is
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; // downward, this shouldn't be simplified.
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; return a - 0;
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; }
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;
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2019-10-05 01:03:46 +08:00
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define double @f2(double %a) #0 {
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2019-11-20 07:51:19 +08:00
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; X87-LABEL: f2:
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; X87: # %bb.0: # %entry
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; X87-NEXT: fldz
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; X87-NEXT: fsubrl {{[0-9]+}}(%esp)
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; X87-NEXT: retl
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;
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2019-11-18 11:58:11 +08:00
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; X86-SSE-LABEL: f2:
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; X86-SSE: # %bb.0: # %entry
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; X86-SSE-NEXT: subl $12, %esp
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; X86-SSE-NEXT: .cfi_def_cfa_offset 16
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; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
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; X86-SSE-NEXT: xorpd %xmm1, %xmm1
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; X86-SSE-NEXT: subsd %xmm1, %xmm0
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; X86-SSE-NEXT: movsd %xmm0, (%esp)
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; X86-SSE-NEXT: fldl (%esp)
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; X86-SSE-NEXT: addl $12, %esp
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; X86-SSE-NEXT: .cfi_def_cfa_offset 4
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; X86-SSE-NEXT: retl
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;
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2019-11-12 07:42:25 +08:00
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; SSE-LABEL: f2:
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; SSE: # %bb.0: # %entry
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; SSE-NEXT: xorpd %xmm1, %xmm1
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; SSE-NEXT: subsd %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: f2:
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; AVX: # %bb.0: # %entry
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; AVX-NEXT: vxorpd %xmm1, %xmm1, %xmm1
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; AVX-NEXT: vsubsd %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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2017-01-27 07:27:59 +08:00
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entry:
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2018-06-16 04:57:55 +08:00
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%sub = call double @llvm.experimental.constrained.fsub.f64(
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2017-01-27 07:27:59 +08:00
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double %a,
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double 0.000000e+00,
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metadata !"round.dynamic",
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2019-10-05 01:03:46 +08:00
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metadata !"fpexcept.strict") #0
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2018-06-16 04:57:55 +08:00
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ret double %sub
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2017-01-27 07:27:59 +08:00
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}
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; Verify that '-((-a)*b)' isn't simplified to 'a*b' when the rounding mode is
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; unknown.
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;
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; double f3(double a, double b) {
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; // Because the intermediate value involved in this calculation may require
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; // rounding, this shouldn't be simplified.
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; return -((-a)*b);
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; }
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;
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2019-10-05 01:03:46 +08:00
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define double @f3(double %a, double %b) #0 {
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2019-11-20 07:51:19 +08:00
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; X87-LABEL: f3:
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; X87: # %bb.0: # %entry
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; X87-NEXT: fldz
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; X87-NEXT: fchs
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; X87-NEXT: fld %st(0)
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; X87-NEXT: fsubl {{[0-9]+}}(%esp)
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; X87-NEXT: fmull {{[0-9]+}}(%esp)
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; X87-NEXT: fsubrp %st, %st(1)
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; X87-NEXT: retl
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;
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2019-11-18 11:58:11 +08:00
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; X86-SSE-LABEL: f3:
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; X86-SSE: # %bb.0: # %entry
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; X86-SSE-NEXT: subl $12, %esp
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; X86-SSE-NEXT: .cfi_def_cfa_offset 16
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; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
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; X86-SSE-NEXT: movapd %xmm0, %xmm1
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; X86-SSE-NEXT: subsd {{[0-9]+}}(%esp), %xmm1
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; X86-SSE-NEXT: mulsd {{[0-9]+}}(%esp), %xmm1
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; X86-SSE-NEXT: subsd %xmm1, %xmm0
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; X86-SSE-NEXT: movsd %xmm0, (%esp)
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; X86-SSE-NEXT: fldl (%esp)
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; X86-SSE-NEXT: addl $12, %esp
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; X86-SSE-NEXT: .cfi_def_cfa_offset 4
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; X86-SSE-NEXT: retl
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;
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2019-11-12 07:42:25 +08:00
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; SSE-LABEL: f3:
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; SSE: # %bb.0: # %entry
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; SSE-NEXT: movsd {{.*#+}} xmm2 = mem[0],zero
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; SSE-NEXT: movapd %xmm2, %xmm3
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; SSE-NEXT: subsd %xmm0, %xmm3
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; SSE-NEXT: mulsd %xmm1, %xmm3
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; SSE-NEXT: subsd %xmm3, %xmm2
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; SSE-NEXT: movapd %xmm2, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: f3:
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; AVX: # %bb.0: # %entry
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; AVX-NEXT: vmovsd {{.*#+}} xmm2 = mem[0],zero
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; AVX-NEXT: vsubsd %xmm0, %xmm2, %xmm0
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; AVX-NEXT: vmulsd %xmm1, %xmm0, %xmm0
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; AVX-NEXT: vsubsd %xmm0, %xmm2, %xmm0
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; AVX-NEXT: retq
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2017-01-27 07:27:59 +08:00
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entry:
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%sub = call double @llvm.experimental.constrained.fsub.f64(
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double -0.000000e+00, double %a,
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metadata !"round.dynamic",
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2019-10-05 01:03:46 +08:00
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metadata !"fpexcept.strict") #0
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2017-01-27 07:27:59 +08:00
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%mul = call double @llvm.experimental.constrained.fmul.f64(
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double %sub, double %b,
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metadata !"round.dynamic",
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2019-10-05 01:03:46 +08:00
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metadata !"fpexcept.strict") #0
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2017-01-27 07:27:59 +08:00
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%ret = call double @llvm.experimental.constrained.fsub.f64(
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double -0.000000e+00,
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double %mul,
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metadata !"round.dynamic",
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2019-10-05 01:03:46 +08:00
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metadata !"fpexcept.strict") #0
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2017-01-27 07:27:59 +08:00
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ret double %ret
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}
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; Verify that FP operations are not performed speculatively when FP exceptions
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; are not being ignored.
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;
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; double f4(int n, double a) {
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; // Because a + 1 may overflow, this should not be simplified.
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; if (n > 0)
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; return a + 1.0;
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; return a;
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; }
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;
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2017-08-24 12:18:24 +08:00
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;
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2019-10-05 01:03:46 +08:00
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define double @f4(i32 %n, double %a) #0 {
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2019-11-20 07:51:19 +08:00
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; X87-LABEL: f4:
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; X87: # %bb.0: # %entry
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; X87-NEXT: fldl {{[0-9]+}}(%esp)
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; X87-NEXT: cmpl $0, {{[0-9]+}}(%esp)
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; X87-NEXT: jle .LBB3_2
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; X87-NEXT: # %bb.1: # %if.then
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; X87-NEXT: fld1
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; X87-NEXT: faddp %st, %st(1)
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; X87-NEXT: .LBB3_2: # %if.end
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; X87-NEXT: retl
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;
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2019-11-18 11:58:11 +08:00
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; X86-SSE-LABEL: f4:
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; X86-SSE: # %bb.0: # %entry
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; X86-SSE-NEXT: subl $12, %esp
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; X86-SSE-NEXT: .cfi_def_cfa_offset 16
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; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
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; X86-SSE-NEXT: cmpl $0, {{[0-9]+}}(%esp)
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; X86-SSE-NEXT: jle .LBB3_2
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; X86-SSE-NEXT: # %bb.1: # %if.then
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; X86-SSE-NEXT: addsd {{\.LCPI.*}}, %xmm0
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; X86-SSE-NEXT: .LBB3_2: # %if.end
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; X86-SSE-NEXT: movsd %xmm0, (%esp)
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; X86-SSE-NEXT: fldl (%esp)
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; X86-SSE-NEXT: addl $12, %esp
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; X86-SSE-NEXT: .cfi_def_cfa_offset 4
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; X86-SSE-NEXT: retl
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;
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2019-11-12 07:42:25 +08:00
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; SSE-LABEL: f4:
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; SSE: # %bb.0: # %entry
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; SSE-NEXT: testl %edi, %edi
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; SSE-NEXT: jle .LBB3_2
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; SSE-NEXT: # %bb.1: # %if.then
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; SSE-NEXT: addsd {{.*}}(%rip), %xmm0
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; SSE-NEXT: .LBB3_2: # %if.end
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; SSE-NEXT: retq
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;
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; AVX-LABEL: f4:
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; AVX: # %bb.0: # %entry
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; AVX-NEXT: testl %edi, %edi
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; AVX-NEXT: jle .LBB3_2
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; AVX-NEXT: # %bb.1: # %if.then
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; AVX-NEXT: vaddsd {{.*}}(%rip), %xmm0, %xmm0
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; AVX-NEXT: .LBB3_2: # %if.end
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; AVX-NEXT: retq
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2017-01-27 07:27:59 +08:00
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entry:
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%cmp = icmp sgt i32 %n, 0
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br i1 %cmp, label %if.then, label %if.end
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if.then:
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%add = call double @llvm.experimental.constrained.fadd.f64(
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double 1.000000e+00, double %a,
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metadata !"round.dynamic",
|
2019-10-05 01:03:46 +08:00
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metadata !"fpexcept.strict") #0
|
2017-01-27 07:27:59 +08:00
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br label %if.end
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if.end:
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|
%a.0 = phi double [%add, %if.then], [ %a, %entry ]
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|
|
ret double %a.0
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|
}
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|
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|
2017-05-26 05:31:00 +08:00
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|
|
; Verify that sqrt(42.0) isn't simplified when the rounding mode is unknown.
|
2019-10-05 01:03:46 +08:00
|
|
|
define double @f5() #0 {
|
2019-11-20 07:51:19 +08:00
|
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|
; X87-LABEL: f5:
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; X87: # %bb.0: # %entry
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|
; X87-NEXT: flds {{\.LCPI.*}}
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; X87-NEXT: fsqrt
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; X87-NEXT: retl
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|
;
|
2019-11-18 11:58:11 +08:00
|
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|
; X86-SSE-LABEL: f5:
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|
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; X86-SSE: # %bb.0: # %entry
|
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|
; X86-SSE-NEXT: subl $12, %esp
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|
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|
; X86-SSE-NEXT: .cfi_def_cfa_offset 16
|
|
|
|
; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
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|
|
|
; X86-SSE-NEXT: sqrtsd %xmm0, %xmm0
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|
; X86-SSE-NEXT: movsd %xmm0, (%esp)
|
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; X86-SSE-NEXT: fldl (%esp)
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; X86-SSE-NEXT: addl $12, %esp
|
|
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|
; X86-SSE-NEXT: .cfi_def_cfa_offset 4
|
|
|
|
; X86-SSE-NEXT: retl
|
|
|
|
;
|
2019-11-12 07:42:25 +08:00
|
|
|
; SSE-LABEL: f5:
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|
|
|
; SSE: # %bb.0: # %entry
|
|
|
|
; SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
|
|
|
|
; SSE-NEXT: sqrtsd %xmm0, %xmm0
|
|
|
|
; SSE-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX-LABEL: f5:
|
|
|
|
; AVX: # %bb.0: # %entry
|
|
|
|
; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
|
|
|
|
; AVX-NEXT: vsqrtsd %xmm0, %xmm0, %xmm0
|
|
|
|
; AVX-NEXT: retq
|
2017-05-26 05:31:00 +08:00
|
|
|
entry:
|
|
|
|
%result = call double @llvm.experimental.constrained.sqrt.f64(double 42.0,
|
|
|
|
metadata !"round.dynamic",
|
2019-10-05 01:03:46 +08:00
|
|
|
metadata !"fpexcept.strict") #0
|
2017-05-26 05:31:00 +08:00
|
|
|
ret double %result
|
|
|
|
}
|
|
|
|
|
|
|
|
; Verify that pow(42.1, 3.0) isn't simplified when the rounding mode is unknown.
|
2019-10-05 01:03:46 +08:00
|
|
|
define double @f6() #0 {
|
2019-11-20 07:51:19 +08:00
|
|
|
; X87-LABEL: f6:
|
|
|
|
; X87: # %bb.0: # %entry
|
|
|
|
; X87-NEXT: subl $28, %esp
|
|
|
|
; X87-NEXT: .cfi_def_cfa_offset 32
|
|
|
|
; X87-NEXT: flds {{\.LCPI.*}}
|
|
|
|
; X87-NEXT: fstpl {{[0-9]+}}(%esp)
|
|
|
|
; X87-NEXT: fldl {{\.LCPI.*}}
|
|
|
|
; X87-NEXT: fstpl (%esp)
|
|
|
|
; X87-NEXT: calll pow
|
|
|
|
; X87-NEXT: addl $28, %esp
|
|
|
|
; X87-NEXT: .cfi_def_cfa_offset 4
|
|
|
|
; X87-NEXT: retl
|
|
|
|
;
|
2019-11-18 11:58:11 +08:00
|
|
|
; X86-SSE-LABEL: f6:
|
|
|
|
; X86-SSE: # %bb.0: # %entry
|
|
|
|
; X86-SSE-NEXT: subl $28, %esp
|
|
|
|
; X86-SSE-NEXT: .cfi_def_cfa_offset 32
|
|
|
|
; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
|
|
|
|
; X86-SSE-NEXT: movsd %xmm0, {{[0-9]+}}(%esp)
|
|
|
|
; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
|
|
|
|
; X86-SSE-NEXT: movsd %xmm0, (%esp)
|
|
|
|
; X86-SSE-NEXT: calll pow
|
|
|
|
; X86-SSE-NEXT: addl $28, %esp
|
|
|
|
; X86-SSE-NEXT: .cfi_def_cfa_offset 4
|
|
|
|
; X86-SSE-NEXT: retl
|
|
|
|
;
|
2019-11-12 07:42:25 +08:00
|
|
|
; SSE-LABEL: f6:
|
|
|
|
; SSE: # %bb.0: # %entry
|
2019-11-19 03:14:13 +08:00
|
|
|
; SSE-NEXT: pushq %rax
|
|
|
|
; SSE-NEXT: .cfi_def_cfa_offset 16
|
2019-11-12 07:42:25 +08:00
|
|
|
; SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
|
|
|
|
; SSE-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
|
2019-11-19 03:14:13 +08:00
|
|
|
; SSE-NEXT: callq pow
|
|
|
|
; SSE-NEXT: popq %rax
|
|
|
|
; SSE-NEXT: .cfi_def_cfa_offset 8
|
|
|
|
; SSE-NEXT: retq
|
2019-11-12 07:42:25 +08:00
|
|
|
;
|
|
|
|
; AVX-LABEL: f6:
|
|
|
|
; AVX: # %bb.0: # %entry
|
2019-11-19 03:14:13 +08:00
|
|
|
; AVX-NEXT: pushq %rax
|
|
|
|
; AVX-NEXT: .cfi_def_cfa_offset 16
|
2019-11-12 07:42:25 +08:00
|
|
|
; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
|
|
|
|
; AVX-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero
|
2019-11-19 03:14:13 +08:00
|
|
|
; AVX-NEXT: callq pow
|
|
|
|
; AVX-NEXT: popq %rax
|
|
|
|
; AVX-NEXT: .cfi_def_cfa_offset 8
|
|
|
|
; AVX-NEXT: retq
|
2017-05-26 05:31:00 +08:00
|
|
|
entry:
|
|
|
|
%result = call double @llvm.experimental.constrained.pow.f64(double 42.1,
|
|
|
|
double 3.0,
|
|
|
|
metadata !"round.dynamic",
|
2019-10-05 01:03:46 +08:00
|
|
|
metadata !"fpexcept.strict") #0
|
2017-05-26 05:31:00 +08:00
|
|
|
ret double %result
|
|
|
|
}
|
|
|
|
|
|
|
|
; Verify that powi(42.1, 3) isn't simplified when the rounding mode is unknown.
|
2019-10-05 01:03:46 +08:00
|
|
|
define double @f7() #0 {
|
2019-11-20 07:51:19 +08:00
|
|
|
; X87-LABEL: f7:
|
|
|
|
; X87: # %bb.0: # %entry
|
|
|
|
; X87-NEXT: subl $12, %esp
|
|
|
|
; X87-NEXT: .cfi_def_cfa_offset 16
|
|
|
|
; X87-NEXT: fldl {{\.LCPI.*}}
|
|
|
|
; X87-NEXT: fstpl (%esp)
|
|
|
|
; X87-NEXT: movl $3, {{[0-9]+}}(%esp)
|
|
|
|
; X87-NEXT: calll __powidf2
|
|
|
|
; X87-NEXT: addl $12, %esp
|
|
|
|
; X87-NEXT: .cfi_def_cfa_offset 4
|
|
|
|
; X87-NEXT: retl
|
|
|
|
;
|
2019-11-18 11:58:11 +08:00
|
|
|
; X86-SSE-LABEL: f7:
|
|
|
|
; X86-SSE: # %bb.0: # %entry
|
|
|
|
; X86-SSE-NEXT: subl $12, %esp
|
|
|
|
; X86-SSE-NEXT: .cfi_def_cfa_offset 16
|
|
|
|
; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
|
|
|
|
; X86-SSE-NEXT: movsd %xmm0, (%esp)
|
|
|
|
; X86-SSE-NEXT: movl $3, {{[0-9]+}}(%esp)
|
|
|
|
; X86-SSE-NEXT: calll __powidf2
|
|
|
|
; X86-SSE-NEXT: addl $12, %esp
|
|
|
|
; X86-SSE-NEXT: .cfi_def_cfa_offset 4
|
|
|
|
; X86-SSE-NEXT: retl
|
|
|
|
;
|
2019-11-12 07:42:25 +08:00
|
|
|
; SSE-LABEL: f7:
|
|
|
|
; SSE: # %bb.0: # %entry
|
2019-11-19 03:14:13 +08:00
|
|
|
; SSE-NEXT: pushq %rax
|
|
|
|
; SSE-NEXT: .cfi_def_cfa_offset 16
|
2019-11-12 07:42:25 +08:00
|
|
|
; SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
|
|
|
|
; SSE-NEXT: movl $3, %edi
|
2019-11-19 03:14:13 +08:00
|
|
|
; SSE-NEXT: callq __powidf2
|
|
|
|
; SSE-NEXT: popq %rax
|
|
|
|
; SSE-NEXT: .cfi_def_cfa_offset 8
|
|
|
|
; SSE-NEXT: retq
|
2019-11-12 07:42:25 +08:00
|
|
|
;
|
|
|
|
; AVX-LABEL: f7:
|
|
|
|
; AVX: # %bb.0: # %entry
|
2019-11-19 03:14:13 +08:00
|
|
|
; AVX-NEXT: pushq %rax
|
|
|
|
; AVX-NEXT: .cfi_def_cfa_offset 16
|
2019-11-12 07:42:25 +08:00
|
|
|
; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
|
|
|
|
; AVX-NEXT: movl $3, %edi
|
2019-11-19 03:14:13 +08:00
|
|
|
; AVX-NEXT: callq __powidf2
|
|
|
|
; AVX-NEXT: popq %rax
|
|
|
|
; AVX-NEXT: .cfi_def_cfa_offset 8
|
|
|
|
; AVX-NEXT: retq
|
2017-05-26 05:31:00 +08:00
|
|
|
entry:
|
|
|
|
%result = call double @llvm.experimental.constrained.powi.f64(double 42.1,
|
|
|
|
i32 3,
|
|
|
|
metadata !"round.dynamic",
|
2019-10-05 01:03:46 +08:00
|
|
|
metadata !"fpexcept.strict") #0
|
2017-05-26 05:31:00 +08:00
|
|
|
ret double %result
|
|
|
|
}
|
|
|
|
|
|
|
|
; Verify that sin(42.0) isn't simplified when the rounding mode is unknown.
|
2019-10-05 01:03:46 +08:00
|
|
|
define double @f8() #0 {
|
2019-11-20 07:51:19 +08:00
|
|
|
; X87-LABEL: f8:
|
|
|
|
; X87: # %bb.0: # %entry
|
|
|
|
; X87-NEXT: subl $12, %esp
|
|
|
|
; X87-NEXT: .cfi_def_cfa_offset 16
|
|
|
|
; X87-NEXT: flds {{\.LCPI.*}}
|
|
|
|
; X87-NEXT: fstpl (%esp)
|
|
|
|
; X87-NEXT: calll sin
|
|
|
|
; X87-NEXT: addl $12, %esp
|
|
|
|
; X87-NEXT: .cfi_def_cfa_offset 4
|
|
|
|
; X87-NEXT: retl
|
|
|
|
;
|
2019-11-18 11:58:11 +08:00
|
|
|
; X86-SSE-LABEL: f8:
|
|
|
|
; X86-SSE: # %bb.0: # %entry
|
|
|
|
; X86-SSE-NEXT: subl $12, %esp
|
|
|
|
; X86-SSE-NEXT: .cfi_def_cfa_offset 16
|
|
|
|
; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
|
|
|
|
; X86-SSE-NEXT: movsd %xmm0, (%esp)
|
|
|
|
; X86-SSE-NEXT: calll sin
|
|
|
|
; X86-SSE-NEXT: addl $12, %esp
|
|
|
|
; X86-SSE-NEXT: .cfi_def_cfa_offset 4
|
|
|
|
; X86-SSE-NEXT: retl
|
|
|
|
;
|
2019-11-12 07:42:25 +08:00
|
|
|
; SSE-LABEL: f8:
|
|
|
|
; SSE: # %bb.0: # %entry
|
2019-11-19 03:14:13 +08:00
|
|
|
; SSE-NEXT: pushq %rax
|
|
|
|
; SSE-NEXT: .cfi_def_cfa_offset 16
|
2019-11-12 07:42:25 +08:00
|
|
|
; SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
|
2019-11-19 03:14:13 +08:00
|
|
|
; SSE-NEXT: callq sin
|
|
|
|
; SSE-NEXT: popq %rax
|
|
|
|
; SSE-NEXT: .cfi_def_cfa_offset 8
|
|
|
|
; SSE-NEXT: retq
|
2019-11-12 07:42:25 +08:00
|
|
|
;
|
|
|
|
; AVX-LABEL: f8:
|
|
|
|
; AVX: # %bb.0: # %entry
|
2019-11-19 03:14:13 +08:00
|
|
|
; AVX-NEXT: pushq %rax
|
|
|
|
; AVX-NEXT: .cfi_def_cfa_offset 16
|
2019-11-12 07:42:25 +08:00
|
|
|
; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
|
2019-11-19 03:14:13 +08:00
|
|
|
; AVX-NEXT: callq sin
|
|
|
|
; AVX-NEXT: popq %rax
|
|
|
|
; AVX-NEXT: .cfi_def_cfa_offset 8
|
|
|
|
; AVX-NEXT: retq
|
2017-05-26 05:31:00 +08:00
|
|
|
entry:
|
|
|
|
%result = call double @llvm.experimental.constrained.sin.f64(double 42.0,
|
|
|
|
metadata !"round.dynamic",
|
2019-10-05 01:03:46 +08:00
|
|
|
metadata !"fpexcept.strict") #0
|
2017-05-26 05:31:00 +08:00
|
|
|
ret double %result
|
|
|
|
}
|
|
|
|
|
|
|
|
; Verify that cos(42.0) isn't simplified when the rounding mode is unknown.
|
2019-10-05 01:03:46 +08:00
|
|
|
define double @f9() #0 {
|
2019-11-20 07:51:19 +08:00
|
|
|
; X87-LABEL: f9:
|
|
|
|
; X87: # %bb.0: # %entry
|
|
|
|
; X87-NEXT: subl $12, %esp
|
|
|
|
; X87-NEXT: .cfi_def_cfa_offset 16
|
|
|
|
; X87-NEXT: flds {{\.LCPI.*}}
|
|
|
|
; X87-NEXT: fstpl (%esp)
|
|
|
|
; X87-NEXT: calll cos
|
|
|
|
; X87-NEXT: addl $12, %esp
|
|
|
|
; X87-NEXT: .cfi_def_cfa_offset 4
|
|
|
|
; X87-NEXT: retl
|
|
|
|
;
|
2019-11-18 11:58:11 +08:00
|
|
|
; X86-SSE-LABEL: f9:
|
|
|
|
; X86-SSE: # %bb.0: # %entry
|
|
|
|
; X86-SSE-NEXT: subl $12, %esp
|
|
|
|
; X86-SSE-NEXT: .cfi_def_cfa_offset 16
|
|
|
|
; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
|
|
|
|
; X86-SSE-NEXT: movsd %xmm0, (%esp)
|
|
|
|
; X86-SSE-NEXT: calll cos
|
|
|
|
; X86-SSE-NEXT: addl $12, %esp
|
|
|
|
; X86-SSE-NEXT: .cfi_def_cfa_offset 4
|
|
|
|
; X86-SSE-NEXT: retl
|
|
|
|
;
|
2019-11-12 07:42:25 +08:00
|
|
|
; SSE-LABEL: f9:
|
|
|
|
; SSE: # %bb.0: # %entry
|
2019-11-19 03:14:13 +08:00
|
|
|
; SSE-NEXT: pushq %rax
|
|
|
|
; SSE-NEXT: .cfi_def_cfa_offset 16
|
2019-11-12 07:42:25 +08:00
|
|
|
; SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
|
2019-11-19 03:14:13 +08:00
|
|
|
; SSE-NEXT: callq cos
|
|
|
|
; SSE-NEXT: popq %rax
|
|
|
|
; SSE-NEXT: .cfi_def_cfa_offset 8
|
|
|
|
; SSE-NEXT: retq
|
2019-11-12 07:42:25 +08:00
|
|
|
;
|
|
|
|
; AVX-LABEL: f9:
|
|
|
|
; AVX: # %bb.0: # %entry
|
2019-11-19 03:14:13 +08:00
|
|
|
; AVX-NEXT: pushq %rax
|
|
|
|
; AVX-NEXT: .cfi_def_cfa_offset 16
|
2019-11-12 07:42:25 +08:00
|
|
|
; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
|
2019-11-19 03:14:13 +08:00
|
|
|
; AVX-NEXT: callq cos
|
|
|
|
; AVX-NEXT: popq %rax
|
|
|
|
; AVX-NEXT: .cfi_def_cfa_offset 8
|
|
|
|
; AVX-NEXT: retq
|
2017-05-26 05:31:00 +08:00
|
|
|
entry:
|
|
|
|
%result = call double @llvm.experimental.constrained.cos.f64(double 42.0,
|
|
|
|
metadata !"round.dynamic",
|
2019-10-05 01:03:46 +08:00
|
|
|
metadata !"fpexcept.strict") #0
|
2017-05-26 05:31:00 +08:00
|
|
|
ret double %result
|
|
|
|
}
|
|
|
|
|
|
|
|
; Verify that exp(42.0) isn't simplified when the rounding mode is unknown.
|
2019-10-05 01:03:46 +08:00
|
|
|
define double @f10() #0 {
|
2019-11-20 07:51:19 +08:00
|
|
|
; X87-LABEL: f10:
|
|
|
|
; X87: # %bb.0: # %entry
|
|
|
|
; X87-NEXT: subl $12, %esp
|
|
|
|
; X87-NEXT: .cfi_def_cfa_offset 16
|
|
|
|
; X87-NEXT: flds {{\.LCPI.*}}
|
|
|
|
; X87-NEXT: fstpl (%esp)
|
|
|
|
; X87-NEXT: calll exp
|
|
|
|
; X87-NEXT: addl $12, %esp
|
|
|
|
; X87-NEXT: .cfi_def_cfa_offset 4
|
|
|
|
; X87-NEXT: retl
|
|
|
|
;
|
2019-11-18 11:58:11 +08:00
|
|
|
; X86-SSE-LABEL: f10:
|
|
|
|
; X86-SSE: # %bb.0: # %entry
|
|
|
|
; X86-SSE-NEXT: subl $12, %esp
|
|
|
|
; X86-SSE-NEXT: .cfi_def_cfa_offset 16
|
|
|
|
; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
|
|
|
|
; X86-SSE-NEXT: movsd %xmm0, (%esp)
|
|
|
|
; X86-SSE-NEXT: calll exp
|
|
|
|
; X86-SSE-NEXT: addl $12, %esp
|
|
|
|
; X86-SSE-NEXT: .cfi_def_cfa_offset 4
|
|
|
|
; X86-SSE-NEXT: retl
|
|
|
|
;
|
2019-11-12 07:42:25 +08:00
|
|
|
; SSE-LABEL: f10:
|
|
|
|
; SSE: # %bb.0: # %entry
|
2019-11-19 03:14:13 +08:00
|
|
|
; SSE-NEXT: pushq %rax
|
|
|
|
; SSE-NEXT: .cfi_def_cfa_offset 16
|
2019-11-12 07:42:25 +08:00
|
|
|
; SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
|
2019-11-19 03:14:13 +08:00
|
|
|
; SSE-NEXT: callq exp
|
|
|
|
; SSE-NEXT: popq %rax
|
|
|
|
; SSE-NEXT: .cfi_def_cfa_offset 8
|
|
|
|
; SSE-NEXT: retq
|
2019-11-12 07:42:25 +08:00
|
|
|
;
|
|
|
|
; AVX-LABEL: f10:
|
|
|
|
; AVX: # %bb.0: # %entry
|
2019-11-19 03:14:13 +08:00
|
|
|
; AVX-NEXT: pushq %rax
|
|
|
|
; AVX-NEXT: .cfi_def_cfa_offset 16
|
2019-11-12 07:42:25 +08:00
|
|
|
; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
|
2019-11-19 03:14:13 +08:00
|
|
|
; AVX-NEXT: callq exp
|
|
|
|
; AVX-NEXT: popq %rax
|
|
|
|
; AVX-NEXT: .cfi_def_cfa_offset 8
|
|
|
|
; AVX-NEXT: retq
|
2017-05-26 05:31:00 +08:00
|
|
|
entry:
|
|
|
|
%result = call double @llvm.experimental.constrained.exp.f64(double 42.0,
|
|
|
|
metadata !"round.dynamic",
|
2019-10-05 01:03:46 +08:00
|
|
|
metadata !"fpexcept.strict") #0
|
2017-05-26 05:31:00 +08:00
|
|
|
ret double %result
|
|
|
|
}
|
|
|
|
|
|
|
|
; Verify that exp2(42.1) isn't simplified when the rounding mode is unknown.
|
2019-10-05 01:03:46 +08:00
|
|
|
define double @f11() #0 {
|
2019-11-20 07:51:19 +08:00
|
|
|
; X87-LABEL: f11:
|
|
|
|
; X87: # %bb.0: # %entry
|
|
|
|
; X87-NEXT: subl $12, %esp
|
|
|
|
; X87-NEXT: .cfi_def_cfa_offset 16
|
|
|
|
; X87-NEXT: fldl {{\.LCPI.*}}
|
|
|
|
; X87-NEXT: fstpl (%esp)
|
|
|
|
; X87-NEXT: calll exp2
|
|
|
|
; X87-NEXT: addl $12, %esp
|
|
|
|
; X87-NEXT: .cfi_def_cfa_offset 4
|
|
|
|
; X87-NEXT: retl
|
|
|
|
;
|
2019-11-18 11:58:11 +08:00
|
|
|
; X86-SSE-LABEL: f11:
|
|
|
|
; X86-SSE: # %bb.0: # %entry
|
|
|
|
; X86-SSE-NEXT: subl $12, %esp
|
|
|
|
; X86-SSE-NEXT: .cfi_def_cfa_offset 16
|
|
|
|
; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
|
|
|
|
; X86-SSE-NEXT: movsd %xmm0, (%esp)
|
|
|
|
; X86-SSE-NEXT: calll exp2
|
|
|
|
; X86-SSE-NEXT: addl $12, %esp
|
|
|
|
; X86-SSE-NEXT: .cfi_def_cfa_offset 4
|
|
|
|
; X86-SSE-NEXT: retl
|
|
|
|
;
|
2019-11-12 07:42:25 +08:00
|
|
|
; SSE-LABEL: f11:
|
|
|
|
; SSE: # %bb.0: # %entry
|
2019-11-19 03:14:13 +08:00
|
|
|
; SSE-NEXT: pushq %rax
|
|
|
|
; SSE-NEXT: .cfi_def_cfa_offset 16
|
2019-11-12 07:42:25 +08:00
|
|
|
; SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
|
2019-11-19 03:14:13 +08:00
|
|
|
; SSE-NEXT: callq exp2
|
|
|
|
; SSE-NEXT: popq %rax
|
|
|
|
; SSE-NEXT: .cfi_def_cfa_offset 8
|
|
|
|
; SSE-NEXT: retq
|
2019-11-12 07:42:25 +08:00
|
|
|
;
|
|
|
|
; AVX-LABEL: f11:
|
|
|
|
; AVX: # %bb.0: # %entry
|
2019-11-19 03:14:13 +08:00
|
|
|
; AVX-NEXT: pushq %rax
|
|
|
|
; AVX-NEXT: .cfi_def_cfa_offset 16
|
2019-11-12 07:42:25 +08:00
|
|
|
; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
|
2019-11-19 03:14:13 +08:00
|
|
|
; AVX-NEXT: callq exp2
|
|
|
|
; AVX-NEXT: popq %rax
|
|
|
|
; AVX-NEXT: .cfi_def_cfa_offset 8
|
|
|
|
; AVX-NEXT: retq
|
2017-05-26 05:31:00 +08:00
|
|
|
entry:
|
|
|
|
%result = call double @llvm.experimental.constrained.exp2.f64(double 42.1,
|
|
|
|
metadata !"round.dynamic",
|
2019-10-05 01:03:46 +08:00
|
|
|
metadata !"fpexcept.strict") #0
|
2017-05-26 05:31:00 +08:00
|
|
|
ret double %result
|
|
|
|
}
|
|
|
|
|
|
|
|
; Verify that log(42.0) isn't simplified when the rounding mode is unknown.
|
2019-10-05 01:03:46 +08:00
|
|
|
define double @f12() #0 {
|
2019-11-20 07:51:19 +08:00
|
|
|
; X87-LABEL: f12:
|
|
|
|
; X87: # %bb.0: # %entry
|
|
|
|
; X87-NEXT: subl $12, %esp
|
|
|
|
; X87-NEXT: .cfi_def_cfa_offset 16
|
|
|
|
; X87-NEXT: flds {{\.LCPI.*}}
|
|
|
|
; X87-NEXT: fstpl (%esp)
|
|
|
|
; X87-NEXT: calll log
|
|
|
|
; X87-NEXT: addl $12, %esp
|
|
|
|
; X87-NEXT: .cfi_def_cfa_offset 4
|
|
|
|
; X87-NEXT: retl
|
|
|
|
;
|
2019-11-18 11:58:11 +08:00
|
|
|
; X86-SSE-LABEL: f12:
|
|
|
|
; X86-SSE: # %bb.0: # %entry
|
|
|
|
; X86-SSE-NEXT: subl $12, %esp
|
|
|
|
; X86-SSE-NEXT: .cfi_def_cfa_offset 16
|
|
|
|
; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
|
|
|
|
; X86-SSE-NEXT: movsd %xmm0, (%esp)
|
|
|
|
; X86-SSE-NEXT: calll log
|
|
|
|
; X86-SSE-NEXT: addl $12, %esp
|
|
|
|
; X86-SSE-NEXT: .cfi_def_cfa_offset 4
|
|
|
|
; X86-SSE-NEXT: retl
|
|
|
|
;
|
2019-11-12 07:42:25 +08:00
|
|
|
; SSE-LABEL: f12:
|
|
|
|
; SSE: # %bb.0: # %entry
|
2019-11-19 03:14:13 +08:00
|
|
|
; SSE-NEXT: pushq %rax
|
|
|
|
; SSE-NEXT: .cfi_def_cfa_offset 16
|
2019-11-12 07:42:25 +08:00
|
|
|
; SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
|
2019-11-19 03:14:13 +08:00
|
|
|
; SSE-NEXT: callq log
|
|
|
|
; SSE-NEXT: popq %rax
|
|
|
|
; SSE-NEXT: .cfi_def_cfa_offset 8
|
|
|
|
; SSE-NEXT: retq
|
2019-11-12 07:42:25 +08:00
|
|
|
;
|
|
|
|
; AVX-LABEL: f12:
|
|
|
|
; AVX: # %bb.0: # %entry
|
2019-11-19 03:14:13 +08:00
|
|
|
; AVX-NEXT: pushq %rax
|
|
|
|
; AVX-NEXT: .cfi_def_cfa_offset 16
|
2019-11-12 07:42:25 +08:00
|
|
|
; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
|
2019-11-19 03:14:13 +08:00
|
|
|
; AVX-NEXT: callq log
|
|
|
|
; AVX-NEXT: popq %rax
|
|
|
|
; AVX-NEXT: .cfi_def_cfa_offset 8
|
|
|
|
; AVX-NEXT: retq
|
2017-05-26 05:31:00 +08:00
|
|
|
entry:
|
|
|
|
%result = call double @llvm.experimental.constrained.log.f64(double 42.0,
|
|
|
|
metadata !"round.dynamic",
|
2019-10-05 01:03:46 +08:00
|
|
|
metadata !"fpexcept.strict") #0
|
2017-05-26 05:31:00 +08:00
|
|
|
ret double %result
|
|
|
|
}
|
|
|
|
|
|
|
|
; Verify that log10(42.0) isn't simplified when the rounding mode is unknown.
|
2019-10-05 01:03:46 +08:00
|
|
|
define double @f13() #0 {
|
2019-11-20 07:51:19 +08:00
|
|
|
; X87-LABEL: f13:
|
|
|
|
; X87: # %bb.0: # %entry
|
|
|
|
; X87-NEXT: subl $12, %esp
|
|
|
|
; X87-NEXT: .cfi_def_cfa_offset 16
|
|
|
|
; X87-NEXT: flds {{\.LCPI.*}}
|
|
|
|
; X87-NEXT: fstpl (%esp)
|
|
|
|
; X87-NEXT: calll log10
|
|
|
|
; X87-NEXT: addl $12, %esp
|
|
|
|
; X87-NEXT: .cfi_def_cfa_offset 4
|
|
|
|
; X87-NEXT: retl
|
|
|
|
;
|
2019-11-18 11:58:11 +08:00
|
|
|
; X86-SSE-LABEL: f13:
|
|
|
|
; X86-SSE: # %bb.0: # %entry
|
|
|
|
; X86-SSE-NEXT: subl $12, %esp
|
|
|
|
; X86-SSE-NEXT: .cfi_def_cfa_offset 16
|
|
|
|
; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
|
|
|
|
; X86-SSE-NEXT: movsd %xmm0, (%esp)
|
|
|
|
; X86-SSE-NEXT: calll log10
|
|
|
|
; X86-SSE-NEXT: addl $12, %esp
|
|
|
|
; X86-SSE-NEXT: .cfi_def_cfa_offset 4
|
|
|
|
; X86-SSE-NEXT: retl
|
|
|
|
;
|
2019-11-12 07:42:25 +08:00
|
|
|
; SSE-LABEL: f13:
|
|
|
|
; SSE: # %bb.0: # %entry
|
2019-11-19 03:14:13 +08:00
|
|
|
; SSE-NEXT: pushq %rax
|
|
|
|
; SSE-NEXT: .cfi_def_cfa_offset 16
|
2019-11-12 07:42:25 +08:00
|
|
|
; SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
|
2019-11-19 03:14:13 +08:00
|
|
|
; SSE-NEXT: callq log10
|
|
|
|
; SSE-NEXT: popq %rax
|
|
|
|
; SSE-NEXT: .cfi_def_cfa_offset 8
|
|
|
|
; SSE-NEXT: retq
|
2019-11-12 07:42:25 +08:00
|
|
|
;
|
|
|
|
; AVX-LABEL: f13:
|
|
|
|
; AVX: # %bb.0: # %entry
|
2019-11-19 03:14:13 +08:00
|
|
|
; AVX-NEXT: pushq %rax
|
|
|
|
; AVX-NEXT: .cfi_def_cfa_offset 16
|
2019-11-12 07:42:25 +08:00
|
|
|
; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
|
2019-11-19 03:14:13 +08:00
|
|
|
; AVX-NEXT: callq log10
|
|
|
|
; AVX-NEXT: popq %rax
|
|
|
|
; AVX-NEXT: .cfi_def_cfa_offset 8
|
|
|
|
; AVX-NEXT: retq
|
2017-05-26 05:31:00 +08:00
|
|
|
entry:
|
|
|
|
%result = call double @llvm.experimental.constrained.log10.f64(double 42.0,
|
|
|
|
metadata !"round.dynamic",
|
2019-10-05 01:03:46 +08:00
|
|
|
metadata !"fpexcept.strict") #0
|
2017-05-26 05:31:00 +08:00
|
|
|
ret double %result
|
|
|
|
}
|
|
|
|
|
|
|
|
; Verify that log2(42.0) isn't simplified when the rounding mode is unknown.
|
2019-10-05 01:03:46 +08:00
|
|
|
define double @f14() #0 {
|
2019-11-20 07:51:19 +08:00
|
|
|
; X87-LABEL: f14:
|
|
|
|
; X87: # %bb.0: # %entry
|
|
|
|
; X87-NEXT: subl $12, %esp
|
|
|
|
; X87-NEXT: .cfi_def_cfa_offset 16
|
|
|
|
; X87-NEXT: flds {{\.LCPI.*}}
|
|
|
|
; X87-NEXT: fstpl (%esp)
|
|
|
|
; X87-NEXT: calll log2
|
|
|
|
; X87-NEXT: addl $12, %esp
|
|
|
|
; X87-NEXT: .cfi_def_cfa_offset 4
|
|
|
|
; X87-NEXT: retl
|
|
|
|
;
|
2019-11-18 11:58:11 +08:00
|
|
|
; X86-SSE-LABEL: f14:
|
|
|
|
; X86-SSE: # %bb.0: # %entry
|
|
|
|
; X86-SSE-NEXT: subl $12, %esp
|
|
|
|
; X86-SSE-NEXT: .cfi_def_cfa_offset 16
|
|
|
|
; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
|
|
|
|
; X86-SSE-NEXT: movsd %xmm0, (%esp)
|
|
|
|
; X86-SSE-NEXT: calll log2
|
|
|
|
; X86-SSE-NEXT: addl $12, %esp
|
|
|
|
; X86-SSE-NEXT: .cfi_def_cfa_offset 4
|
|
|
|
; X86-SSE-NEXT: retl
|
|
|
|
;
|
2019-11-12 07:42:25 +08:00
|
|
|
; SSE-LABEL: f14:
|
|
|
|
; SSE: # %bb.0: # %entry
|
2019-11-19 03:14:13 +08:00
|
|
|
; SSE-NEXT: pushq %rax
|
|
|
|
; SSE-NEXT: .cfi_def_cfa_offset 16
|
2019-11-12 07:42:25 +08:00
|
|
|
; SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
|
2019-11-19 03:14:13 +08:00
|
|
|
; SSE-NEXT: callq log2
|
|
|
|
; SSE-NEXT: popq %rax
|
|
|
|
; SSE-NEXT: .cfi_def_cfa_offset 8
|
|
|
|
; SSE-NEXT: retq
|
2019-11-12 07:42:25 +08:00
|
|
|
;
|
|
|
|
; AVX-LABEL: f14:
|
|
|
|
; AVX: # %bb.0: # %entry
|
2019-11-19 03:14:13 +08:00
|
|
|
; AVX-NEXT: pushq %rax
|
|
|
|
; AVX-NEXT: .cfi_def_cfa_offset 16
|
2019-11-12 07:42:25 +08:00
|
|
|
; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
|
2019-11-19 03:14:13 +08:00
|
|
|
; AVX-NEXT: callq log2
|
|
|
|
; AVX-NEXT: popq %rax
|
|
|
|
; AVX-NEXT: .cfi_def_cfa_offset 8
|
|
|
|
; AVX-NEXT: retq
|
2017-05-26 05:31:00 +08:00
|
|
|
entry:
|
|
|
|
%result = call double @llvm.experimental.constrained.log2.f64(double 42.0,
|
|
|
|
metadata !"round.dynamic",
|
2019-10-05 01:03:46 +08:00
|
|
|
metadata !"fpexcept.strict") #0
|
2017-05-26 05:31:00 +08:00
|
|
|
ret double %result
|
|
|
|
}
|
|
|
|
|
|
|
|
; Verify that rint(42.1) isn't simplified when the rounding mode is unknown.
|
2019-10-05 01:03:46 +08:00
|
|
|
define double @f15() #0 {
|
2019-11-20 07:51:19 +08:00
|
|
|
; X87-LABEL: f15:
|
|
|
|
; X87: # %bb.0: # %entry
|
|
|
|
; X87-NEXT: subl $12, %esp
|
|
|
|
; X87-NEXT: .cfi_def_cfa_offset 16
|
|
|
|
; X87-NEXT: fldl {{\.LCPI.*}}
|
|
|
|
; X87-NEXT: fstpl (%esp)
|
|
|
|
; X87-NEXT: calll rint
|
|
|
|
; X87-NEXT: addl $12, %esp
|
|
|
|
; X87-NEXT: .cfi_def_cfa_offset 4
|
|
|
|
; X87-NEXT: retl
|
|
|
|
;
|
2019-11-18 11:58:11 +08:00
|
|
|
; X86-SSE-LABEL: f15:
|
|
|
|
; X86-SSE: # %bb.0: # %entry
|
|
|
|
; X86-SSE-NEXT: subl $12, %esp
|
|
|
|
; X86-SSE-NEXT: .cfi_def_cfa_offset 16
|
|
|
|
; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
|
|
|
|
; X86-SSE-NEXT: movsd %xmm0, (%esp)
|
|
|
|
; X86-SSE-NEXT: calll rint
|
|
|
|
; X86-SSE-NEXT: addl $12, %esp
|
|
|
|
; X86-SSE-NEXT: .cfi_def_cfa_offset 4
|
|
|
|
; X86-SSE-NEXT: retl
|
|
|
|
;
|
2019-11-12 07:42:25 +08:00
|
|
|
; SSE-LABEL: f15:
|
|
|
|
; SSE: # %bb.0: # %entry
|
2019-11-19 03:14:13 +08:00
|
|
|
; SSE-NEXT: pushq %rax
|
|
|
|
; SSE-NEXT: .cfi_def_cfa_offset 16
|
2019-11-12 07:42:25 +08:00
|
|
|
; SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
|
2019-11-19 03:14:13 +08:00
|
|
|
; SSE-NEXT: callq rint
|
|
|
|
; SSE-NEXT: popq %rax
|
|
|
|
; SSE-NEXT: .cfi_def_cfa_offset 8
|
|
|
|
; SSE-NEXT: retq
|
2019-11-12 07:42:25 +08:00
|
|
|
;
|
|
|
|
; AVX-LABEL: f15:
|
|
|
|
; AVX: # %bb.0: # %entry
|
|
|
|
; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
|
|
|
|
; AVX-NEXT: vroundsd $4, %xmm0, %xmm0, %xmm0
|
|
|
|
; AVX-NEXT: retq
|
2017-05-26 05:31:00 +08:00
|
|
|
entry:
|
|
|
|
%result = call double @llvm.experimental.constrained.rint.f64(double 42.1,
|
|
|
|
metadata !"round.dynamic",
|
2019-10-05 01:03:46 +08:00
|
|
|
metadata !"fpexcept.strict") #0
|
2017-05-26 05:31:00 +08:00
|
|
|
ret double %result
|
|
|
|
}
|
|
|
|
|
|
|
|
; Verify that nearbyint(42.1) isn't simplified when the rounding mode is
|
|
|
|
; unknown.
|
2019-10-05 01:03:46 +08:00
|
|
|
define double @f16() #0 {
|
2019-11-20 07:51:19 +08:00
|
|
|
; X87-LABEL: f16:
|
|
|
|
; X87: # %bb.0: # %entry
|
|
|
|
; X87-NEXT: subl $12, %esp
|
|
|
|
; X87-NEXT: .cfi_def_cfa_offset 16
|
|
|
|
; X87-NEXT: fldl {{\.LCPI.*}}
|
|
|
|
; X87-NEXT: fstpl (%esp)
|
|
|
|
; X87-NEXT: calll nearbyint
|
|
|
|
; X87-NEXT: addl $12, %esp
|
|
|
|
; X87-NEXT: .cfi_def_cfa_offset 4
|
|
|
|
; X87-NEXT: retl
|
|
|
|
;
|
2019-11-18 11:58:11 +08:00
|
|
|
; X86-SSE-LABEL: f16:
|
|
|
|
; X86-SSE: # %bb.0: # %entry
|
|
|
|
; X86-SSE-NEXT: subl $12, %esp
|
|
|
|
; X86-SSE-NEXT: .cfi_def_cfa_offset 16
|
|
|
|
; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
|
|
|
|
; X86-SSE-NEXT: movsd %xmm0, (%esp)
|
|
|
|
; X86-SSE-NEXT: calll nearbyint
|
|
|
|
; X86-SSE-NEXT: addl $12, %esp
|
|
|
|
; X86-SSE-NEXT: .cfi_def_cfa_offset 4
|
|
|
|
; X86-SSE-NEXT: retl
|
|
|
|
;
|
2019-11-12 07:42:25 +08:00
|
|
|
; SSE-LABEL: f16:
|
|
|
|
; SSE: # %bb.0: # %entry
|
2019-11-19 03:14:13 +08:00
|
|
|
; SSE-NEXT: pushq %rax
|
|
|
|
; SSE-NEXT: .cfi_def_cfa_offset 16
|
2019-11-12 07:42:25 +08:00
|
|
|
; SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
|
2019-11-19 03:14:13 +08:00
|
|
|
; SSE-NEXT: callq nearbyint
|
|
|
|
; SSE-NEXT: popq %rax
|
|
|
|
; SSE-NEXT: .cfi_def_cfa_offset 8
|
|
|
|
; SSE-NEXT: retq
|
2019-11-12 07:42:25 +08:00
|
|
|
;
|
|
|
|
; AVX-LABEL: f16:
|
|
|
|
; AVX: # %bb.0: # %entry
|
|
|
|
; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
|
|
|
|
; AVX-NEXT: vroundsd $12, %xmm0, %xmm0, %xmm0
|
|
|
|
; AVX-NEXT: retq
|
2017-05-26 05:31:00 +08:00
|
|
|
entry:
|
|
|
|
%result = call double @llvm.experimental.constrained.nearbyint.f64(
|
|
|
|
double 42.1,
|
|
|
|
metadata !"round.dynamic",
|
2019-10-05 01:03:46 +08:00
|
|
|
metadata !"fpexcept.strict") #0
|
2017-05-26 05:31:00 +08:00
|
|
|
ret double %result
|
|
|
|
}
|
2017-01-27 07:27:59 +08:00
|
|
|
|
2019-10-05 01:03:46 +08:00
|
|
|
define double @f19() #0 {
|
2019-11-20 07:51:19 +08:00
|
|
|
; X87-LABEL: f19:
|
|
|
|
; X87: # %bb.0: # %entry
|
|
|
|
; X87-NEXT: subl $28, %esp
|
|
|
|
; X87-NEXT: .cfi_def_cfa_offset 32
|
|
|
|
; X87-NEXT: flds {{\.LCPI.*}}
|
|
|
|
; X87-NEXT: fstpl {{[0-9]+}}(%esp)
|
|
|
|
; X87-NEXT: movl $1072693248, {{[0-9]+}}(%esp) # imm = 0x3FF00000
|
|
|
|
; X87-NEXT: movl $0, (%esp)
|
|
|
|
; X87-NEXT: calll fmod
|
|
|
|
; X87-NEXT: addl $28, %esp
|
|
|
|
; X87-NEXT: .cfi_def_cfa_offset 4
|
|
|
|
; X87-NEXT: retl
|
|
|
|
;
|
2019-11-18 11:58:11 +08:00
|
|
|
; X86-SSE-LABEL: f19:
|
|
|
|
; X86-SSE: # %bb.0: # %entry
|
|
|
|
; X86-SSE-NEXT: subl $28, %esp
|
|
|
|
; X86-SSE-NEXT: .cfi_def_cfa_offset 32
|
|
|
|
; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
|
|
|
|
; X86-SSE-NEXT: movsd %xmm0, {{[0-9]+}}(%esp)
|
|
|
|
; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
|
|
|
|
; X86-SSE-NEXT: movsd %xmm0, (%esp)
|
|
|
|
; X86-SSE-NEXT: calll fmod
|
|
|
|
; X86-SSE-NEXT: addl $28, %esp
|
|
|
|
; X86-SSE-NEXT: .cfi_def_cfa_offset 4
|
|
|
|
; X86-SSE-NEXT: retl
|
|
|
|
;
|
2019-11-12 07:42:25 +08:00
|
|
|
; SSE-LABEL: f19:
|
|
|
|
; SSE: # %bb.0: # %entry
|
2019-11-19 03:14:13 +08:00
|
|
|
; SSE-NEXT: pushq %rax
|
|
|
|
; SSE-NEXT: .cfi_def_cfa_offset 16
|
2019-11-12 07:42:25 +08:00
|
|
|
; SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
|
|
|
|
; SSE-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
|
2019-11-19 03:14:13 +08:00
|
|
|
; SSE-NEXT: callq fmod
|
|
|
|
; SSE-NEXT: popq %rax
|
|
|
|
; SSE-NEXT: .cfi_def_cfa_offset 8
|
|
|
|
; SSE-NEXT: retq
|
2019-11-12 07:42:25 +08:00
|
|
|
;
|
|
|
|
; AVX-LABEL: f19:
|
|
|
|
; AVX: # %bb.0: # %entry
|
2019-11-19 03:14:13 +08:00
|
|
|
; AVX-NEXT: pushq %rax
|
|
|
|
; AVX-NEXT: .cfi_def_cfa_offset 16
|
2019-11-12 07:42:25 +08:00
|
|
|
; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
|
|
|
|
; AVX-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero
|
2019-11-19 03:14:13 +08:00
|
|
|
; AVX-NEXT: callq fmod
|
|
|
|
; AVX-NEXT: popq %rax
|
|
|
|
; AVX-NEXT: .cfi_def_cfa_offset 8
|
|
|
|
; AVX-NEXT: retq
|
2018-08-21 03:28:56 +08:00
|
|
|
entry:
|
|
|
|
%rem = call double @llvm.experimental.constrained.frem.f64(
|
|
|
|
double 1.000000e+00,
|
|
|
|
double 1.000000e+01,
|
|
|
|
metadata !"round.dynamic",
|
2019-10-05 01:03:46 +08:00
|
|
|
metadata !"fpexcept.strict") #0
|
2018-08-21 03:28:56 +08:00
|
|
|
ret double %rem
|
|
|
|
}
|
|
|
|
|
2019-11-20 08:07:50 +08:00
|
|
|
; Verify that fptosi(%x) isn't simplified when the rounding mode is
|
|
|
|
; unknown.
|
|
|
|
; Verify that no gross errors happen.
|
|
|
|
; FIXME: The SSE/AVX code does not raise an invalid exception for all values
|
|
|
|
; that don't fit in i8.
|
|
|
|
define i8 @f20s8(double %x) #0 {
|
|
|
|
; X87-LABEL: f20s8:
|
|
|
|
; X87: # %bb.0: # %entry
|
|
|
|
; X87-NEXT: subl $8, %esp
|
|
|
|
; X87-NEXT: .cfi_def_cfa_offset 12
|
|
|
|
; X87-NEXT: fldl {{[0-9]+}}(%esp)
|
|
|
|
; X87-NEXT: fnstcw {{[0-9]+}}(%esp)
|
|
|
|
; X87-NEXT: movzwl {{[0-9]+}}(%esp), %eax
|
|
|
|
; X87-NEXT: orl $3072, %eax # imm = 0xC00
|
|
|
|
; X87-NEXT: movw %ax, {{[0-9]+}}(%esp)
|
|
|
|
; X87-NEXT: fldcw {{[0-9]+}}(%esp)
|
|
|
|
; X87-NEXT: fistps {{[0-9]+}}(%esp)
|
|
|
|
; X87-NEXT: fldcw {{[0-9]+}}(%esp)
|
|
|
|
; X87-NEXT: movb {{[0-9]+}}(%esp), %al
|
|
|
|
; X87-NEXT: addl $8, %esp
|
|
|
|
; X87-NEXT: .cfi_def_cfa_offset 4
|
|
|
|
; X87-NEXT: retl
|
|
|
|
;
|
|
|
|
; X86-SSE-LABEL: f20s8:
|
|
|
|
; X86-SSE: # %bb.0: # %entry
|
|
|
|
; X86-SSE-NEXT: cvttsd2si {{[0-9]+}}(%esp), %eax
|
|
|
|
; X86-SSE-NEXT: # kill: def $al killed $al killed $eax
|
|
|
|
; X86-SSE-NEXT: retl
|
|
|
|
;
|
|
|
|
; SSE-LABEL: f20s8:
|
|
|
|
; SSE: # %bb.0: # %entry
|
|
|
|
; SSE-NEXT: cvttsd2si %xmm0, %eax
|
|
|
|
; SSE-NEXT: # kill: def $al killed $al killed $eax
|
|
|
|
; SSE-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX-LABEL: f20s8:
|
|
|
|
; AVX: # %bb.0: # %entry
|
|
|
|
; AVX-NEXT: vcvttsd2si %xmm0, %eax
|
|
|
|
; AVX-NEXT: # kill: def $al killed $al killed $eax
|
|
|
|
; AVX-NEXT: retq
|
|
|
|
entry:
|
|
|
|
%result = call i8 @llvm.experimental.constrained.fptosi.i8.f64(double %x,
|
|
|
|
metadata !"fpexcept.strict") #0
|
|
|
|
ret i8 %result
|
|
|
|
}
|
|
|
|
|
2019-11-12 15:30:55 +08:00
|
|
|
; Verify that fptosi(%x) isn't simplified when the rounding mode is
|
2019-11-20 07:51:19 +08:00
|
|
|
; unknown.
|
|
|
|
; Verify that no gross errors happen.
|
|
|
|
; FIXME: The SSE/AVX code does not raise an invalid exception for all values
|
|
|
|
; that don't fit in i16.
|
|
|
|
define i16 @f20s16(double %x) #0 {
|
|
|
|
; X87-LABEL: f20s16:
|
|
|
|
; X87: # %bb.0: # %entry
|
|
|
|
; X87-NEXT: subl $8, %esp
|
|
|
|
; X87-NEXT: .cfi_def_cfa_offset 12
|
|
|
|
; X87-NEXT: fldl {{[0-9]+}}(%esp)
|
|
|
|
; X87-NEXT: fnstcw {{[0-9]+}}(%esp)
|
|
|
|
; X87-NEXT: movzwl {{[0-9]+}}(%esp), %eax
|
|
|
|
; X87-NEXT: orl $3072, %eax # imm = 0xC00
|
|
|
|
; X87-NEXT: movw %ax, {{[0-9]+}}(%esp)
|
|
|
|
; X87-NEXT: fldcw {{[0-9]+}}(%esp)
|
|
|
|
; X87-NEXT: fistps {{[0-9]+}}(%esp)
|
|
|
|
; X87-NEXT: fldcw {{[0-9]+}}(%esp)
|
|
|
|
; X87-NEXT: movzwl {{[0-9]+}}(%esp), %eax
|
|
|
|
; X87-NEXT: addl $8, %esp
|
|
|
|
; X87-NEXT: .cfi_def_cfa_offset 4
|
|
|
|
; X87-NEXT: retl
|
|
|
|
;
|
|
|
|
; X86-SSE-LABEL: f20s16:
|
|
|
|
; X86-SSE: # %bb.0: # %entry
|
|
|
|
; X86-SSE-NEXT: cvttsd2si {{[0-9]+}}(%esp), %eax
|
|
|
|
; X86-SSE-NEXT: # kill: def $ax killed $ax killed $eax
|
|
|
|
; X86-SSE-NEXT: retl
|
|
|
|
;
|
|
|
|
; SSE-LABEL: f20s16:
|
|
|
|
; SSE: # %bb.0: # %entry
|
|
|
|
; SSE-NEXT: cvttsd2si %xmm0, %eax
|
|
|
|
; SSE-NEXT: # kill: def $ax killed $ax killed $eax
|
|
|
|
; SSE-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX-LABEL: f20s16:
|
|
|
|
; AVX: # %bb.0: # %entry
|
|
|
|
; AVX-NEXT: vcvttsd2si %xmm0, %eax
|
|
|
|
; AVX-NEXT: # kill: def $ax killed $ax killed $eax
|
|
|
|
; AVX-NEXT: retq
|
|
|
|
entry:
|
|
|
|
%result = call i16 @llvm.experimental.constrained.fptosi.i16.f64(double %x,
|
|
|
|
metadata !"fpexcept.strict") #0
|
|
|
|
ret i16 %result
|
|
|
|
}
|
|
|
|
|
|
|
|
; Verify that fptosi(%x) isn't simplified when the rounding mode is
|
|
|
|
; unknown.
|
2019-11-12 15:30:55 +08:00
|
|
|
; Verify that no gross errors happen.
|
|
|
|
define i32 @f20s(double %x) #0 {
|
2019-11-20 07:51:19 +08:00
|
|
|
; X87-LABEL: f20s:
|
|
|
|
; X87: # %bb.0: # %entry
|
|
|
|
; X87-NEXT: subl $8, %esp
|
|
|
|
; X87-NEXT: .cfi_def_cfa_offset 12
|
|
|
|
; X87-NEXT: fldl {{[0-9]+}}(%esp)
|
|
|
|
; X87-NEXT: fnstcw (%esp)
|
|
|
|
; X87-NEXT: movzwl (%esp), %eax
|
|
|
|
; X87-NEXT: orl $3072, %eax # imm = 0xC00
|
|
|
|
; X87-NEXT: movw %ax, {{[0-9]+}}(%esp)
|
|
|
|
; X87-NEXT: fldcw {{[0-9]+}}(%esp)
|
|
|
|
; X87-NEXT: fistpl {{[0-9]+}}(%esp)
|
|
|
|
; X87-NEXT: fldcw (%esp)
|
|
|
|
; X87-NEXT: movl {{[0-9]+}}(%esp), %eax
|
|
|
|
; X87-NEXT: addl $8, %esp
|
|
|
|
; X87-NEXT: .cfi_def_cfa_offset 4
|
|
|
|
; X87-NEXT: retl
|
|
|
|
;
|
2019-11-18 11:58:11 +08:00
|
|
|
; X86-SSE-LABEL: f20s:
|
|
|
|
; X86-SSE: # %bb.0: # %entry
|
|
|
|
; X86-SSE-NEXT: cvttsd2si {{[0-9]+}}(%esp), %eax
|
|
|
|
; X86-SSE-NEXT: retl
|
|
|
|
;
|
2019-11-12 15:30:55 +08:00
|
|
|
; SSE-LABEL: f20s:
|
|
|
|
; SSE: # %bb.0: # %entry
|
|
|
|
; SSE-NEXT: cvttsd2si %xmm0, %eax
|
|
|
|
; SSE-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX-LABEL: f20s:
|
|
|
|
; AVX: # %bb.0: # %entry
|
|
|
|
; AVX-NEXT: vcvttsd2si %xmm0, %eax
|
|
|
|
; AVX-NEXT: retq
|
|
|
|
entry:
|
|
|
|
%result = call i32 @llvm.experimental.constrained.fptosi.i32.f64(double %x,
|
|
|
|
metadata !"fpexcept.strict") #0
|
|
|
|
ret i32 %result
|
|
|
|
}
|
|
|
|
|
2019-08-29 00:33:36 +08:00
|
|
|
; Verify that fptoui(%x) isn't simplified when the rounding mode is
|
2019-11-20 07:51:19 +08:00
|
|
|
; unknown.
|
|
|
|
; Verify that no gross errors happen.
|
|
|
|
; FIXME: This code generates spurious inexact exceptions.
|
|
|
|
define i64 @f20s64(double %x) #0 {
|
|
|
|
; X87-LABEL: f20s64:
|
|
|
|
; X87: # %bb.0: # %entry
|
|
|
|
; X87-NEXT: subl $20, %esp
|
|
|
|
; X87-NEXT: .cfi_def_cfa_offset 24
|
|
|
|
; X87-NEXT: fldl {{[0-9]+}}(%esp)
|
|
|
|
; X87-NEXT: fnstcw {{[0-9]+}}(%esp)
|
|
|
|
; X87-NEXT: movzwl {{[0-9]+}}(%esp), %eax
|
|
|
|
; X87-NEXT: orl $3072, %eax # imm = 0xC00
|
|
|
|
; X87-NEXT: movw %ax, {{[0-9]+}}(%esp)
|
|
|
|
; X87-NEXT: fldcw {{[0-9]+}}(%esp)
|
|
|
|
; X87-NEXT: fistpll {{[0-9]+}}(%esp)
|
|
|
|
; X87-NEXT: fldcw {{[0-9]+}}(%esp)
|
|
|
|
; X87-NEXT: movl {{[0-9]+}}(%esp), %eax
|
|
|
|
; X87-NEXT: movl {{[0-9]+}}(%esp), %edx
|
|
|
|
; X87-NEXT: addl $20, %esp
|
|
|
|
; X87-NEXT: .cfi_def_cfa_offset 4
|
|
|
|
; X87-NEXT: retl
|
|
|
|
;
|
|
|
|
; X86-SSE-LABEL: f20s64:
|
|
|
|
; X86-SSE: # %bb.0: # %entry
|
|
|
|
; X86-SSE-NEXT: subl $20, %esp
|
|
|
|
; X86-SSE-NEXT: .cfi_def_cfa_offset 24
|
|
|
|
; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
|
|
|
|
; X86-SSE-NEXT: movsd %xmm0, {{[0-9]+}}(%esp)
|
|
|
|
; X86-SSE-NEXT: fldl {{[0-9]+}}(%esp)
|
|
|
|
; X86-SSE-NEXT: fnstcw {{[0-9]+}}(%esp)
|
|
|
|
; X86-SSE-NEXT: movzwl {{[0-9]+}}(%esp), %eax
|
|
|
|
; X86-SSE-NEXT: orl $3072, %eax # imm = 0xC00
|
|
|
|
; X86-SSE-NEXT: movw %ax, {{[0-9]+}}(%esp)
|
|
|
|
; X86-SSE-NEXT: fldcw {{[0-9]+}}(%esp)
|
|
|
|
; X86-SSE-NEXT: fistpll {{[0-9]+}}(%esp)
|
|
|
|
; X86-SSE-NEXT: fldcw {{[0-9]+}}(%esp)
|
|
|
|
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
|
|
|
|
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edx
|
|
|
|
; X86-SSE-NEXT: addl $20, %esp
|
|
|
|
; X86-SSE-NEXT: .cfi_def_cfa_offset 4
|
|
|
|
; X86-SSE-NEXT: retl
|
|
|
|
;
|
|
|
|
; SSE-LABEL: f20s64:
|
|
|
|
; SSE: # %bb.0: # %entry
|
|
|
|
; SSE-NEXT: cvttsd2si %xmm0, %rax
|
|
|
|
; SSE-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX-LABEL: f20s64:
|
|
|
|
; AVX: # %bb.0: # %entry
|
|
|
|
; AVX-NEXT: vcvttsd2si %xmm0, %rax
|
|
|
|
; AVX-NEXT: retq
|
|
|
|
entry:
|
|
|
|
%result = call i64 @llvm.experimental.constrained.fptosi.i64.f64(double %x,
|
|
|
|
metadata !"fpexcept.strict") #0
|
|
|
|
ret i64 %result
|
|
|
|
}
|
|
|
|
|
2019-11-28 09:44:43 +08:00
|
|
|
; Verify that fptoui(%x) isn't simplified when the rounding mode is
|
|
|
|
; unknown.
|
|
|
|
; Verify that no gross errors happen.
|
|
|
|
define i128 @f20s128(double %x) nounwind strictfp {
|
|
|
|
; X87-LABEL: f20s128:
|
|
|
|
; X87: # %bb.0: # %entry
|
|
|
|
; X87-NEXT: pushl %edi
|
|
|
|
; X87-NEXT: pushl %esi
|
|
|
|
; X87-NEXT: subl $36, %esp
|
|
|
|
; X87-NEXT: movl {{[0-9]+}}(%esp), %esi
|
|
|
|
; X87-NEXT: fldl {{[0-9]+}}(%esp)
|
|
|
|
; X87-NEXT: fstpl {{[0-9]+}}(%esp)
|
|
|
|
; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
|
|
|
|
; X87-NEXT: movl %eax, (%esp)
|
|
|
|
; X87-NEXT: calll __fixdfti
|
|
|
|
; X87-NEXT: subl $4, %esp
|
|
|
|
; X87-NEXT: movl {{[0-9]+}}(%esp), %eax
|
|
|
|
; X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
|
|
|
|
; X87-NEXT: movl {{[0-9]+}}(%esp), %edx
|
|
|
|
; X87-NEXT: movl {{[0-9]+}}(%esp), %edi
|
[FPEnv][SelectionDAG] Relax chain requirements
This patch implements the following changes:
1) SelectionDAGBuilder::visitConstrainedFPIntrinsic currently treats
each constrained intrinsic like a global barrier (e.g. a function call)
and fully serializes all pending chains. This is actually not required;
it is allowed for constrained intrinsics to be reordered w.r.t one
another or (nonvolatile) memory accesses. The MI-level scheduler already
allows for that flexibility, so it makes sense to allow it at the DAG
level as well.
This patch therefore changes the way chains for constrained intrisincs
are created, and handles them basically like load operations are handled.
This has the effect that constrained intrinsics are no longer serialized
against one another or (nonvolatile) loads. They are still serialized
against stores, but that seems hard to change with the current DAG chain
setup, and it also doesn't seem to be a big problem preventing DAG
2) The OPC_CheckFoldableChainNode check requires that each of the
intermediate nodes in a multi-node pattern match only has a single use.
This check tends to fail if those intermediate nodes are strict operations
as those have a chain output that typically indeed has another use.
However, we don't really need to consider chains here at all, since they
will all be rewritten anyway by UpdateChains later. Other parts of the
matcher therefore already ignore chains, but this hasOneUse check doesn't.
This patch replaces hasOneUse by a custom test that verifies there is no
more than one use of any non-chain output value.
In theory, this change could affect code unrelated to strict FP nodes,
but at least on SystemZ I could not find any single instance of that
happening
3) The SystemZ back-end currently does not allow matching multiply-and-
extend operations (32x32 -> 64bit or 64x64 -> 128bit FP multiply) for
strict FP operations. This was not possible in the past due to the
problems described under 1) and 2) above.
With those issues fixed, it is now possible to fully support those
instructions in strict mode as well, and this patch does so.
Differential Revision: https://reviews.llvm.org/D70913
2019-12-06 18:02:11 +08:00
|
|
|
; X87-NEXT: movl %edi, 12(%esi)
|
|
|
|
; X87-NEXT: movl %edx, 8(%esi)
|
2019-11-28 09:44:43 +08:00
|
|
|
; X87-NEXT: movl %ecx, 4(%esi)
|
[FPEnv][SelectionDAG] Relax chain requirements
This patch implements the following changes:
1) SelectionDAGBuilder::visitConstrainedFPIntrinsic currently treats
each constrained intrinsic like a global barrier (e.g. a function call)
and fully serializes all pending chains. This is actually not required;
it is allowed for constrained intrinsics to be reordered w.r.t one
another or (nonvolatile) memory accesses. The MI-level scheduler already
allows for that flexibility, so it makes sense to allow it at the DAG
level as well.
This patch therefore changes the way chains for constrained intrisincs
are created, and handles them basically like load operations are handled.
This has the effect that constrained intrinsics are no longer serialized
against one another or (nonvolatile) loads. They are still serialized
against stores, but that seems hard to change with the current DAG chain
setup, and it also doesn't seem to be a big problem preventing DAG
2) The OPC_CheckFoldableChainNode check requires that each of the
intermediate nodes in a multi-node pattern match only has a single use.
This check tends to fail if those intermediate nodes are strict operations
as those have a chain output that typically indeed has another use.
However, we don't really need to consider chains here at all, since they
will all be rewritten anyway by UpdateChains later. Other parts of the
matcher therefore already ignore chains, but this hasOneUse check doesn't.
This patch replaces hasOneUse by a custom test that verifies there is no
more than one use of any non-chain output value.
In theory, this change could affect code unrelated to strict FP nodes,
but at least on SystemZ I could not find any single instance of that
happening
3) The SystemZ back-end currently does not allow matching multiply-and-
extend operations (32x32 -> 64bit or 64x64 -> 128bit FP multiply) for
strict FP operations. This was not possible in the past due to the
problems described under 1) and 2) above.
With those issues fixed, it is now possible to fully support those
instructions in strict mode as well, and this patch does so.
Differential Revision: https://reviews.llvm.org/D70913
2019-12-06 18:02:11 +08:00
|
|
|
; X87-NEXT: movl %eax, (%esi)
|
2019-11-28 09:44:43 +08:00
|
|
|
; X87-NEXT: movl %esi, %eax
|
|
|
|
; X87-NEXT: addl $36, %esp
|
|
|
|
; X87-NEXT: popl %esi
|
|
|
|
; X87-NEXT: popl %edi
|
|
|
|
; X87-NEXT: retl $4
|
|
|
|
;
|
|
|
|
; X86-SSE-LABEL: f20s128:
|
|
|
|
; X86-SSE: # %bb.0: # %entry
|
|
|
|
; X86-SSE-NEXT: pushl %edi
|
|
|
|
; X86-SSE-NEXT: pushl %esi
|
|
|
|
; X86-SSE-NEXT: subl $36, %esp
|
|
|
|
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %esi
|
|
|
|
; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
|
|
|
|
; X86-SSE-NEXT: movsd %xmm0, {{[0-9]+}}(%esp)
|
|
|
|
; X86-SSE-NEXT: leal {{[0-9]+}}(%esp), %eax
|
|
|
|
; X86-SSE-NEXT: movl %eax, (%esp)
|
|
|
|
; X86-SSE-NEXT: calll __fixdfti
|
|
|
|
; X86-SSE-NEXT: subl $4, %esp
|
|
|
|
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
|
|
|
|
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %ecx
|
|
|
|
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edx
|
|
|
|
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edi
|
[FPEnv][SelectionDAG] Relax chain requirements
This patch implements the following changes:
1) SelectionDAGBuilder::visitConstrainedFPIntrinsic currently treats
each constrained intrinsic like a global barrier (e.g. a function call)
and fully serializes all pending chains. This is actually not required;
it is allowed for constrained intrinsics to be reordered w.r.t one
another or (nonvolatile) memory accesses. The MI-level scheduler already
allows for that flexibility, so it makes sense to allow it at the DAG
level as well.
This patch therefore changes the way chains for constrained intrisincs
are created, and handles them basically like load operations are handled.
This has the effect that constrained intrinsics are no longer serialized
against one another or (nonvolatile) loads. They are still serialized
against stores, but that seems hard to change with the current DAG chain
setup, and it also doesn't seem to be a big problem preventing DAG
2) The OPC_CheckFoldableChainNode check requires that each of the
intermediate nodes in a multi-node pattern match only has a single use.
This check tends to fail if those intermediate nodes are strict operations
as those have a chain output that typically indeed has another use.
However, we don't really need to consider chains here at all, since they
will all be rewritten anyway by UpdateChains later. Other parts of the
matcher therefore already ignore chains, but this hasOneUse check doesn't.
This patch replaces hasOneUse by a custom test that verifies there is no
more than one use of any non-chain output value.
In theory, this change could affect code unrelated to strict FP nodes,
but at least on SystemZ I could not find any single instance of that
happening
3) The SystemZ back-end currently does not allow matching multiply-and-
extend operations (32x32 -> 64bit or 64x64 -> 128bit FP multiply) for
strict FP operations. This was not possible in the past due to the
problems described under 1) and 2) above.
With those issues fixed, it is now possible to fully support those
instructions in strict mode as well, and this patch does so.
Differential Revision: https://reviews.llvm.org/D70913
2019-12-06 18:02:11 +08:00
|
|
|
; X86-SSE-NEXT: movl %edi, 12(%esi)
|
|
|
|
; X86-SSE-NEXT: movl %edx, 8(%esi)
|
2019-11-28 09:44:43 +08:00
|
|
|
; X86-SSE-NEXT: movl %ecx, 4(%esi)
|
[FPEnv][SelectionDAG] Relax chain requirements
This patch implements the following changes:
1) SelectionDAGBuilder::visitConstrainedFPIntrinsic currently treats
each constrained intrinsic like a global barrier (e.g. a function call)
and fully serializes all pending chains. This is actually not required;
it is allowed for constrained intrinsics to be reordered w.r.t one
another or (nonvolatile) memory accesses. The MI-level scheduler already
allows for that flexibility, so it makes sense to allow it at the DAG
level as well.
This patch therefore changes the way chains for constrained intrisincs
are created, and handles them basically like load operations are handled.
This has the effect that constrained intrinsics are no longer serialized
against one another or (nonvolatile) loads. They are still serialized
against stores, but that seems hard to change with the current DAG chain
setup, and it also doesn't seem to be a big problem preventing DAG
2) The OPC_CheckFoldableChainNode check requires that each of the
intermediate nodes in a multi-node pattern match only has a single use.
This check tends to fail if those intermediate nodes are strict operations
as those have a chain output that typically indeed has another use.
However, we don't really need to consider chains here at all, since they
will all be rewritten anyway by UpdateChains later. Other parts of the
matcher therefore already ignore chains, but this hasOneUse check doesn't.
This patch replaces hasOneUse by a custom test that verifies there is no
more than one use of any non-chain output value.
In theory, this change could affect code unrelated to strict FP nodes,
but at least on SystemZ I could not find any single instance of that
happening
3) The SystemZ back-end currently does not allow matching multiply-and-
extend operations (32x32 -> 64bit or 64x64 -> 128bit FP multiply) for
strict FP operations. This was not possible in the past due to the
problems described under 1) and 2) above.
With those issues fixed, it is now possible to fully support those
instructions in strict mode as well, and this patch does so.
Differential Revision: https://reviews.llvm.org/D70913
2019-12-06 18:02:11 +08:00
|
|
|
; X86-SSE-NEXT: movl %eax, (%esi)
|
2019-11-28 09:44:43 +08:00
|
|
|
; X86-SSE-NEXT: movl %esi, %eax
|
|
|
|
; X86-SSE-NEXT: addl $36, %esp
|
|
|
|
; X86-SSE-NEXT: popl %esi
|
|
|
|
; X86-SSE-NEXT: popl %edi
|
|
|
|
; X86-SSE-NEXT: retl $4
|
|
|
|
;
|
|
|
|
; SSE-LABEL: f20s128:
|
|
|
|
; SSE: # %bb.0: # %entry
|
|
|
|
; SSE-NEXT: pushq %rax
|
|
|
|
; SSE-NEXT: callq __fixdfti
|
|
|
|
; SSE-NEXT: popq %rcx
|
|
|
|
; SSE-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX-LABEL: f20s128:
|
|
|
|
; AVX: # %bb.0: # %entry
|
|
|
|
; AVX-NEXT: pushq %rax
|
|
|
|
; AVX-NEXT: callq __fixdfti
|
|
|
|
; AVX-NEXT: popq %rcx
|
|
|
|
; AVX-NEXT: retq
|
|
|
|
entry:
|
|
|
|
%result = call i128 @llvm.experimental.constrained.fptosi.i128.f64(double %x,
|
|
|
|
metadata !"fpexcept.strict") #0
|
|
|
|
ret i128 %result
|
|
|
|
}
|
|
|
|
|
2019-11-20 08:07:50 +08:00
|
|
|
; Verify that fptoui(%x) isn't simplified when the rounding mode is
|
|
|
|
; unknown.
|
|
|
|
; Verify that no gross errors happen.
|
|
|
|
; FIXME: The SSE/AVX code does not raise an invalid exception for all values
|
|
|
|
; that don't fit in i8.
|
|
|
|
define i8 @f20u8(double %x) #0 {
|
|
|
|
; X87-LABEL: f20u8:
|
|
|
|
; X87: # %bb.0: # %entry
|
|
|
|
; X87-NEXT: subl $8, %esp
|
|
|
|
; X87-NEXT: .cfi_def_cfa_offset 12
|
|
|
|
; X87-NEXT: fldl {{[0-9]+}}(%esp)
|
|
|
|
; X87-NEXT: fnstcw {{[0-9]+}}(%esp)
|
|
|
|
; X87-NEXT: movzwl {{[0-9]+}}(%esp), %eax
|
|
|
|
; X87-NEXT: orl $3072, %eax # imm = 0xC00
|
|
|
|
; X87-NEXT: movw %ax, {{[0-9]+}}(%esp)
|
|
|
|
; X87-NEXT: fldcw {{[0-9]+}}(%esp)
|
|
|
|
; X87-NEXT: fistps {{[0-9]+}}(%esp)
|
|
|
|
; X87-NEXT: fldcw {{[0-9]+}}(%esp)
|
|
|
|
; X87-NEXT: movb {{[0-9]+}}(%esp), %al
|
|
|
|
; X87-NEXT: addl $8, %esp
|
|
|
|
; X87-NEXT: .cfi_def_cfa_offset 4
|
|
|
|
; X87-NEXT: retl
|
|
|
|
;
|
|
|
|
; X86-SSE-LABEL: f20u8:
|
|
|
|
; X86-SSE: # %bb.0: # %entry
|
|
|
|
; X86-SSE-NEXT: cvttsd2si {{[0-9]+}}(%esp), %eax
|
|
|
|
; X86-SSE-NEXT: # kill: def $al killed $al killed $eax
|
|
|
|
; X86-SSE-NEXT: retl
|
|
|
|
;
|
|
|
|
; SSE-LABEL: f20u8:
|
|
|
|
; SSE: # %bb.0: # %entry
|
|
|
|
; SSE-NEXT: cvttsd2si %xmm0, %eax
|
|
|
|
; SSE-NEXT: # kill: def $al killed $al killed $eax
|
|
|
|
; SSE-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX-LABEL: f20u8:
|
|
|
|
; AVX: # %bb.0: # %entry
|
|
|
|
; AVX-NEXT: vcvttsd2si %xmm0, %eax
|
|
|
|
; AVX-NEXT: # kill: def $al killed $al killed $eax
|
|
|
|
; AVX-NEXT: retq
|
|
|
|
entry:
|
|
|
|
%result = call i8 @llvm.experimental.constrained.fptoui.i8.f64(double %x,
|
|
|
|
metadata !"fpexcept.strict") #0
|
|
|
|
ret i8 %result
|
|
|
|
}
|
|
|
|
; Verify that fptoui(%x) isn't simplified when the rounding mode is
|
|
|
|
; unknown.
|
|
|
|
; Verify that no gross errors happen.
|
|
|
|
; FIXME: The SSE/AVX code does not raise an invalid exception for all values
|
|
|
|
; that don't fit in i16.
|
|
|
|
define i16 @f20u16(double %x) #0 {
|
|
|
|
; X87-LABEL: f20u16:
|
|
|
|
; X87: # %bb.0: # %entry
|
|
|
|
; X87-NEXT: subl $8, %esp
|
|
|
|
; X87-NEXT: .cfi_def_cfa_offset 12
|
|
|
|
; X87-NEXT: fldl {{[0-9]+}}(%esp)
|
|
|
|
; X87-NEXT: fnstcw (%esp)
|
|
|
|
; X87-NEXT: movzwl (%esp), %eax
|
|
|
|
; X87-NEXT: orl $3072, %eax # imm = 0xC00
|
|
|
|
; X87-NEXT: movw %ax, {{[0-9]+}}(%esp)
|
|
|
|
; X87-NEXT: fldcw {{[0-9]+}}(%esp)
|
|
|
|
; X87-NEXT: fistpl {{[0-9]+}}(%esp)
|
|
|
|
; X87-NEXT: fldcw (%esp)
|
|
|
|
; X87-NEXT: movl {{[0-9]+}}(%esp), %eax
|
|
|
|
; X87-NEXT: # kill: def $ax killed $ax killed $eax
|
|
|
|
; X87-NEXT: addl $8, %esp
|
|
|
|
; X87-NEXT: .cfi_def_cfa_offset 4
|
|
|
|
; X87-NEXT: retl
|
|
|
|
;
|
|
|
|
; X86-SSE-LABEL: f20u16:
|
|
|
|
; X86-SSE: # %bb.0: # %entry
|
|
|
|
; X86-SSE-NEXT: cvttsd2si {{[0-9]+}}(%esp), %eax
|
|
|
|
; X86-SSE-NEXT: # kill: def $ax killed $ax killed $eax
|
|
|
|
; X86-SSE-NEXT: retl
|
|
|
|
;
|
|
|
|
; SSE-LABEL: f20u16:
|
|
|
|
; SSE: # %bb.0: # %entry
|
|
|
|
; SSE-NEXT: cvttsd2si %xmm0, %eax
|
|
|
|
; SSE-NEXT: # kill: def $ax killed $ax killed $eax
|
|
|
|
; SSE-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX-LABEL: f20u16:
|
|
|
|
; AVX: # %bb.0: # %entry
|
|
|
|
; AVX-NEXT: vcvttsd2si %xmm0, %eax
|
|
|
|
; AVX-NEXT: # kill: def $ax killed $ax killed $eax
|
|
|
|
; AVX-NEXT: retq
|
|
|
|
entry:
|
|
|
|
%result = call i16 @llvm.experimental.constrained.fptoui.i16.f64(double %x,
|
|
|
|
metadata !"fpexcept.strict") #0
|
|
|
|
ret i16 %result
|
|
|
|
}
|
|
|
|
|
2019-11-20 07:51:19 +08:00
|
|
|
; Verify that fptoui(%x) isn't simplified when the rounding mode is
|
|
|
|
; unknown.
|
2019-08-29 00:33:36 +08:00
|
|
|
; Verify that no gross errors happen.
|
2019-11-20 07:51:19 +08:00
|
|
|
; FIXME: The X87/SSE/AVX1 code does not raise an invalid exception for all
|
|
|
|
; values that don't fit in i32. The AVX512 code does.
|
2019-10-05 01:03:46 +08:00
|
|
|
define i32 @f20u(double %x) #0 {
|
2019-11-20 07:51:19 +08:00
|
|
|
; X87-LABEL: f20u:
|
|
|
|
; X87: # %bb.0: # %entry
|
|
|
|
; X87-NEXT: subl $20, %esp
|
|
|
|
; X87-NEXT: .cfi_def_cfa_offset 24
|
|
|
|
; X87-NEXT: fldl {{[0-9]+}}(%esp)
|
|
|
|
; X87-NEXT: fnstcw {{[0-9]+}}(%esp)
|
|
|
|
; X87-NEXT: movzwl {{[0-9]+}}(%esp), %eax
|
|
|
|
; X87-NEXT: orl $3072, %eax # imm = 0xC00
|
|
|
|
; X87-NEXT: movw %ax, {{[0-9]+}}(%esp)
|
|
|
|
; X87-NEXT: fldcw {{[0-9]+}}(%esp)
|
|
|
|
; X87-NEXT: fistpll {{[0-9]+}}(%esp)
|
|
|
|
; X87-NEXT: fldcw {{[0-9]+}}(%esp)
|
|
|
|
; X87-NEXT: movl {{[0-9]+}}(%esp), %eax
|
|
|
|
; X87-NEXT: addl $20, %esp
|
|
|
|
; X87-NEXT: .cfi_def_cfa_offset 4
|
|
|
|
; X87-NEXT: retl
|
|
|
|
;
|
2019-11-18 11:58:11 +08:00
|
|
|
; X86-SSE-LABEL: f20u:
|
|
|
|
; X86-SSE: # %bb.0: # %entry
|
|
|
|
; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
|
|
|
|
; X86-SSE-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
|
|
|
|
; X86-SSE-NEXT: movapd %xmm0, %xmm2
|
|
|
|
; X86-SSE-NEXT: cmpltsd %xmm1, %xmm2
|
|
|
|
; X86-SSE-NEXT: movapd %xmm2, %xmm3
|
|
|
|
; X86-SSE-NEXT: andpd %xmm0, %xmm2
|
|
|
|
; X86-SSE-NEXT: xorl %eax, %eax
|
|
|
|
; X86-SSE-NEXT: ucomisd %xmm0, %xmm1
|
|
|
|
; X86-SSE-NEXT: subsd %xmm1, %xmm0
|
|
|
|
; X86-SSE-NEXT: andnpd %xmm0, %xmm3
|
|
|
|
; X86-SSE-NEXT: orpd %xmm3, %xmm2
|
|
|
|
; X86-SSE-NEXT: cvttsd2si %xmm2, %ecx
|
|
|
|
; X86-SSE-NEXT: setbe %al
|
|
|
|
; X86-SSE-NEXT: shll $31, %eax
|
|
|
|
; X86-SSE-NEXT: xorl %ecx, %eax
|
|
|
|
; X86-SSE-NEXT: retl
|
|
|
|
;
|
2019-11-12 07:42:25 +08:00
|
|
|
; SSE-LABEL: f20u:
|
|
|
|
; SSE: # %bb.0: # %entry
|
2019-11-20 07:51:19 +08:00
|
|
|
; SSE-NEXT: cvttsd2si %xmm0, %rax
|
|
|
|
; SSE-NEXT: # kill: def $eax killed $eax killed $rax
|
|
|
|
; SSE-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX1-LABEL: f20u:
|
|
|
|
; AVX1: # %bb.0: # %entry
|
|
|
|
; AVX1-NEXT: vcvttsd2si %xmm0, %rax
|
|
|
|
; AVX1-NEXT: # kill: def $eax killed $eax killed $rax
|
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX512-LABEL: f20u:
|
|
|
|
; AVX512: # %bb.0: # %entry
|
|
|
|
; AVX512-NEXT: vcvttsd2usi %xmm0, %eax
|
|
|
|
; AVX512-NEXT: retq
|
|
|
|
entry:
|
|
|
|
%result = call i32 @llvm.experimental.constrained.fptoui.i32.f64(double %x,
|
|
|
|
metadata !"fpexcept.strict") #0
|
|
|
|
ret i32 %result
|
|
|
|
}
|
|
|
|
|
|
|
|
; Verify that fptoui(%x) isn't simplified when the rounding mode is
|
|
|
|
; unknown.
|
|
|
|
; Verify that no gross errors happen.
|
|
|
|
; FIXME: This code generates spurious inexact exceptions.
|
|
|
|
define i64 @f20u64(double %x) #0 {
|
|
|
|
; X87-LABEL: f20u64:
|
|
|
|
; X87: # %bb.0: # %entry
|
|
|
|
; X87-NEXT: subl $20, %esp
|
|
|
|
; X87-NEXT: .cfi_def_cfa_offset 24
|
|
|
|
; X87-NEXT: fldl {{[0-9]+}}(%esp)
|
|
|
|
; X87-NEXT: flds {{\.LCPI.*}}
|
|
|
|
; X87-NEXT: fld %st(1)
|
|
|
|
; X87-NEXT: fsub %st(1), %st
|
|
|
|
; X87-NEXT: xorl %edx, %edx
|
|
|
|
; X87-NEXT: fxch %st(1)
|
|
|
|
; X87-NEXT: fucompi %st(2), %st
|
|
|
|
; X87-NEXT: fcmovnbe %st(1), %st
|
|
|
|
; X87-NEXT: fstp %st(1)
|
|
|
|
; X87-NEXT: setbe %dl
|
|
|
|
; X87-NEXT: fnstcw {{[0-9]+}}(%esp)
|
|
|
|
; X87-NEXT: movzwl {{[0-9]+}}(%esp), %eax
|
|
|
|
; X87-NEXT: orl $3072, %eax # imm = 0xC00
|
|
|
|
; X87-NEXT: movw %ax, {{[0-9]+}}(%esp)
|
|
|
|
; X87-NEXT: fldcw {{[0-9]+}}(%esp)
|
|
|
|
; X87-NEXT: fistpll {{[0-9]+}}(%esp)
|
|
|
|
; X87-NEXT: fldcw {{[0-9]+}}(%esp)
|
|
|
|
; X87-NEXT: shll $31, %edx
|
|
|
|
; X87-NEXT: xorl {{[0-9]+}}(%esp), %edx
|
|
|
|
; X87-NEXT: movl {{[0-9]+}}(%esp), %eax
|
|
|
|
; X87-NEXT: addl $20, %esp
|
|
|
|
; X87-NEXT: .cfi_def_cfa_offset 4
|
|
|
|
; X87-NEXT: retl
|
|
|
|
;
|
|
|
|
; X86-SSE-LABEL: f20u64:
|
|
|
|
; X86-SSE: # %bb.0: # %entry
|
|
|
|
; X86-SSE-NEXT: subl $20, %esp
|
|
|
|
; X86-SSE-NEXT: .cfi_def_cfa_offset 24
|
|
|
|
; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
|
|
|
|
; X86-SSE-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
|
|
|
|
; X86-SSE-NEXT: movapd %xmm0, %xmm2
|
|
|
|
; X86-SSE-NEXT: subsd %xmm1, %xmm2
|
|
|
|
; X86-SSE-NEXT: movapd %xmm0, %xmm3
|
|
|
|
; X86-SSE-NEXT: cmpltsd %xmm1, %xmm3
|
|
|
|
; X86-SSE-NEXT: movapd %xmm3, %xmm4
|
|
|
|
; X86-SSE-NEXT: andnpd %xmm2, %xmm4
|
|
|
|
; X86-SSE-NEXT: andpd %xmm0, %xmm3
|
|
|
|
; X86-SSE-NEXT: orpd %xmm4, %xmm3
|
|
|
|
; X86-SSE-NEXT: movlpd %xmm3, {{[0-9]+}}(%esp)
|
|
|
|
; X86-SSE-NEXT: fldl {{[0-9]+}}(%esp)
|
|
|
|
; X86-SSE-NEXT: fnstcw {{[0-9]+}}(%esp)
|
|
|
|
; X86-SSE-NEXT: movzwl {{[0-9]+}}(%esp), %eax
|
|
|
|
; X86-SSE-NEXT: orl $3072, %eax # imm = 0xC00
|
|
|
|
; X86-SSE-NEXT: movw %ax, {{[0-9]+}}(%esp)
|
|
|
|
; X86-SSE-NEXT: fldcw {{[0-9]+}}(%esp)
|
|
|
|
; X86-SSE-NEXT: fistpll {{[0-9]+}}(%esp)
|
|
|
|
; X86-SSE-NEXT: fldcw {{[0-9]+}}(%esp)
|
|
|
|
; X86-SSE-NEXT: xorl %edx, %edx
|
|
|
|
; X86-SSE-NEXT: ucomisd %xmm0, %xmm1
|
|
|
|
; X86-SSE-NEXT: setbe %dl
|
|
|
|
; X86-SSE-NEXT: shll $31, %edx
|
|
|
|
; X86-SSE-NEXT: xorl {{[0-9]+}}(%esp), %edx
|
|
|
|
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
|
|
|
|
; X86-SSE-NEXT: addl $20, %esp
|
|
|
|
; X86-SSE-NEXT: .cfi_def_cfa_offset 4
|
|
|
|
; X86-SSE-NEXT: retl
|
|
|
|
;
|
|
|
|
; SSE-LABEL: f20u64:
|
|
|
|
; SSE: # %bb.0: # %entry
|
2019-11-12 07:42:25 +08:00
|
|
|
; SSE-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
|
|
|
|
; SSE-NEXT: movapd %xmm0, %xmm2
|
|
|
|
; SSE-NEXT: cmpltsd %xmm1, %xmm2
|
|
|
|
; SSE-NEXT: movapd %xmm2, %xmm3
|
|
|
|
; SSE-NEXT: andpd %xmm0, %xmm2
|
|
|
|
; SSE-NEXT: xorl %eax, %eax
|
|
|
|
; SSE-NEXT: ucomisd %xmm1, %xmm0
|
|
|
|
; SSE-NEXT: subsd %xmm1, %xmm0
|
|
|
|
; SSE-NEXT: andnpd %xmm0, %xmm3
|
|
|
|
; SSE-NEXT: orpd %xmm3, %xmm2
|
2019-11-20 07:51:19 +08:00
|
|
|
; SSE-NEXT: cvttsd2si %xmm2, %rcx
|
2019-11-12 07:42:25 +08:00
|
|
|
; SSE-NEXT: setae %al
|
2019-11-20 07:51:19 +08:00
|
|
|
; SSE-NEXT: shlq $63, %rax
|
|
|
|
; SSE-NEXT: xorq %rcx, %rax
|
2019-11-12 07:42:25 +08:00
|
|
|
; SSE-NEXT: retq
|
|
|
|
;
|
2019-11-20 07:51:19 +08:00
|
|
|
; AVX1-LABEL: f20u64:
|
2019-11-12 07:42:25 +08:00
|
|
|
; AVX1: # %bb.0: # %entry
|
|
|
|
; AVX1-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero
|
|
|
|
; AVX1-NEXT: vcmpltsd %xmm1, %xmm0, %xmm2
|
|
|
|
; AVX1-NEXT: vsubsd %xmm1, %xmm0, %xmm3
|
|
|
|
; AVX1-NEXT: vblendvpd %xmm2, %xmm0, %xmm3, %xmm2
|
2019-11-20 07:51:19 +08:00
|
|
|
; AVX1-NEXT: vcvttsd2si %xmm2, %rcx
|
2019-11-12 07:42:25 +08:00
|
|
|
; AVX1-NEXT: xorl %eax, %eax
|
|
|
|
; AVX1-NEXT: vucomisd %xmm1, %xmm0
|
|
|
|
; AVX1-NEXT: setae %al
|
2019-11-20 07:51:19 +08:00
|
|
|
; AVX1-NEXT: shlq $63, %rax
|
|
|
|
; AVX1-NEXT: xorq %rcx, %rax
|
2019-11-12 07:42:25 +08:00
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
2019-11-20 07:51:19 +08:00
|
|
|
; AVX512-LABEL: f20u64:
|
2019-11-12 07:42:25 +08:00
|
|
|
; AVX512: # %bb.0: # %entry
|
2019-11-20 07:51:19 +08:00
|
|
|
; AVX512-NEXT: vcvttsd2usi %xmm0, %rax
|
2019-11-12 07:42:25 +08:00
|
|
|
; AVX512-NEXT: retq
|
2019-08-29 00:33:36 +08:00
|
|
|
entry:
|
2019-11-20 07:51:19 +08:00
|
|
|
%result = call i64 @llvm.experimental.constrained.fptoui.i64.f64(double %x,
|
2019-10-05 01:03:46 +08:00
|
|
|
metadata !"fpexcept.strict") #0
|
2019-11-20 07:51:19 +08:00
|
|
|
ret i64 %result
|
2019-08-29 00:33:36 +08:00
|
|
|
}
|
|
|
|
|
2019-11-28 09:44:43 +08:00
|
|
|
|
|
|
|
; Verify that fptoui(%x) isn't simplified when the rounding mode is
|
|
|
|
; unknown.
|
|
|
|
; Verify that no gross errors happen.
|
|
|
|
define i128 @f20u128(double %x) nounwind strictfp {
|
|
|
|
; X87-LABEL: f20u128:
|
|
|
|
; X87: # %bb.0: # %entry
|
|
|
|
; X87-NEXT: pushl %edi
|
|
|
|
; X87-NEXT: pushl %esi
|
|
|
|
; X87-NEXT: subl $36, %esp
|
|
|
|
; X87-NEXT: movl {{[0-9]+}}(%esp), %esi
|
|
|
|
; X87-NEXT: fldl {{[0-9]+}}(%esp)
|
|
|
|
; X87-NEXT: fstpl {{[0-9]+}}(%esp)
|
|
|
|
; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
|
|
|
|
; X87-NEXT: movl %eax, (%esp)
|
|
|
|
; X87-NEXT: calll __fixunsdfti
|
|
|
|
; X87-NEXT: subl $4, %esp
|
|
|
|
; X87-NEXT: movl {{[0-9]+}}(%esp), %eax
|
|
|
|
; X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
|
|
|
|
; X87-NEXT: movl {{[0-9]+}}(%esp), %edx
|
|
|
|
; X87-NEXT: movl {{[0-9]+}}(%esp), %edi
|
[FPEnv][SelectionDAG] Relax chain requirements
This patch implements the following changes:
1) SelectionDAGBuilder::visitConstrainedFPIntrinsic currently treats
each constrained intrinsic like a global barrier (e.g. a function call)
and fully serializes all pending chains. This is actually not required;
it is allowed for constrained intrinsics to be reordered w.r.t one
another or (nonvolatile) memory accesses. The MI-level scheduler already
allows for that flexibility, so it makes sense to allow it at the DAG
level as well.
This patch therefore changes the way chains for constrained intrisincs
are created, and handles them basically like load operations are handled.
This has the effect that constrained intrinsics are no longer serialized
against one another or (nonvolatile) loads. They are still serialized
against stores, but that seems hard to change with the current DAG chain
setup, and it also doesn't seem to be a big problem preventing DAG
2) The OPC_CheckFoldableChainNode check requires that each of the
intermediate nodes in a multi-node pattern match only has a single use.
This check tends to fail if those intermediate nodes are strict operations
as those have a chain output that typically indeed has another use.
However, we don't really need to consider chains here at all, since they
will all be rewritten anyway by UpdateChains later. Other parts of the
matcher therefore already ignore chains, but this hasOneUse check doesn't.
This patch replaces hasOneUse by a custom test that verifies there is no
more than one use of any non-chain output value.
In theory, this change could affect code unrelated to strict FP nodes,
but at least on SystemZ I could not find any single instance of that
happening
3) The SystemZ back-end currently does not allow matching multiply-and-
extend operations (32x32 -> 64bit or 64x64 -> 128bit FP multiply) for
strict FP operations. This was not possible in the past due to the
problems described under 1) and 2) above.
With those issues fixed, it is now possible to fully support those
instructions in strict mode as well, and this patch does so.
Differential Revision: https://reviews.llvm.org/D70913
2019-12-06 18:02:11 +08:00
|
|
|
; X87-NEXT: movl %edi, 12(%esi)
|
|
|
|
; X87-NEXT: movl %edx, 8(%esi)
|
2019-11-28 09:44:43 +08:00
|
|
|
; X87-NEXT: movl %ecx, 4(%esi)
|
[FPEnv][SelectionDAG] Relax chain requirements
This patch implements the following changes:
1) SelectionDAGBuilder::visitConstrainedFPIntrinsic currently treats
each constrained intrinsic like a global barrier (e.g. a function call)
and fully serializes all pending chains. This is actually not required;
it is allowed for constrained intrinsics to be reordered w.r.t one
another or (nonvolatile) memory accesses. The MI-level scheduler already
allows for that flexibility, so it makes sense to allow it at the DAG
level as well.
This patch therefore changes the way chains for constrained intrisincs
are created, and handles them basically like load operations are handled.
This has the effect that constrained intrinsics are no longer serialized
against one another or (nonvolatile) loads. They are still serialized
against stores, but that seems hard to change with the current DAG chain
setup, and it also doesn't seem to be a big problem preventing DAG
2) The OPC_CheckFoldableChainNode check requires that each of the
intermediate nodes in a multi-node pattern match only has a single use.
This check tends to fail if those intermediate nodes are strict operations
as those have a chain output that typically indeed has another use.
However, we don't really need to consider chains here at all, since they
will all be rewritten anyway by UpdateChains later. Other parts of the
matcher therefore already ignore chains, but this hasOneUse check doesn't.
This patch replaces hasOneUse by a custom test that verifies there is no
more than one use of any non-chain output value.
In theory, this change could affect code unrelated to strict FP nodes,
but at least on SystemZ I could not find any single instance of that
happening
3) The SystemZ back-end currently does not allow matching multiply-and-
extend operations (32x32 -> 64bit or 64x64 -> 128bit FP multiply) for
strict FP operations. This was not possible in the past due to the
problems described under 1) and 2) above.
With those issues fixed, it is now possible to fully support those
instructions in strict mode as well, and this patch does so.
Differential Revision: https://reviews.llvm.org/D70913
2019-12-06 18:02:11 +08:00
|
|
|
; X87-NEXT: movl %eax, (%esi)
|
2019-11-28 09:44:43 +08:00
|
|
|
; X87-NEXT: movl %esi, %eax
|
|
|
|
; X87-NEXT: addl $36, %esp
|
|
|
|
; X87-NEXT: popl %esi
|
|
|
|
; X87-NEXT: popl %edi
|
|
|
|
; X87-NEXT: retl $4
|
|
|
|
;
|
|
|
|
; X86-SSE-LABEL: f20u128:
|
|
|
|
; X86-SSE: # %bb.0: # %entry
|
|
|
|
; X86-SSE-NEXT: pushl %edi
|
|
|
|
; X86-SSE-NEXT: pushl %esi
|
|
|
|
; X86-SSE-NEXT: subl $36, %esp
|
|
|
|
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %esi
|
|
|
|
; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
|
|
|
|
; X86-SSE-NEXT: movsd %xmm0, {{[0-9]+}}(%esp)
|
|
|
|
; X86-SSE-NEXT: leal {{[0-9]+}}(%esp), %eax
|
|
|
|
; X86-SSE-NEXT: movl %eax, (%esp)
|
|
|
|
; X86-SSE-NEXT: calll __fixunsdfti
|
|
|
|
; X86-SSE-NEXT: subl $4, %esp
|
|
|
|
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
|
|
|
|
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %ecx
|
|
|
|
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edx
|
|
|
|
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edi
|
[FPEnv][SelectionDAG] Relax chain requirements
This patch implements the following changes:
1) SelectionDAGBuilder::visitConstrainedFPIntrinsic currently treats
each constrained intrinsic like a global barrier (e.g. a function call)
and fully serializes all pending chains. This is actually not required;
it is allowed for constrained intrinsics to be reordered w.r.t one
another or (nonvolatile) memory accesses. The MI-level scheduler already
allows for that flexibility, so it makes sense to allow it at the DAG
level as well.
This patch therefore changes the way chains for constrained intrisincs
are created, and handles them basically like load operations are handled.
This has the effect that constrained intrinsics are no longer serialized
against one another or (nonvolatile) loads. They are still serialized
against stores, but that seems hard to change with the current DAG chain
setup, and it also doesn't seem to be a big problem preventing DAG
2) The OPC_CheckFoldableChainNode check requires that each of the
intermediate nodes in a multi-node pattern match only has a single use.
This check tends to fail if those intermediate nodes are strict operations
as those have a chain output that typically indeed has another use.
However, we don't really need to consider chains here at all, since they
will all be rewritten anyway by UpdateChains later. Other parts of the
matcher therefore already ignore chains, but this hasOneUse check doesn't.
This patch replaces hasOneUse by a custom test that verifies there is no
more than one use of any non-chain output value.
In theory, this change could affect code unrelated to strict FP nodes,
but at least on SystemZ I could not find any single instance of that
happening
3) The SystemZ back-end currently does not allow matching multiply-and-
extend operations (32x32 -> 64bit or 64x64 -> 128bit FP multiply) for
strict FP operations. This was not possible in the past due to the
problems described under 1) and 2) above.
With those issues fixed, it is now possible to fully support those
instructions in strict mode as well, and this patch does so.
Differential Revision: https://reviews.llvm.org/D70913
2019-12-06 18:02:11 +08:00
|
|
|
; X86-SSE-NEXT: movl %edi, 12(%esi)
|
|
|
|
; X86-SSE-NEXT: movl %edx, 8(%esi)
|
2019-11-28 09:44:43 +08:00
|
|
|
; X86-SSE-NEXT: movl %ecx, 4(%esi)
|
[FPEnv][SelectionDAG] Relax chain requirements
This patch implements the following changes:
1) SelectionDAGBuilder::visitConstrainedFPIntrinsic currently treats
each constrained intrinsic like a global barrier (e.g. a function call)
and fully serializes all pending chains. This is actually not required;
it is allowed for constrained intrinsics to be reordered w.r.t one
another or (nonvolatile) memory accesses. The MI-level scheduler already
allows for that flexibility, so it makes sense to allow it at the DAG
level as well.
This patch therefore changes the way chains for constrained intrisincs
are created, and handles them basically like load operations are handled.
This has the effect that constrained intrinsics are no longer serialized
against one another or (nonvolatile) loads. They are still serialized
against stores, but that seems hard to change with the current DAG chain
setup, and it also doesn't seem to be a big problem preventing DAG
2) The OPC_CheckFoldableChainNode check requires that each of the
intermediate nodes in a multi-node pattern match only has a single use.
This check tends to fail if those intermediate nodes are strict operations
as those have a chain output that typically indeed has another use.
However, we don't really need to consider chains here at all, since they
will all be rewritten anyway by UpdateChains later. Other parts of the
matcher therefore already ignore chains, but this hasOneUse check doesn't.
This patch replaces hasOneUse by a custom test that verifies there is no
more than one use of any non-chain output value.
In theory, this change could affect code unrelated to strict FP nodes,
but at least on SystemZ I could not find any single instance of that
happening
3) The SystemZ back-end currently does not allow matching multiply-and-
extend operations (32x32 -> 64bit or 64x64 -> 128bit FP multiply) for
strict FP operations. This was not possible in the past due to the
problems described under 1) and 2) above.
With those issues fixed, it is now possible to fully support those
instructions in strict mode as well, and this patch does so.
Differential Revision: https://reviews.llvm.org/D70913
2019-12-06 18:02:11 +08:00
|
|
|
; X86-SSE-NEXT: movl %eax, (%esi)
|
2019-11-28 09:44:43 +08:00
|
|
|
; X86-SSE-NEXT: movl %esi, %eax
|
|
|
|
; X86-SSE-NEXT: addl $36, %esp
|
|
|
|
; X86-SSE-NEXT: popl %esi
|
|
|
|
; X86-SSE-NEXT: popl %edi
|
|
|
|
; X86-SSE-NEXT: retl $4
|
|
|
|
;
|
|
|
|
; SSE-LABEL: f20u128:
|
|
|
|
; SSE: # %bb.0: # %entry
|
|
|
|
; SSE-NEXT: pushq %rax
|
|
|
|
; SSE-NEXT: callq __fixunsdfti
|
|
|
|
; SSE-NEXT: popq %rcx
|
|
|
|
; SSE-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX-LABEL: f20u128:
|
|
|
|
; AVX: # %bb.0: # %entry
|
|
|
|
; AVX-NEXT: pushq %rax
|
|
|
|
; AVX-NEXT: callq __fixunsdfti
|
|
|
|
; AVX-NEXT: popq %rcx
|
|
|
|
; AVX-NEXT: retq
|
|
|
|
entry:
|
|
|
|
%result = call i128 @llvm.experimental.constrained.fptoui.i128.f64(double %x,
|
|
|
|
metadata !"fpexcept.strict") #0
|
|
|
|
ret i128 %result
|
|
|
|
}
|
|
|
|
|
2019-05-13 21:23:30 +08:00
|
|
|
; Verify that round(42.1) isn't simplified when the rounding mode is
|
|
|
|
; unknown.
|
|
|
|
; Verify that no gross errors happen.
|
2019-10-05 01:03:46 +08:00
|
|
|
define float @f21() #0 {
|
2019-11-20 07:51:19 +08:00
|
|
|
; X87-LABEL: f21:
|
|
|
|
; X87: # %bb.0: # %entry
|
|
|
|
; X87-NEXT: pushl %eax
|
|
|
|
; X87-NEXT: .cfi_def_cfa_offset 8
|
|
|
|
; X87-NEXT: fldl {{\.LCPI.*}}
|
|
|
|
; X87-NEXT: fstps (%esp)
|
|
|
|
; X87-NEXT: flds (%esp)
|
|
|
|
; X87-NEXT: popl %eax
|
|
|
|
; X87-NEXT: .cfi_def_cfa_offset 4
|
|
|
|
; X87-NEXT: retl
|
|
|
|
;
|
2019-11-18 11:58:11 +08:00
|
|
|
; X86-SSE-LABEL: f21:
|
|
|
|
; X86-SSE: # %bb.0: # %entry
|
|
|
|
; X86-SSE-NEXT: pushl %eax
|
|
|
|
; X86-SSE-NEXT: .cfi_def_cfa_offset 8
|
|
|
|
; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
|
|
|
|
; X86-SSE-NEXT: cvtsd2ss %xmm0, %xmm0
|
|
|
|
; X86-SSE-NEXT: movss %xmm0, (%esp)
|
|
|
|
; X86-SSE-NEXT: flds (%esp)
|
|
|
|
; X86-SSE-NEXT: popl %eax
|
|
|
|
; X86-SSE-NEXT: .cfi_def_cfa_offset 4
|
|
|
|
; X86-SSE-NEXT: retl
|
|
|
|
;
|
2019-11-12 07:42:25 +08:00
|
|
|
; SSE-LABEL: f21:
|
|
|
|
; SSE: # %bb.0: # %entry
|
|
|
|
; SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
|
|
|
|
; SSE-NEXT: cvtsd2ss %xmm0, %xmm0
|
|
|
|
; SSE-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX-LABEL: f21:
|
|
|
|
; AVX: # %bb.0: # %entry
|
|
|
|
; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
|
|
|
|
; AVX-NEXT: vcvtsd2ss %xmm0, %xmm0, %xmm0
|
|
|
|
; AVX-NEXT: retq
|
2019-05-13 21:23:30 +08:00
|
|
|
entry:
|
|
|
|
%result = call float @llvm.experimental.constrained.fptrunc.f32.f64(
|
|
|
|
double 42.1,
|
|
|
|
metadata !"round.dynamic",
|
2019-10-05 01:03:46 +08:00
|
|
|
metadata !"fpexcept.strict") #0
|
2019-05-13 21:23:30 +08:00
|
|
|
ret float %result
|
|
|
|
}
|
|
|
|
|
2019-10-05 01:03:46 +08:00
|
|
|
define double @f22(float %x) #0 {
|
2019-11-20 07:51:19 +08:00
|
|
|
; X87-LABEL: f22:
|
|
|
|
; X87: # %bb.0: # %entry
|
|
|
|
; X87-NEXT: flds {{[0-9]+}}(%esp)
|
|
|
|
; X87-NEXT: retl
|
|
|
|
;
|
2019-11-18 11:58:11 +08:00
|
|
|
; X86-SSE-LABEL: f22:
|
|
|
|
; X86-SSE: # %bb.0: # %entry
|
|
|
|
; X86-SSE-NEXT: subl $12, %esp
|
|
|
|
; X86-SSE-NEXT: .cfi_def_cfa_offset 16
|
|
|
|
; X86-SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
|
|
|
|
; X86-SSE-NEXT: cvtss2sd %xmm0, %xmm0
|
|
|
|
; X86-SSE-NEXT: movsd %xmm0, (%esp)
|
|
|
|
; X86-SSE-NEXT: fldl (%esp)
|
|
|
|
; X86-SSE-NEXT: addl $12, %esp
|
|
|
|
; X86-SSE-NEXT: .cfi_def_cfa_offset 4
|
|
|
|
; X86-SSE-NEXT: retl
|
|
|
|
;
|
2019-11-12 07:42:25 +08:00
|
|
|
; SSE-LABEL: f22:
|
|
|
|
; SSE: # %bb.0: # %entry
|
|
|
|
; SSE-NEXT: cvtss2sd %xmm0, %xmm0
|
|
|
|
; SSE-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX-LABEL: f22:
|
|
|
|
; AVX: # %bb.0: # %entry
|
|
|
|
; AVX-NEXT: vcvtss2sd %xmm0, %xmm0, %xmm0
|
|
|
|
; AVX-NEXT: retq
|
2019-05-13 21:23:30 +08:00
|
|
|
entry:
|
|
|
|
%result = call double @llvm.experimental.constrained.fpext.f64.f32(float %x,
|
2019-10-05 01:03:46 +08:00
|
|
|
metadata !"fpexcept.strict") #0
|
2019-05-13 21:23:30 +08:00
|
|
|
ret double %result
|
|
|
|
}
|
|
|
|
|
2019-10-07 21:20:00 +08:00
|
|
|
define i32 @f23(double %x) #0 {
|
2019-11-20 07:51:19 +08:00
|
|
|
; X87-LABEL: f23:
|
|
|
|
; X87: # %bb.0: # %entry
|
|
|
|
; X87-NEXT: subl $12, %esp
|
|
|
|
; X87-NEXT: .cfi_def_cfa_offset 16
|
|
|
|
; X87-NEXT: fldl {{[0-9]+}}(%esp)
|
|
|
|
; X87-NEXT: fstpl (%esp)
|
|
|
|
; X87-NEXT: calll lrint
|
|
|
|
; X87-NEXT: addl $12, %esp
|
|
|
|
; X87-NEXT: .cfi_def_cfa_offset 4
|
|
|
|
; X87-NEXT: retl
|
|
|
|
;
|
2019-11-19 03:14:13 +08:00
|
|
|
; X86-SSE-LABEL: f23:
|
|
|
|
; X86-SSE: # %bb.0: # %entry
|
|
|
|
; X86-SSE-NEXT: subl $12, %esp
|
|
|
|
; X86-SSE-NEXT: .cfi_def_cfa_offset 16
|
|
|
|
; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
|
|
|
|
; X86-SSE-NEXT: movsd %xmm0, (%esp)
|
|
|
|
; X86-SSE-NEXT: calll lrint
|
|
|
|
; X86-SSE-NEXT: addl $12, %esp
|
|
|
|
; X86-SSE-NEXT: .cfi_def_cfa_offset 4
|
|
|
|
; X86-SSE-NEXT: retl
|
|
|
|
;
|
|
|
|
; SSE-LABEL: f23:
|
|
|
|
; SSE: # %bb.0: # %entry
|
|
|
|
; SSE-NEXT: pushq %rax
|
|
|
|
; SSE-NEXT: .cfi_def_cfa_offset 16
|
|
|
|
; SSE-NEXT: callq lrint
|
|
|
|
; SSE-NEXT: popq %rcx
|
|
|
|
; SSE-NEXT: .cfi_def_cfa_offset 8
|
|
|
|
; SSE-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX-LABEL: f23:
|
|
|
|
; AVX: # %bb.0: # %entry
|
|
|
|
; AVX-NEXT: pushq %rax
|
|
|
|
; AVX-NEXT: .cfi_def_cfa_offset 16
|
|
|
|
; AVX-NEXT: callq lrint
|
|
|
|
; AVX-NEXT: popq %rcx
|
|
|
|
; AVX-NEXT: .cfi_def_cfa_offset 8
|
|
|
|
; AVX-NEXT: retq
|
2019-10-07 21:20:00 +08:00
|
|
|
entry:
|
|
|
|
%result = call i32 @llvm.experimental.constrained.lrint.i32.f64(double %x,
|
|
|
|
metadata !"round.dynamic",
|
|
|
|
metadata !"fpexcept.strict") #0
|
|
|
|
ret i32 %result
|
|
|
|
}
|
|
|
|
|
|
|
|
define i32 @f24(float %x) #0 {
|
2019-11-20 07:51:19 +08:00
|
|
|
; X87-LABEL: f24:
|
|
|
|
; X87: # %bb.0: # %entry
|
|
|
|
; X87-NEXT: subl $12, %esp
|
|
|
|
; X87-NEXT: .cfi_def_cfa_offset 16
|
|
|
|
; X87-NEXT: flds {{[0-9]+}}(%esp)
|
|
|
|
; X87-NEXT: fstps (%esp)
|
|
|
|
; X87-NEXT: calll lrintf
|
|
|
|
; X87-NEXT: addl $12, %esp
|
|
|
|
; X87-NEXT: .cfi_def_cfa_offset 4
|
|
|
|
; X87-NEXT: retl
|
|
|
|
;
|
2019-11-19 03:14:13 +08:00
|
|
|
; X86-SSE-LABEL: f24:
|
|
|
|
; X86-SSE: # %bb.0: # %entry
|
|
|
|
; X86-SSE-NEXT: subl $12, %esp
|
|
|
|
; X86-SSE-NEXT: .cfi_def_cfa_offset 16
|
|
|
|
; X86-SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
|
|
|
|
; X86-SSE-NEXT: movss %xmm0, (%esp)
|
|
|
|
; X86-SSE-NEXT: calll lrintf
|
|
|
|
; X86-SSE-NEXT: addl $12, %esp
|
|
|
|
; X86-SSE-NEXT: .cfi_def_cfa_offset 4
|
|
|
|
; X86-SSE-NEXT: retl
|
|
|
|
;
|
|
|
|
; SSE-LABEL: f24:
|
|
|
|
; SSE: # %bb.0: # %entry
|
|
|
|
; SSE-NEXT: pushq %rax
|
|
|
|
; SSE-NEXT: .cfi_def_cfa_offset 16
|
|
|
|
; SSE-NEXT: callq lrintf
|
|
|
|
; SSE-NEXT: popq %rcx
|
|
|
|
; SSE-NEXT: .cfi_def_cfa_offset 8
|
|
|
|
; SSE-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX-LABEL: f24:
|
|
|
|
; AVX: # %bb.0: # %entry
|
|
|
|
; AVX-NEXT: pushq %rax
|
|
|
|
; AVX-NEXT: .cfi_def_cfa_offset 16
|
|
|
|
; AVX-NEXT: callq lrintf
|
|
|
|
; AVX-NEXT: popq %rcx
|
|
|
|
; AVX-NEXT: .cfi_def_cfa_offset 8
|
|
|
|
; AVX-NEXT: retq
|
2019-10-07 21:20:00 +08:00
|
|
|
entry:
|
|
|
|
%result = call i32 @llvm.experimental.constrained.lrint.i32.f32(float %x,
|
|
|
|
metadata !"round.dynamic",
|
|
|
|
metadata !"fpexcept.strict") #0
|
|
|
|
ret i32 %result
|
|
|
|
}
|
|
|
|
|
|
|
|
define i64 @f25(double %x) #0 {
|
2019-11-20 07:51:19 +08:00
|
|
|
; X87-LABEL: f25:
|
|
|
|
; X87: # %bb.0: # %entry
|
|
|
|
; X87-NEXT: subl $12, %esp
|
|
|
|
; X87-NEXT: .cfi_def_cfa_offset 16
|
|
|
|
; X87-NEXT: fldl {{[0-9]+}}(%esp)
|
|
|
|
; X87-NEXT: fstpl (%esp)
|
|
|
|
; X87-NEXT: calll llrint
|
|
|
|
; X87-NEXT: addl $12, %esp
|
|
|
|
; X87-NEXT: .cfi_def_cfa_offset 4
|
|
|
|
; X87-NEXT: retl
|
|
|
|
;
|
2019-11-18 11:58:11 +08:00
|
|
|
; X86-SSE-LABEL: f25:
|
|
|
|
; X86-SSE: # %bb.0: # %entry
|
|
|
|
; X86-SSE-NEXT: subl $12, %esp
|
|
|
|
; X86-SSE-NEXT: .cfi_def_cfa_offset 16
|
|
|
|
; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
|
|
|
|
; X86-SSE-NEXT: movsd %xmm0, (%esp)
|
|
|
|
; X86-SSE-NEXT: calll llrint
|
|
|
|
; X86-SSE-NEXT: addl $12, %esp
|
|
|
|
; X86-SSE-NEXT: .cfi_def_cfa_offset 4
|
|
|
|
; X86-SSE-NEXT: retl
|
|
|
|
;
|
|
|
|
; SSE-LABEL: f25:
|
|
|
|
; SSE: # %bb.0: # %entry
|
2019-11-19 03:14:13 +08:00
|
|
|
; SSE-NEXT: pushq %rax
|
|
|
|
; SSE-NEXT: .cfi_def_cfa_offset 16
|
|
|
|
; SSE-NEXT: callq llrint
|
|
|
|
; SSE-NEXT: popq %rcx
|
|
|
|
; SSE-NEXT: .cfi_def_cfa_offset 8
|
|
|
|
; SSE-NEXT: retq
|
2019-11-18 11:58:11 +08:00
|
|
|
;
|
|
|
|
; AVX-LABEL: f25:
|
|
|
|
; AVX: # %bb.0: # %entry
|
2019-11-19 03:14:13 +08:00
|
|
|
; AVX-NEXT: pushq %rax
|
|
|
|
; AVX-NEXT: .cfi_def_cfa_offset 16
|
|
|
|
; AVX-NEXT: callq llrint
|
|
|
|
; AVX-NEXT: popq %rcx
|
|
|
|
; AVX-NEXT: .cfi_def_cfa_offset 8
|
|
|
|
; AVX-NEXT: retq
|
2019-10-07 21:20:00 +08:00
|
|
|
entry:
|
|
|
|
%result = call i64 @llvm.experimental.constrained.llrint.i64.f64(double %x,
|
|
|
|
metadata !"round.dynamic",
|
|
|
|
metadata !"fpexcept.strict") #0
|
|
|
|
ret i64 %result
|
|
|
|
}
|
|
|
|
|
|
|
|
define i64 @f26(float %x) {
|
2019-11-20 07:51:19 +08:00
|
|
|
; X87-LABEL: f26:
|
|
|
|
; X87: # %bb.0: # %entry
|
|
|
|
; X87-NEXT: subl $12, %esp
|
|
|
|
; X87-NEXT: .cfi_def_cfa_offset 16
|
|
|
|
; X87-NEXT: flds {{[0-9]+}}(%esp)
|
|
|
|
; X87-NEXT: fstps (%esp)
|
|
|
|
; X87-NEXT: calll llrintf
|
|
|
|
; X87-NEXT: addl $12, %esp
|
|
|
|
; X87-NEXT: .cfi_def_cfa_offset 4
|
|
|
|
; X87-NEXT: retl
|
|
|
|
;
|
2019-11-18 11:58:11 +08:00
|
|
|
; X86-SSE-LABEL: f26:
|
|
|
|
; X86-SSE: # %bb.0: # %entry
|
|
|
|
; X86-SSE-NEXT: subl $12, %esp
|
|
|
|
; X86-SSE-NEXT: .cfi_def_cfa_offset 16
|
|
|
|
; X86-SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
|
|
|
|
; X86-SSE-NEXT: movss %xmm0, (%esp)
|
|
|
|
; X86-SSE-NEXT: calll llrintf
|
|
|
|
; X86-SSE-NEXT: addl $12, %esp
|
|
|
|
; X86-SSE-NEXT: .cfi_def_cfa_offset 4
|
|
|
|
; X86-SSE-NEXT: retl
|
|
|
|
;
|
|
|
|
; SSE-LABEL: f26:
|
|
|
|
; SSE: # %bb.0: # %entry
|
2019-11-19 03:14:13 +08:00
|
|
|
; SSE-NEXT: pushq %rax
|
|
|
|
; SSE-NEXT: .cfi_def_cfa_offset 16
|
|
|
|
; SSE-NEXT: callq llrintf
|
|
|
|
; SSE-NEXT: popq %rcx
|
|
|
|
; SSE-NEXT: .cfi_def_cfa_offset 8
|
|
|
|
; SSE-NEXT: retq
|
2019-11-18 11:58:11 +08:00
|
|
|
;
|
|
|
|
; AVX-LABEL: f26:
|
|
|
|
; AVX: # %bb.0: # %entry
|
2019-11-19 03:14:13 +08:00
|
|
|
; AVX-NEXT: pushq %rax
|
|
|
|
; AVX-NEXT: .cfi_def_cfa_offset 16
|
|
|
|
; AVX-NEXT: callq llrintf
|
|
|
|
; AVX-NEXT: popq %rcx
|
|
|
|
; AVX-NEXT: .cfi_def_cfa_offset 8
|
|
|
|
; AVX-NEXT: retq
|
2019-10-07 21:20:00 +08:00
|
|
|
entry:
|
|
|
|
%result = call i64 @llvm.experimental.constrained.llrint.i64.f32(float %x,
|
|
|
|
metadata !"round.dynamic",
|
|
|
|
metadata !"fpexcept.strict") #0
|
|
|
|
ret i64 %result
|
|
|
|
}
|
|
|
|
|
|
|
|
define i32 @f27(double %x) #0 {
|
2019-11-20 07:51:19 +08:00
|
|
|
; X87-LABEL: f27:
|
|
|
|
; X87: # %bb.0: # %entry
|
|
|
|
; X87-NEXT: subl $12, %esp
|
|
|
|
; X87-NEXT: .cfi_def_cfa_offset 16
|
|
|
|
; X87-NEXT: fldl {{[0-9]+}}(%esp)
|
|
|
|
; X87-NEXT: fstpl (%esp)
|
|
|
|
; X87-NEXT: calll lround
|
|
|
|
; X87-NEXT: addl $12, %esp
|
|
|
|
; X87-NEXT: .cfi_def_cfa_offset 4
|
|
|
|
; X87-NEXT: retl
|
|
|
|
;
|
2019-11-19 03:14:13 +08:00
|
|
|
; X86-SSE-LABEL: f27:
|
|
|
|
; X86-SSE: # %bb.0: # %entry
|
|
|
|
; X86-SSE-NEXT: subl $12, %esp
|
|
|
|
; X86-SSE-NEXT: .cfi_def_cfa_offset 16
|
|
|
|
; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
|
|
|
|
; X86-SSE-NEXT: movsd %xmm0, (%esp)
|
|
|
|
; X86-SSE-NEXT: calll lround
|
|
|
|
; X86-SSE-NEXT: addl $12, %esp
|
|
|
|
; X86-SSE-NEXT: .cfi_def_cfa_offset 4
|
|
|
|
; X86-SSE-NEXT: retl
|
|
|
|
;
|
|
|
|
; SSE-LABEL: f27:
|
|
|
|
; SSE: # %bb.0: # %entry
|
|
|
|
; SSE-NEXT: pushq %rax
|
|
|
|
; SSE-NEXT: .cfi_def_cfa_offset 16
|
|
|
|
; SSE-NEXT: callq lround
|
|
|
|
; SSE-NEXT: popq %rcx
|
|
|
|
; SSE-NEXT: .cfi_def_cfa_offset 8
|
|
|
|
; SSE-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX-LABEL: f27:
|
|
|
|
; AVX: # %bb.0: # %entry
|
|
|
|
; AVX-NEXT: pushq %rax
|
|
|
|
; AVX-NEXT: .cfi_def_cfa_offset 16
|
|
|
|
; AVX-NEXT: callq lround
|
|
|
|
; AVX-NEXT: popq %rcx
|
|
|
|
; AVX-NEXT: .cfi_def_cfa_offset 8
|
|
|
|
; AVX-NEXT: retq
|
2019-10-07 21:20:00 +08:00
|
|
|
entry:
|
|
|
|
%result = call i32 @llvm.experimental.constrained.lround.i32.f64(double %x,
|
|
|
|
metadata !"fpexcept.strict") #0
|
|
|
|
ret i32 %result
|
|
|
|
}
|
|
|
|
|
|
|
|
define i32 @f28(float %x) #0 {
|
2019-11-20 07:51:19 +08:00
|
|
|
; X87-LABEL: f28:
|
|
|
|
; X87: # %bb.0: # %entry
|
|
|
|
; X87-NEXT: subl $12, %esp
|
|
|
|
; X87-NEXT: .cfi_def_cfa_offset 16
|
|
|
|
; X87-NEXT: flds {{[0-9]+}}(%esp)
|
|
|
|
; X87-NEXT: fstps (%esp)
|
|
|
|
; X87-NEXT: calll lroundf
|
|
|
|
; X87-NEXT: addl $12, %esp
|
|
|
|
; X87-NEXT: .cfi_def_cfa_offset 4
|
|
|
|
; X87-NEXT: retl
|
|
|
|
;
|
2019-11-19 03:14:13 +08:00
|
|
|
; X86-SSE-LABEL: f28:
|
|
|
|
; X86-SSE: # %bb.0: # %entry
|
|
|
|
; X86-SSE-NEXT: subl $12, %esp
|
|
|
|
; X86-SSE-NEXT: .cfi_def_cfa_offset 16
|
|
|
|
; X86-SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
|
|
|
|
; X86-SSE-NEXT: movss %xmm0, (%esp)
|
|
|
|
; X86-SSE-NEXT: calll lroundf
|
|
|
|
; X86-SSE-NEXT: addl $12, %esp
|
|
|
|
; X86-SSE-NEXT: .cfi_def_cfa_offset 4
|
|
|
|
; X86-SSE-NEXT: retl
|
|
|
|
;
|
|
|
|
; SSE-LABEL: f28:
|
|
|
|
; SSE: # %bb.0: # %entry
|
|
|
|
; SSE-NEXT: pushq %rax
|
|
|
|
; SSE-NEXT: .cfi_def_cfa_offset 16
|
|
|
|
; SSE-NEXT: callq lroundf
|
|
|
|
; SSE-NEXT: popq %rcx
|
|
|
|
; SSE-NEXT: .cfi_def_cfa_offset 8
|
|
|
|
; SSE-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX-LABEL: f28:
|
|
|
|
; AVX: # %bb.0: # %entry
|
|
|
|
; AVX-NEXT: pushq %rax
|
|
|
|
; AVX-NEXT: .cfi_def_cfa_offset 16
|
|
|
|
; AVX-NEXT: callq lroundf
|
|
|
|
; AVX-NEXT: popq %rcx
|
|
|
|
; AVX-NEXT: .cfi_def_cfa_offset 8
|
|
|
|
; AVX-NEXT: retq
|
2019-10-07 21:20:00 +08:00
|
|
|
entry:
|
|
|
|
%result = call i32 @llvm.experimental.constrained.lround.i32.f32(float %x,
|
|
|
|
metadata !"fpexcept.strict") #0
|
|
|
|
ret i32 %result
|
|
|
|
}
|
|
|
|
|
|
|
|
define i64 @f29(double %x) #0 {
|
2019-11-20 07:51:19 +08:00
|
|
|
; X87-LABEL: f29:
|
|
|
|
; X87: # %bb.0: # %entry
|
|
|
|
; X87-NEXT: subl $12, %esp
|
|
|
|
; X87-NEXT: .cfi_def_cfa_offset 16
|
|
|
|
; X87-NEXT: fldl {{[0-9]+}}(%esp)
|
|
|
|
; X87-NEXT: fstpl (%esp)
|
|
|
|
; X87-NEXT: calll llround
|
|
|
|
; X87-NEXT: addl $12, %esp
|
|
|
|
; X87-NEXT: .cfi_def_cfa_offset 4
|
|
|
|
; X87-NEXT: retl
|
|
|
|
;
|
2019-11-18 11:58:11 +08:00
|
|
|
; X86-SSE-LABEL: f29:
|
|
|
|
; X86-SSE: # %bb.0: # %entry
|
|
|
|
; X86-SSE-NEXT: subl $12, %esp
|
|
|
|
; X86-SSE-NEXT: .cfi_def_cfa_offset 16
|
|
|
|
; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
|
|
|
|
; X86-SSE-NEXT: movsd %xmm0, (%esp)
|
|
|
|
; X86-SSE-NEXT: calll llround
|
|
|
|
; X86-SSE-NEXT: addl $12, %esp
|
|
|
|
; X86-SSE-NEXT: .cfi_def_cfa_offset 4
|
|
|
|
; X86-SSE-NEXT: retl
|
|
|
|
;
|
|
|
|
; SSE-LABEL: f29:
|
|
|
|
; SSE: # %bb.0: # %entry
|
2019-11-19 03:14:13 +08:00
|
|
|
; SSE-NEXT: pushq %rax
|
|
|
|
; SSE-NEXT: .cfi_def_cfa_offset 16
|
|
|
|
; SSE-NEXT: callq llround
|
|
|
|
; SSE-NEXT: popq %rcx
|
|
|
|
; SSE-NEXT: .cfi_def_cfa_offset 8
|
|
|
|
; SSE-NEXT: retq
|
2019-11-18 11:58:11 +08:00
|
|
|
;
|
|
|
|
; AVX-LABEL: f29:
|
|
|
|
; AVX: # %bb.0: # %entry
|
2019-11-19 03:14:13 +08:00
|
|
|
; AVX-NEXT: pushq %rax
|
|
|
|
; AVX-NEXT: .cfi_def_cfa_offset 16
|
|
|
|
; AVX-NEXT: callq llround
|
|
|
|
; AVX-NEXT: popq %rcx
|
|
|
|
; AVX-NEXT: .cfi_def_cfa_offset 8
|
|
|
|
; AVX-NEXT: retq
|
2019-10-07 21:20:00 +08:00
|
|
|
entry:
|
|
|
|
%result = call i64 @llvm.experimental.constrained.llround.i64.f64(double %x,
|
|
|
|
metadata !"fpexcept.strict") #0
|
|
|
|
ret i64 %result
|
|
|
|
}
|
|
|
|
|
|
|
|
define i64 @f30(float %x) #0 {
|
2019-11-20 07:51:19 +08:00
|
|
|
; X87-LABEL: f30:
|
|
|
|
; X87: # %bb.0: # %entry
|
|
|
|
; X87-NEXT: subl $12, %esp
|
|
|
|
; X87-NEXT: .cfi_def_cfa_offset 16
|
|
|
|
; X87-NEXT: flds {{[0-9]+}}(%esp)
|
|
|
|
; X87-NEXT: fstps (%esp)
|
|
|
|
; X87-NEXT: calll llroundf
|
|
|
|
; X87-NEXT: addl $12, %esp
|
|
|
|
; X87-NEXT: .cfi_def_cfa_offset 4
|
|
|
|
; X87-NEXT: retl
|
|
|
|
;
|
2019-11-18 11:58:11 +08:00
|
|
|
; X86-SSE-LABEL: f30:
|
|
|
|
; X86-SSE: # %bb.0: # %entry
|
|
|
|
; X86-SSE-NEXT: subl $12, %esp
|
|
|
|
; X86-SSE-NEXT: .cfi_def_cfa_offset 16
|
|
|
|
; X86-SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
|
|
|
|
; X86-SSE-NEXT: movss %xmm0, (%esp)
|
|
|
|
; X86-SSE-NEXT: calll llroundf
|
|
|
|
; X86-SSE-NEXT: addl $12, %esp
|
|
|
|
; X86-SSE-NEXT: .cfi_def_cfa_offset 4
|
|
|
|
; X86-SSE-NEXT: retl
|
|
|
|
;
|
|
|
|
; SSE-LABEL: f30:
|
|
|
|
; SSE: # %bb.0: # %entry
|
2019-11-19 03:14:13 +08:00
|
|
|
; SSE-NEXT: pushq %rax
|
|
|
|
; SSE-NEXT: .cfi_def_cfa_offset 16
|
|
|
|
; SSE-NEXT: callq llroundf
|
|
|
|
; SSE-NEXT: popq %rcx
|
|
|
|
; SSE-NEXT: .cfi_def_cfa_offset 8
|
|
|
|
; SSE-NEXT: retq
|
2019-11-18 11:58:11 +08:00
|
|
|
;
|
|
|
|
; AVX-LABEL: f30:
|
|
|
|
; AVX: # %bb.0: # %entry
|
2019-11-19 03:14:13 +08:00
|
|
|
; AVX-NEXT: pushq %rax
|
|
|
|
; AVX-NEXT: .cfi_def_cfa_offset 16
|
|
|
|
; AVX-NEXT: callq llroundf
|
|
|
|
; AVX-NEXT: popq %rcx
|
|
|
|
; AVX-NEXT: .cfi_def_cfa_offset 8
|
|
|
|
; AVX-NEXT: retq
|
2019-10-07 21:20:00 +08:00
|
|
|
entry:
|
|
|
|
%result = call i64 @llvm.experimental.constrained.llround.i64.f32(float %x,
|
|
|
|
metadata !"fpexcept.strict") #0
|
|
|
|
ret i64 %result
|
|
|
|
}
|
|
|
|
|
2019-10-05 01:03:46 +08:00
|
|
|
attributes #0 = { strictfp }
|
|
|
|
|
2017-01-27 07:27:59 +08:00
|
|
|
@llvm.fp.env = thread_local global i8 zeroinitializer, section "llvm.metadata"
|
|
|
|
declare double @llvm.experimental.constrained.fadd.f64(double, double, metadata, metadata)
|
|
|
|
declare double @llvm.experimental.constrained.fsub.f64(double, double, metadata, metadata)
|
2018-08-21 03:28:56 +08:00
|
|
|
declare double @llvm.experimental.constrained.fmul.f64(double, double, metadata, metadata)
|
|
|
|
declare double @llvm.experimental.constrained.fdiv.f64(double, double, metadata, metadata)
|
|
|
|
declare double @llvm.experimental.constrained.frem.f64(double, double, metadata, metadata)
|
2017-05-26 05:31:00 +08:00
|
|
|
declare double @llvm.experimental.constrained.sqrt.f64(double, metadata, metadata)
|
|
|
|
declare double @llvm.experimental.constrained.pow.f64(double, double, metadata, metadata)
|
|
|
|
declare double @llvm.experimental.constrained.powi.f64(double, i32, metadata, metadata)
|
|
|
|
declare double @llvm.experimental.constrained.sin.f64(double, metadata, metadata)
|
|
|
|
declare double @llvm.experimental.constrained.cos.f64(double, metadata, metadata)
|
|
|
|
declare double @llvm.experimental.constrained.exp.f64(double, metadata, metadata)
|
|
|
|
declare double @llvm.experimental.constrained.exp2.f64(double, metadata, metadata)
|
|
|
|
declare double @llvm.experimental.constrained.log.f64(double, metadata, metadata)
|
|
|
|
declare double @llvm.experimental.constrained.log10.f64(double, metadata, metadata)
|
|
|
|
declare double @llvm.experimental.constrained.log2.f64(double, metadata, metadata)
|
|
|
|
declare double @llvm.experimental.constrained.rint.f64(double, metadata, metadata)
|
|
|
|
declare double @llvm.experimental.constrained.nearbyint.f64(double, metadata, metadata)
|
2019-11-20 08:07:50 +08:00
|
|
|
declare i8 @llvm.experimental.constrained.fptosi.i8.f64(double, metadata)
|
2019-11-20 07:51:19 +08:00
|
|
|
declare i16 @llvm.experimental.constrained.fptosi.i16.f64(double, metadata)
|
2019-08-29 00:33:36 +08:00
|
|
|
declare i32 @llvm.experimental.constrained.fptosi.i32.f64(double, metadata)
|
2019-11-20 07:51:19 +08:00
|
|
|
declare i64 @llvm.experimental.constrained.fptosi.i64.f64(double, metadata)
|
2019-11-28 09:44:43 +08:00
|
|
|
declare i128 @llvm.experimental.constrained.fptosi.i128.f64(double, metadata)
|
2019-11-20 08:07:50 +08:00
|
|
|
declare i8 @llvm.experimental.constrained.fptoui.i8.f64(double, metadata)
|
|
|
|
declare i16 @llvm.experimental.constrained.fptoui.i16.f64(double, metadata)
|
2019-08-29 00:33:36 +08:00
|
|
|
declare i32 @llvm.experimental.constrained.fptoui.i32.f64(double, metadata)
|
2019-11-20 07:51:19 +08:00
|
|
|
declare i64 @llvm.experimental.constrained.fptoui.i64.f64(double, metadata)
|
2019-11-28 09:44:43 +08:00
|
|
|
declare i128 @llvm.experimental.constrained.fptoui.i128.f64(double, metadata)
|
2019-05-13 21:23:30 +08:00
|
|
|
declare float @llvm.experimental.constrained.fptrunc.f32.f64(double, metadata, metadata)
|
|
|
|
declare double @llvm.experimental.constrained.fpext.f64.f32(float, metadata)
|
2019-10-07 21:20:00 +08:00
|
|
|
declare i32 @llvm.experimental.constrained.lrint.i32.f64(double, metadata, metadata)
|
|
|
|
declare i32 @llvm.experimental.constrained.lrint.i32.f32(float, metadata, metadata)
|
|
|
|
declare i64 @llvm.experimental.constrained.llrint.i64.f64(double, metadata, metadata)
|
|
|
|
declare i64 @llvm.experimental.constrained.llrint.i64.f32(float, metadata, metadata)
|
|
|
|
declare i32 @llvm.experimental.constrained.lround.i32.f64(double, metadata)
|
|
|
|
declare i32 @llvm.experimental.constrained.lround.i32.f32(float, metadata)
|
|
|
|
declare i64 @llvm.experimental.constrained.llround.i64.f64(double, metadata)
|
|
|
|
declare i64 @llvm.experimental.constrained.llround.i64.f32(float, metadata)
|