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llvm-project/llvm/test/TableGen/dag-isel-regclass-emit-enum.td

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[TableGen] Fix register class handling in TableGen's DAG ISel Matcher Generator Summary: In TableGen's instruction selection table generator, references to register classes were handled by generating a matcher table entry in the form of "EmitStringInteger, MVT::i32, 'RegisterClassID'". This ID is in fact the enum integer value corresponding to the register class. However, both the table generator and the table consumer (SelectionDAGISel) assume that this ID is less than or equal to 127, i.e. at most 7 bits. Values greater than this threshold cause completely wrong behaviours in the instruction selection process. This patch adds a check to determine if the enum integer value is greater than the limit of 127. In finding so, the generator emits an "EmitInteger" instead, which properly supports values with arbitrary sizes. Commit f8d044bbcfdc9e1ddc02247ffb86fe39e1f277f0 fixed the very same bug for register subindices. The present patch now extends this cover to register classes. Reviewers: rampitec Reviewed By: rampitec Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D79705
2020-05-05 22:42:23 +08:00
// RUN: llvm-tblgen -gen-dag-isel -I %p/../../include %s | FileCheck %s
include "llvm/Target/Target.td"
def TestTargetInstrInfo : InstrInfo;
def TestTarget : Target {
let InstructionSet = TestTargetInstrInfo;
}
let Namespace = "TestNamespace" in {
def R0 : Register<"r0">;
Update TableGen test files to use the new '...' range punctuation.
2020-09-11 22:26:26 +08:00
foreach i = 0...127 in {
[TableGen] Fix register class handling in TableGen's DAG ISel Matcher Generator Summary: In TableGen's instruction selection table generator, references to register classes were handled by generating a matcher table entry in the form of "EmitStringInteger, MVT::i32, 'RegisterClassID'". This ID is in fact the enum integer value corresponding to the register class. However, both the table generator and the table consumer (SelectionDAGISel) assume that this ID is less than or equal to 127, i.e. at most 7 bits. Values greater than this threshold cause completely wrong behaviours in the instruction selection process. This patch adds a check to determine if the enum integer value is greater than the limit of 127. In finding so, the generator emits an "EmitInteger" instead, which properly supports values with arbitrary sizes. Commit f8d044bbcfdc9e1ddc02247ffb86fe39e1f277f0 fixed the very same bug for register subindices. The present patch now extends this cover to register classes. Reviewers: rampitec Reviewed By: rampitec Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D79705
2020-05-05 22:42:23 +08:00
def GPR#i : RegisterClass<"TestTarget", [i32], 32,
(add R0)>;
}
def GPRAbove127 : RegisterClass<"TestTarget", [i32], 32,
(add R0)>;
} // end Namespace TestNamespace
// CHECK: OPC_CheckOpcode, TARGET_VAL(ISD::ADD),
// CHECK-NEXT: OPC_RecordChild0, // #0 = $src
// CHECK-NEXT: OPC_Scope, 14, /*->20*/ // 2 children in Scope
// CHECK-NEXT: OPC_CheckChild1Integer, 0,
[TableGen] Use sign rotated VBR for OPC_EmitInteger. This allows for a much more efficient encoding for small negative numbers by storing the sign bit first and negating the rest of the bits. This was already being used for OPC_CheckInteger. For every in tree target this affects, the table got smaller. R600GenDAGISel.inc saw the largest reduction of 7K. I did have to add a new opcode for StringIntegers used for register class ids and subregister indices since we don't have the integer value to encode. The enum name is emitted directly into the table. Previously assumed the enum would expand to a positive 7-bit number. We might be able to just shift that right by 1 and assume it is a positive 6 bit number, but that will need more investigation.
2021-05-03 03:33:44 +08:00
// CHECK-NEXT: OPC_EmitInteger, MVT::i32, 0|128,2/*256*/,
[TableGen] Fix register class handling in TableGen's DAG ISel Matcher Generator Summary: In TableGen's instruction selection table generator, references to register classes were handled by generating a matcher table entry in the form of "EmitStringInteger, MVT::i32, 'RegisterClassID'". This ID is in fact the enum integer value corresponding to the register class. However, both the table generator and the table consumer (SelectionDAGISel) assume that this ID is less than or equal to 127, i.e. at most 7 bits. Values greater than this threshold cause completely wrong behaviours in the instruction selection process. This patch adds a check to determine if the enum integer value is greater than the limit of 127. In finding so, the generator emits an "EmitInteger" instead, which properly supports values with arbitrary sizes. Commit f8d044bbcfdc9e1ddc02247ffb86fe39e1f277f0 fixed the very same bug for register subindices. The present patch now extends this cover to register classes. Reviewers: rampitec Reviewed By: rampitec Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D79705
2020-05-05 22:42:23 +08:00
// CHECK-NEXT: OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
// CHECK-NEXT: MVT::i32, 2/*#Ops*/, 1, 0,
def : Pat<(i32 (add i32:$src, (i32 0))),
(COPY_TO_REGCLASS GPRAbove127, GPR0:$src)>;
[TableGen][SelectionDAG] Improve efficiency of encoding negative immediates for isel's CheckInteger opcode. CheckInteger uses an int64_t encoded using a variable width encoding that is optimized for encoding a number with a lot of leading zeros. Negative numbers have no leading zeros so use the largest encoding requiring 9 bytes. I believe its most like we want to check for positive and negative numbers near 0. -1 is quite common due to its use in the 'not' idiom. To optimize for this, we can borrow an idea from the bitcode format and move the sign bit to bit 0 with the magnitude stored in the upper bits. This will drastically increase the number of leading zeros for small magnitudes. Then we can run this value through VBR encoding. This gives a small reduction in the table size on all in tree targets except VE where size increased by about 300 bytes due to intrinsic ids now requiring 3 bytes instead of 2. Since the intrinsic enum space is shared by all targets this an unfortunate consquence of where VE is currently located in the range. Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D96317
2021-02-19 00:45:08 +08:00
// CHECK: OPC_CheckChild1Integer, 2,
[TableGen] Use sign rotated VBR for OPC_EmitInteger. This allows for a much more efficient encoding for small negative numbers by storing the sign bit first and negating the rest of the bits. This was already being used for OPC_CheckInteger. For every in tree target this affects, the table got smaller. R600GenDAGISel.inc saw the largest reduction of 7K. I did have to add a new opcode for StringIntegers used for register class ids and subregister indices since we don't have the integer value to encode. The enum name is emitted directly into the table. Previously assumed the enum would expand to a positive 7-bit number. We might be able to just shift that right by 1 and assume it is a positive 6 bit number, but that will need more investigation.
2021-05-03 03:33:44 +08:00
// CHECK-NEXT: OPC_EmitStringInteger, MVT::i32, TestNamespace::GPR127RegClassID,
[TableGen] Fix register class handling in TableGen's DAG ISel Matcher Generator Summary: In TableGen's instruction selection table generator, references to register classes were handled by generating a matcher table entry in the form of "EmitStringInteger, MVT::i32, 'RegisterClassID'". This ID is in fact the enum integer value corresponding to the register class. However, both the table generator and the table consumer (SelectionDAGISel) assume that this ID is less than or equal to 127, i.e. at most 7 bits. Values greater than this threshold cause completely wrong behaviours in the instruction selection process. This patch adds a check to determine if the enum integer value is greater than the limit of 127. In finding so, the generator emits an "EmitInteger" instead, which properly supports values with arbitrary sizes. Commit f8d044bbcfdc9e1ddc02247ffb86fe39e1f277f0 fixed the very same bug for register subindices. The present patch now extends this cover to register classes. Reviewers: rampitec Reviewed By: rampitec Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D79705
2020-05-05 22:42:23 +08:00
// CHECK-NEXT: OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
// CHECK-NEXT: MVT::i32, 2/*#Ops*/, 1, 0,
def : Pat<(i32 (add i32:$src, (i32 1))),
(COPY_TO_REGCLASS GPR127, GPR0:$src)>;