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llvm-project/llvm/lib/Target/Mips/MicroMipsInstrFPU.td

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Support for microMIPS FPU instructions 1. llvm-svn: 197815
2013-12-20 23:44:08 +08:00
let isCodeGenOnly = 1, Predicates = [InMicroMips] in {
[mips][sched] Split IIFadd into II_ADD_[DS], II_SUB_[DS] No functional change since the InstrItinData's have been duplicated. llvm-svn: 199732
2014-01-21 20:38:07 +08:00
def FADD_S_MM : MMRel, ADDS_FT<"add.s", FGR32Opnd, II_ADD_S, 1, fadd>,
Support for microMIPS FPU instructions 1. llvm-svn: 197815
2013-12-20 23:44:08 +08:00
ADDS_FM_MM<0, 0x30>;
[mips][sched] Renamed II_FdivSingle and II_FdivDouble to II_DIV_S and II_DIV_D respectively No functional change llvm-svn: 199738
2014-01-21 21:22:08 +08:00
def FDIV_S_MM : MMRel, ADDS_FT<"div.s", FGR32Opnd, II_DIV_S, 0, fdiv>,
Support for microMIPS FPU instructions 1. llvm-svn: 197815
2013-12-20 23:44:08 +08:00
ADDS_FM_MM<0, 0xf0>;
[mips][sched] Split IIFmulSingle into II_MUL_S, II_MADD_S, II_MSUB_S, II_NMADD_S, and II_NMSUB_S No functional change since the InstrItinData's have been duplicated. llvm-svn: 199734
2014-01-21 20:51:44 +08:00
def FMUL_S_MM : MMRel, ADDS_FT<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>,
Support for microMIPS FPU instructions 1. llvm-svn: 197815
2013-12-20 23:44:08 +08:00
ADDS_FM_MM<0, 0xb0>;
[mips][sched] Split IIFadd into II_ADD_[DS], II_SUB_[DS] No functional change since the InstrItinData's have been duplicated. llvm-svn: 199732
2014-01-21 20:38:07 +08:00
def FSUB_S_MM : MMRel, ADDS_FT<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>,
Support for microMIPS FPU instructions 1. llvm-svn: 197815
2013-12-20 23:44:08 +08:00
ADDS_FM_MM<0, 0x70>;
[mips][sched] Split IIFadd into II_ADD_[DS], II_SUB_[DS] No functional change since the InstrItinData's have been duplicated. llvm-svn: 199732
2014-01-21 20:38:07 +08:00
def FADD_MM : MMRel, ADDS_FT<"add.d", AFGR64Opnd, II_ADD_D, 1, fadd>,
Support for microMIPS FPU instructions 1. llvm-svn: 197815
2013-12-20 23:44:08 +08:00
ADDS_FM_MM<1, 0x30>;
[mips][sched] Renamed II_FdivSingle and II_FdivDouble to II_DIV_S and II_DIV_D respectively No functional change llvm-svn: 199738
2014-01-21 21:22:08 +08:00
def FDIV_MM : MMRel, ADDS_FT<"div.d", AFGR64Opnd, II_DIV_D, 0, fdiv>,
Support for microMIPS FPU instructions 1. llvm-svn: 197815
2013-12-20 23:44:08 +08:00
ADDS_FM_MM<1, 0xf0>;
[mips][sched] Split IIFmulDouble into II_MUL_D, II_MADD_D, II_MSUB_D, II_NMADD_D, and II_NMSUB_S No functional change since the InstrItinData's have been duplicated. llvm-svn: 199737
2014-01-21 21:07:31 +08:00
def FMUL_MM : MMRel, ADDS_FT<"mul.d", AFGR64Opnd, II_MUL_D, 1, fmul>,
Support for microMIPS FPU instructions 1. llvm-svn: 197815
2013-12-20 23:44:08 +08:00
ADDS_FM_MM<1, 0xb0>;
[mips][sched] Split IIFadd into II_ADD_[DS], II_SUB_[DS] No functional change since the InstrItinData's have been duplicated. llvm-svn: 199732
2014-01-21 20:38:07 +08:00
def FSUB_MM : MMRel, ADDS_FT<"sub.d", AFGR64Opnd, II_SUB_D, 0, fsub>,
Support for microMIPS FPU instructions 1. llvm-svn: 197815
2013-12-20 23:44:08 +08:00
ADDS_FM_MM<1, 0x70>;
[mips][sched] Split IIFLoad into II_L[WD]C1, and II_L[WDU]XC1 No functional change since the InstrItinData's have been duplicated. llvm-svn: 199743
2014-01-21 21:59:56 +08:00
def LWXC1_MM : MMRel, LWXC1_FT<"lwxc1", FGR32Opnd, II_LWXC1, load>,
[mips][mips64r6] [sl][duw]xc1 are not available on MIPS32r6/MIPS64r6 Summary: Folded mips64-fp-indexed-ls.ll into fp-indexed-ls.ll. To do so, the zext's in mips64-fp-indexed-ls.ll were changed to implicit sign extensions (performed by getelementptr). This does not affect the purpose of the test. Depends on D4004 Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4110 llvm-svn: 210784
2014-06-12 22:19:28 +08:00
LWXC1_FM_MM<0x48>, INSN_MIPS4_32R2_NOT_32R6_64R6;
[mips][sched] Split IIFStore into II_S[WD]C1, and II_S[WDU]XC1 No functional change since the InstrItinData's have been duplicated. llvm-svn: 199747
2014-01-21 22:50:20 +08:00
def SWXC1_MM : MMRel, SWXC1_FT<"swxc1", FGR32Opnd, II_SWXC1, store>,
[mips][mips64r6] [sl][duw]xc1 are not available on MIPS32r6/MIPS64r6 Summary: Folded mips64-fp-indexed-ls.ll into fp-indexed-ls.ll. To do so, the zext's in mips64-fp-indexed-ls.ll were changed to implicit sign extensions (performed by getelementptr). This does not affect the purpose of the test. Depends on D4004 Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4110 llvm-svn: 210784
2014-06-12 22:19:28 +08:00
SWXC1_FM_MM<0x88>, INSN_MIPS4_32R2_NOT_32R6_64R6;
[mips][sched] Split IIFLoad into II_L[WD]C1, and II_L[WDU]XC1 No functional change since the InstrItinData's have been duplicated. llvm-svn: 199743
2014-01-21 21:59:56 +08:00
def LUXC1_MM : MMRel, LWXC1_FT<"luxc1", AFGR64Opnd, II_LUXC1>,
[mips][mips64r6] [sl][duw]xc1 are not available on MIPS32r6/MIPS64r6 Summary: Folded mips64-fp-indexed-ls.ll into fp-indexed-ls.ll. To do so, the zext's in mips64-fp-indexed-ls.ll were changed to implicit sign extensions (performed by getelementptr). This does not affect the purpose of the test. Depends on D4004 Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4110 llvm-svn: 210784
2014-06-12 22:19:28 +08:00
LWXC1_FM_MM<0x148>, INSN_MIPS5_32R2_NOT_32R6_64R6;
[mips][sched] Split IIFStore into II_S[WD]C1, and II_S[WDU]XC1 No functional change since the InstrItinData's have been duplicated. llvm-svn: 199747
2014-01-21 22:50:20 +08:00
def SUXC1_MM : MMRel, SWXC1_FT<"suxc1", AFGR64Opnd, II_SUXC1>,
[mips][mips64r6] [sl][duw]xc1 are not available on MIPS32r6/MIPS64r6 Summary: Folded mips64-fp-indexed-ls.ll into fp-indexed-ls.ll. To do so, the zext's in mips64-fp-indexed-ls.ll were changed to implicit sign extensions (performed by getelementptr). This does not affect the purpose of the test. Depends on D4004 Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4110 llvm-svn: 210784
2014-06-12 22:19:28 +08:00
SWXC1_FM_MM<0x188>, INSN_MIPS5_32R2_NOT_32R6_64R6;
Support for microMIPS FPU instructions 1. llvm-svn: 197815
2013-12-20 23:44:08 +08:00
Revert "[mips] Fix c.<cc>.<fmt> instruction definition." This reverts commit r281022. Mips buildbot broke, due to unhandled register class FCC. llvm-svn: 281033
2016-09-09 19:06:01 +08:00
def FCMP_S32_MM : MMRel, CEQS_FT<"s", FGR32, II_C_CC_S, MipsFPCmp>,
[mips] Correct c.cond.fmt instruction definition. Permit explicit $fcc<X> operand in c.cond.fmt instruction. Add c.cond.fmt to the MIPS to microMIPS instruction mapping table. Check that $fcc1 - $fcc7 are unusable for MIPS-I to MIPS-III for c.cond.fmt, bc1t, bc1f. Reviewers: seanbruno, zoran.jovanovic, vkalintiris Differential Revision: https://reviews.llvm.org/D24510 llvm-svn: 292117
2017-01-16 21:55:58 +08:00
CEQS_FM_MM<0> {
// FIXME: This is a required to work around the fact that these instructions
// only use $fcc0. Ideally, MipsFPCmp nodes could be removed and the
// fcc register set is used directly.
bits<3> fcc = 0;
}
Revert "[mips] Fix c.<cc>.<fmt> instruction definition." This reverts commit r281022. Mips buildbot broke, due to unhandled register class FCC. llvm-svn: 281033
2016-09-09 19:06:01 +08:00
def FCMP_D32_MM : MMRel, CEQS_FT<"d", AFGR64, II_C_CC_D, MipsFPCmp>,
[mips] Correct c.cond.fmt instruction definition. Permit explicit $fcc<X> operand in c.cond.fmt instruction. Add c.cond.fmt to the MIPS to microMIPS instruction mapping table. Check that $fcc1 - $fcc7 are unusable for MIPS-I to MIPS-III for c.cond.fmt, bc1t, bc1f. Reviewers: seanbruno, zoran.jovanovic, vkalintiris Differential Revision: https://reviews.llvm.org/D24510 llvm-svn: 292117
2017-01-16 21:55:58 +08:00
CEQS_FM_MM<1> {
// FIXME: This is a required to work around the fact that these instructions
// only use $fcc0. Ideally, MipsFPCmp nodes could be removed and the
// fcc register set is used directly.
bits<3> fcc = 0;
}
Revert "[mips] Fix c.<cc>.<fmt> instruction definition." This reverts commit r281022. Mips buildbot broke, due to unhandled register class FCC. llvm-svn: 281033
2016-09-09 19:06:01 +08:00
[mips][sched] Split IIBranch into specific instruction classes. Summary: Almost no functional change since the InstrItinData's have been duplicated. The one functional change is to remove IIBranch from the MSA branches. The classes will be assigned to the MSA instructions as part of implementing the P5600 scheduler. II_IndirectBranchPseudo and II_ReturnPseudo can probably be removed. I've preserved the itinerary information for the corresponding pseudo instructions to avoid making a functional change to these pseudos in this patch. Reviewers: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D12189 llvm-svn: 248273
2015-09-22 21:36:28 +08:00
def BC1F_MM : MMRel, BC1F_FT<"bc1f", brtarget_mm, II_BC1F, MIPS_BRANCH_F>,
[mips][mips64r6] bc1[tf] are not available on MIPS32r6/MIPS64r6 Summary: Also tightened up the acceptable condition operand for these instructions on MIPS-I to MIPS-III. Support for $fcc[1-7] was added in MIPS-IV. Prior to that only $fcc0 is acceptable. We currently don't optimize (BEQZ (NOT $a), $target) and similar. It's probably best to do this in InstCombine. Depends on D4111 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4112 llvm-svn: 210787
2014-06-12 23:00:17 +08:00
BC1F_FM_MM<0x1c>, ISA_MIPS1_NOT_32R6_64R6;
[mips][sched] Split IIBranch into specific instruction classes. Summary: Almost no functional change since the InstrItinData's have been duplicated. The one functional change is to remove IIBranch from the MSA branches. The classes will be assigned to the MSA instructions as part of implementing the P5600 scheduler. II_IndirectBranchPseudo and II_ReturnPseudo can probably be removed. I've preserved the itinerary information for the corresponding pseudo instructions to avoid making a functional change to these pseudos in this patch. Reviewers: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D12189 llvm-svn: 248273
2015-09-22 21:36:28 +08:00
def BC1T_MM : MMRel, BC1F_FT<"bc1t", brtarget_mm, II_BC1T, MIPS_BRANCH_T>,
[mips][mips64r6] bc1[tf] are not available on MIPS32r6/MIPS64r6 Summary: Also tightened up the acceptable condition operand for these instructions on MIPS-I to MIPS-III. Support for $fcc[1-7] was added in MIPS-IV. Prior to that only $fcc0 is acceptable. We currently don't optimize (BEQZ (NOT $a), $target) and similar. It's probably best to do this in InstCombine. Depends on D4111 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4112 llvm-svn: 210787
2014-06-12 23:00:17 +08:00
BC1F_FM_MM<0x1d>, ISA_MIPS1_NOT_32R6_64R6;
[mips][sched] Split IIFcvt into II_(ROUND|TRUNC|CEIL|FLOOR|CVT), II_ABS, II_NEG No functional change since the InstrItinData's have been duplicated. llvm-svn: 199722
2014-01-21 18:56:23 +08:00
def CVT_W_S_MM : MMRel, ABSS_FT<"cvt.w.s", FGR32Opnd, FGR32Opnd, II_CVT>,
Support for microMIPS FPU instructions 1. llvm-svn: 197815
2013-12-20 23:44:08 +08:00
ROUND_W_FM_MM<0, 0x24>;
[mips][microMIPS] Implement RECIP.fmt, RINT.fmt, ROUND.L.fmt, ROUND.W.fmt, SEL.fmt, SELEQZ.fmt, SELNEQZ.fmt and CLASS.fmt Differential Revision: http://reviews.llvm.org/D13885 llvm-svn: 254405
2015-12-01 19:59:21 +08:00
def ROUND_W_S_MM : MMRel, StdMMR6Rel, ABSS_FT<"round.w.s", FGR32Opnd, FGR32Opnd, II_ROUND>,
Support for microMIPS FPU instructions 1. llvm-svn: 197815
2013-12-20 23:44:08 +08:00
ROUND_W_FM_MM<0, 0xec>;
[mips][sched] Split IIFcvt into II_(ROUND|TRUNC|CEIL|FLOOR|CVT), II_ABS, II_NEG No functional change since the InstrItinData's have been duplicated. llvm-svn: 199722
2014-01-21 18:56:23 +08:00
def CEIL_W_MM : MMRel, ABSS_FT<"ceil.w.d", FGR32Opnd, AFGR64Opnd, II_CEIL>,
Support for microMIPS FPU instructions 1. llvm-svn: 197815
2013-12-20 23:44:08 +08:00
ROUND_W_FM_MM<1, 0x6c>;
[mips][sched] Split IIFcvt into II_(ROUND|TRUNC|CEIL|FLOOR|CVT), II_ABS, II_NEG No functional change since the InstrItinData's have been duplicated. llvm-svn: 199722
2014-01-21 18:56:23 +08:00
def CVT_W_MM : MMRel, ABSS_FT<"cvt.w.d", FGR32Opnd, AFGR64Opnd, II_CVT>,
Support for microMIPS FPU instructions 1. llvm-svn: 197815
2013-12-20 23:44:08 +08:00
ROUND_W_FM_MM<1, 0x24>;
[mips][sched] Split IIFcvt into II_(ROUND|TRUNC|CEIL|FLOOR|CVT), II_ABS, II_NEG No functional change since the InstrItinData's have been duplicated. llvm-svn: 199722
2014-01-21 18:56:23 +08:00
def FLOOR_W_MM : MMRel, ABSS_FT<"floor.w.d", FGR32Opnd, AFGR64Opnd, II_FLOOR>,
Support for microMIPS FPU instructions 1. llvm-svn: 197815
2013-12-20 23:44:08 +08:00
ROUND_W_FM_MM<1, 0x2c>;
[mips][microMIPS] Implement RECIP.fmt, RINT.fmt, ROUND.L.fmt, ROUND.W.fmt, SEL.fmt, SELEQZ.fmt, SELNEQZ.fmt and CLASS.fmt Differential Revision: http://reviews.llvm.org/D13885 llvm-svn: 254405
2015-12-01 19:59:21 +08:00
def ROUND_W_MM : MMRel, StdMMR6Rel, ABSS_FT<"round.w.d", FGR32Opnd, AFGR64Opnd, II_ROUND>,
Support for microMIPS FPU instructions 1. llvm-svn: 197815
2013-12-20 23:44:08 +08:00
ROUND_W_FM_MM<1, 0xec>;
[mips][sched] Split IIFcvt into II_(ROUND|TRUNC|CEIL|FLOOR|CVT), II_ABS, II_NEG No functional change since the InstrItinData's have been duplicated. llvm-svn: 199722
2014-01-21 18:56:23 +08:00
def TRUNC_W_MM : MMRel, ABSS_FT<"trunc.w.d", FGR32Opnd, AFGR64Opnd, II_TRUNC>,
Support for microMIPS FPU instructions 1. llvm-svn: 197815
2013-12-20 23:44:08 +08:00
ROUND_W_FM_MM<1, 0xac>;
[mips][sched] Renamed II_FsqrtSingle and II_FsqrtDouble to II_SQRT_S and II_SQRT_D respectively No functional change llvm-svn: 199741
2014-01-21 21:36:45 +08:00
def FSQRT_MM : MMRel, ABSS_FT<"sqrt.d", AFGR64Opnd, AFGR64Opnd, II_SQRT_D,
fsqrt>, ROUND_W_FM_MM<1, 0x28>;
Support for microMIPS FPU instructions 1. llvm-svn: 197815
2013-12-20 23:44:08 +08:00
[mips][sched] Split IIFcvt into II_(ROUND|TRUNC|CEIL|FLOOR|CVT), II_ABS, II_NEG No functional change since the InstrItinData's have been duplicated. llvm-svn: 199722
2014-01-21 18:56:23 +08:00
def CVT_L_S_MM : MMRel, ABSS_FT<"cvt.l.s", FGR64Opnd, FGR32Opnd, II_CVT>,
[mips] Marked up instructions added in MIPS32r2 and tested that IAS for -mcpu=mips(2|32) does not accept them Summary: This required a new instruction group representing the 32-bit subset of MIPS-3 that was available in MIPS32R2. To limit the number of tests required, only one 32-bit and one 64-bit ISA prior to MIPS32/MIPS64 are tested. rdhwr has been deliberately left without an ISA annotation for now. This is because the assembler and CodeGen disagree on when the instruction is available. Strictly speaking, it is only available in MIPS32r2 and MIPS64r2. However, it is emulated by a kernel trap on earlier ISA's and is necessary for TLS so CodeGen should emit it on older ISA's too. Depends on D3696 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3697 llvm-svn: 208690
2014-05-13 19:45:36 +08:00
ROUND_W_FM_MM<0, 0x4>, INSN_MIPS3_32R2;
[mips][sched] Split IIFcvt into II_(ROUND|TRUNC|CEIL|FLOOR|CVT), II_ABS, II_NEG No functional change since the InstrItinData's have been duplicated. llvm-svn: 199722
2014-01-21 18:56:23 +08:00
def CVT_L_D64_MM : MMRel, ABSS_FT<"cvt.l.d", FGR64Opnd, FGR64Opnd, II_CVT>,
[mips] Marked up instructions added in MIPS32r2 and tested that IAS for -mcpu=mips(2|32) does not accept them Summary: This required a new instruction group representing the 32-bit subset of MIPS-3 that was available in MIPS32R2. To limit the number of tests required, only one 32-bit and one 64-bit ISA prior to MIPS32/MIPS64 are tested. rdhwr has been deliberately left without an ISA annotation for now. This is because the assembler and CodeGen disagree on when the instruction is available. Strictly speaking, it is only available in MIPS32r2 and MIPS64r2. However, it is emulated by a kernel trap on earlier ISA's and is necessary for TLS so CodeGen should emit it on older ISA's too. Depends on D3696 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3697 llvm-svn: 208690
2014-05-13 19:45:36 +08:00
ROUND_W_FM_MM<1, 0x4>, INSN_MIPS3_32R2;
Support for microMIPS FPU instructions 1. llvm-svn: 197815
2013-12-20 23:44:08 +08:00
[mips][sched] Split IIFcvt into II_(ROUND|TRUNC|CEIL|FLOOR|CVT), II_ABS, II_NEG No functional change since the InstrItinData's have been duplicated. llvm-svn: 199722
2014-01-21 18:56:23 +08:00
def FABS_S_MM : MMRel, ABSS_FT<"abs.s", FGR32Opnd, FGR32Opnd, II_ABS, fabs>,
Support for microMIPS FPU instructions 1. llvm-svn: 197815
2013-12-20 23:44:08 +08:00
ABS_FM_MM<0, 0xd>;
[mips][sched] Split IIFmove into II_C[FT]C1, II_MOV[FNTZ]_[SD], II_MOV_[SD] No functional change since the InstrItinData's have been duplicated. llvm-svn: 199727
2014-01-21 19:28:03 +08:00
def FMOV_S_MM : MMRel, ABSS_FT<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>,
Support for microMIPS FPU instructions 1. llvm-svn: 197815
2013-12-20 23:44:08 +08:00
ABS_FM_MM<0, 0x1>;
[mips][sched] Split IIFcvt into II_(ROUND|TRUNC|CEIL|FLOOR|CVT), II_ABS, II_NEG No functional change since the InstrItinData's have been duplicated. llvm-svn: 199722
2014-01-21 18:56:23 +08:00
def FNEG_S_MM : MMRel, ABSS_FT<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>,
Support for microMIPS FPU instructions 1. llvm-svn: 197815
2013-12-20 23:44:08 +08:00
ABS_FM_MM<0, 0x2d>;
[mips][sched] Split IIFcvt into II_(ROUND|TRUNC|CEIL|FLOOR|CVT), II_ABS, II_NEG No functional change since the InstrItinData's have been duplicated. llvm-svn: 199722
2014-01-21 18:56:23 +08:00
def CVT_D_S_MM : MMRel, ABSS_FT<"cvt.d.s", AFGR64Opnd, FGR32Opnd, II_CVT>,
Support for microMIPS FPU instructions 1. llvm-svn: 197815
2013-12-20 23:44:08 +08:00
ABS_FM_MM<0, 0x4d>;
[mips][sched] Split IIFcvt into II_(ROUND|TRUNC|CEIL|FLOOR|CVT), II_ABS, II_NEG No functional change since the InstrItinData's have been duplicated. llvm-svn: 199722
2014-01-21 18:56:23 +08:00
def CVT_D32_W_MM : MMRel, ABSS_FT<"cvt.d.w", AFGR64Opnd, FGR32Opnd, II_CVT>,
Support for microMIPS FPU instructions 1. llvm-svn: 197815
2013-12-20 23:44:08 +08:00
ABS_FM_MM<1, 0x4d>;
[mips][sched] Split IIFcvt into II_(ROUND|TRUNC|CEIL|FLOOR|CVT), II_ABS, II_NEG No functional change since the InstrItinData's have been duplicated. llvm-svn: 199722
2014-01-21 18:56:23 +08:00
def CVT_S_D32_MM : MMRel, ABSS_FT<"cvt.s.d", FGR32Opnd, AFGR64Opnd, II_CVT>,
Support for microMIPS FPU instructions 1. llvm-svn: 197815
2013-12-20 23:44:08 +08:00
ABS_FM_MM<0, 0x6d>;
[mips][sched] Split IIFcvt into II_(ROUND|TRUNC|CEIL|FLOOR|CVT), II_ABS, II_NEG No functional change since the InstrItinData's have been duplicated. llvm-svn: 199722
2014-01-21 18:56:23 +08:00
def CVT_S_W_MM : MMRel, ABSS_FT<"cvt.s.w", FGR32Opnd, FGR32Opnd, II_CVT>,
Support for microMIPS FPU instructions 1. llvm-svn: 197815
2013-12-20 23:44:08 +08:00
ABS_FM_MM<1, 0x6d>;
[mips][sched] Split IIFcvt into II_(ROUND|TRUNC|CEIL|FLOOR|CVT), II_ABS, II_NEG No functional change since the InstrItinData's have been duplicated. llvm-svn: 199722
2014-01-21 18:56:23 +08:00
def FABS_MM : MMRel, ABSS_FT<"abs.d", AFGR64Opnd, AFGR64Opnd, II_ABS, fabs>,
Support for microMIPS FPU instructions 1. llvm-svn: 197815
2013-12-20 23:44:08 +08:00
ABS_FM_MM<1, 0xd>;
[mips][sched] Split IIFcvt into II_(ROUND|TRUNC|CEIL|FLOOR|CVT), II_ABS, II_NEG No functional change since the InstrItinData's have been duplicated. llvm-svn: 199722
2014-01-21 18:56:23 +08:00
def FNEG_MM : MMRel, ABSS_FT<"neg.d", AFGR64Opnd, AFGR64Opnd, II_NEG, fneg>,
Support for microMIPS FPU instructions 1. llvm-svn: 197815
2013-12-20 23:44:08 +08:00
ABS_FM_MM<1, 0x2d>;
[mips][sched] Split IIFmove into II_C[FT]C1, II_MOV[FNTZ]_[SD], II_MOV_[SD] No functional change since the InstrItinData's have been duplicated. llvm-svn: 199727
2014-01-21 19:28:03 +08:00
def FMOV_D32_MM : MMRel, ABSS_FT<"mov.d", AFGR64Opnd, AFGR64Opnd, II_MOV_D>,
[mips] Only use FGR_{32,64} in TableGen descriptions. NFC. Summary: Instead of explicitly adding the IsFP64bit and NotFP64bit predicates through AdditionalRequires. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9566 llvm-svn: 236835
2015-05-08 20:15:04 +08:00
ABS_FM_MM<1, 0x1>, FGR_32;
Support for microMIPS FPU instructions 2. llvm-svn: 198009
2013-12-25 18:09:27 +08:00
[mips][sched] Split IIFmove into II_C[FT]C1, II_MOV[FNTZ]_[SD], II_MOV_[SD] No functional change since the InstrItinData's have been duplicated. llvm-svn: 199727
2014-01-21 19:28:03 +08:00
def MOVZ_I_S_MM : MMRel, CMov_I_F_FT<"movz.s", GPR32Opnd, FGR32Opnd,
II_MOVZ_S>, CMov_I_F_FM_MM<0x78, 0>;
def MOVN_I_S_MM : MMRel, CMov_I_F_FT<"movn.s", GPR32Opnd, FGR32Opnd,
II_MOVN_S>, CMov_I_F_FM_MM<0x38, 0>;
Support for microMIPS FPU instructions 2. llvm-svn: 198009
2013-12-25 18:09:27 +08:00
def MOVZ_I_D32_MM : MMRel, CMov_I_F_FT<"movz.d", GPR32Opnd, AFGR64Opnd,
[mips][sched] Split IIFmove into II_C[FT]C1, II_MOV[FNTZ]_[SD], II_MOV_[SD] No functional change since the InstrItinData's have been duplicated. llvm-svn: 199727
2014-01-21 19:28:03 +08:00
II_MOVZ_D>, CMov_I_F_FM_MM<0x78, 1>;
Support for microMIPS FPU instructions 2. llvm-svn: 198009
2013-12-25 18:09:27 +08:00
def MOVN_I_D32_MM : MMRel, CMov_I_F_FT<"movn.d", GPR32Opnd, AFGR64Opnd,
[mips][sched] Split IIFmove into II_C[FT]C1, II_MOV[FNTZ]_[SD], II_MOV_[SD] No functional change since the InstrItinData's have been duplicated. llvm-svn: 199727
2014-01-21 19:28:03 +08:00
II_MOVN_D>, CMov_I_F_FM_MM<0x38, 1>;
Support for microMIPS FPU instructions 2. llvm-svn: 198009
2013-12-25 18:09:27 +08:00
[mips][sched] Split IIFmove into II_C[FT]C1, II_MOV[FNTZ]_[SD], II_MOV_[SD] No functional change since the InstrItinData's have been duplicated. llvm-svn: 199727
2014-01-21 19:28:03 +08:00
def MOVT_S_MM : MMRel, CMov_F_F_FT<"movt.s", FGR32Opnd, II_MOVT_S,
MipsCMovFP_T>, CMov_F_F_FM_MM<0x60, 0>;
def MOVF_S_MM : MMRel, CMov_F_F_FT<"movf.s", FGR32Opnd, II_MOVF_S,
MipsCMovFP_F>, CMov_F_F_FM_MM<0x20, 0>;
def MOVT_D32_MM : MMRel, CMov_F_F_FT<"movt.d", AFGR64Opnd, II_MOVT_D,
MipsCMovFP_T>, CMov_F_F_FM_MM<0x60, 1>;
def MOVF_D32_MM : MMRel, CMov_F_F_FT<"movf.d", AFGR64Opnd, II_MOVF_D,
MipsCMovFP_F>, CMov_F_F_FM_MM<0x20, 1>;
Support for microMIPS FPU instructions 2. llvm-svn: 198009
2013-12-25 18:09:27 +08:00
def MFC1_MM : MMRel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd,
[mips][sched] Split IIFmoveC1 into II_M[FT]C1, II_M[FT]HC1, II_DM[FT]C1 No functional change since the InstrItinData's have been duplicated. llvm-svn: 199748
2014-01-21 23:03:52 +08:00
II_MFC1, bitconvert>, MFC1_FM_MM<0x80>;
Support for microMIPS FPU instructions 2. llvm-svn: 198009
2013-12-25 18:09:27 +08:00
def MTC1_MM : MMRel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd,
[mips][sched] Split IIFmoveC1 into II_M[FT]C1, II_M[FT]HC1, II_DM[FT]C1 No functional change since the InstrItinData's have been duplicated. llvm-svn: 199748
2014-01-21 23:03:52 +08:00
II_MTC1, bitconvert>, MFC1_FM_MM<0xa0>;
Support for microMIPS FPU instructions 2. llvm-svn: 198009
2013-12-25 18:09:27 +08:00
[mips][sched] Split IIFmulSingle into II_MUL_S, II_MADD_S, II_MSUB_S, II_NMADD_S, and II_NMSUB_S No functional change since the InstrItinData's have been duplicated. llvm-svn: 199734
2014-01-21 20:51:44 +08:00
def MADD_S_MM : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S, fadd>,
Support for microMIPS FPU instructions 2. llvm-svn: 198009
2013-12-25 18:09:27 +08:00
MADDS_FM_MM<0x1>;
[mips][sched] Split IIFmulSingle into II_MUL_S, II_MADD_S, II_MSUB_S, II_NMADD_S, and II_NMSUB_S No functional change since the InstrItinData's have been duplicated. llvm-svn: 199734
2014-01-21 20:51:44 +08:00
def MSUB_S_MM : MMRel, MADDS_FT<"msub.s", FGR32Opnd, II_MSUB_S, fsub>,
Support for microMIPS FPU instructions 2. llvm-svn: 198009
2013-12-25 18:09:27 +08:00
MADDS_FM_MM<0x21>;
[mips][sched] Split IIFmulSingle into II_MUL_S, II_MADD_S, II_MSUB_S, II_NMADD_S, and II_NMSUB_S No functional change since the InstrItinData's have been duplicated. llvm-svn: 199734
2014-01-21 20:51:44 +08:00
def NMADD_S_MM : MMRel, NMADDS_FT<"nmadd.s", FGR32Opnd, II_NMADD_S, fadd>,
Support for microMIPS FPU instructions 2. llvm-svn: 198009
2013-12-25 18:09:27 +08:00
MADDS_FM_MM<0x2>;
[mips][sched] Split IIFmulSingle into II_MUL_S, II_MADD_S, II_MSUB_S, II_NMADD_S, and II_NMSUB_S No functional change since the InstrItinData's have been duplicated. llvm-svn: 199734
2014-01-21 20:51:44 +08:00
def NMSUB_S_MM : MMRel, NMADDS_FT<"nmsub.s", FGR32Opnd, II_NMSUB_S, fsub>,
Support for microMIPS FPU instructions 2. llvm-svn: 198009
2013-12-25 18:09:27 +08:00
MADDS_FM_MM<0x22>;
[mips][sched] Split IIFmulDouble into II_MUL_D, II_MADD_D, II_MSUB_D, II_NMADD_D, and II_NMSUB_S No functional change since the InstrItinData's have been duplicated. llvm-svn: 199737
2014-01-21 21:07:31 +08:00
def MADD_D32_MM : MMRel, MADDS_FT<"madd.d", AFGR64Opnd, II_MADD_D, fadd>,
Support for microMIPS FPU instructions 2. llvm-svn: 198009
2013-12-25 18:09:27 +08:00
MADDS_FM_MM<0x9>;
[mips][sched] Split IIFmulDouble into II_MUL_D, II_MADD_D, II_MSUB_D, II_NMADD_D, and II_NMSUB_S No functional change since the InstrItinData's have been duplicated. llvm-svn: 199737
2014-01-21 21:07:31 +08:00
def MSUB_D32_MM : MMRel, MADDS_FT<"msub.d", AFGR64Opnd, II_MSUB_D, fsub>,
Support for microMIPS FPU instructions 2. llvm-svn: 198009
2013-12-25 18:09:27 +08:00
MADDS_FM_MM<0x29>;
[mips][sched] Split IIFmulDouble into II_MUL_D, II_MADD_D, II_MSUB_D, II_NMADD_D, and II_NMSUB_S No functional change since the InstrItinData's have been duplicated. llvm-svn: 199737
2014-01-21 21:07:31 +08:00
def NMADD_D32_MM : MMRel, NMADDS_FT<"nmadd.d", AFGR64Opnd, II_NMADD_D, fadd>,
MADDS_FM_MM<0xa>;
def NMSUB_D32_MM : MMRel, NMADDS_FT<"nmsub.d", AFGR64Opnd, II_NMSUB_D, fsub>,
MADDS_FM_MM<0x2a>;
Support for microMIPS FPU instructions 1. llvm-svn: 197815
2013-12-20 23:44:08 +08:00
}
[mips][microMIPS] Implement ABS.fmt, CEIL.L.fmt, CEIL.W.fmt, FLOOR.L.fmt, FLOOR.W.fmt, TRUNC.L.fmt, TRUNC.W.fmt, RSQRT.fmt and SQRT.fmt instructions Differential Revision: http://reviews.llvm.org/D11674 llvm-svn: 246968
2015-09-07 21:01:04 +08:00
let AdditionalPredicates = [InMicroMips] in {
def FLOOR_W_S_MM : MMRel, ABSS_FT<"floor.w.s", FGR32Opnd, FGR32Opnd,
II_FLOOR>, ROUND_W_FM_MM<0, 0x2c>;
def TRUNC_W_S_MM : MMRel, StdMMR6Rel, ABSS_FT<"trunc.w.s", FGR32Opnd,
FGR32Opnd, II_TRUNC>, ROUND_W_FM_MM<0, 0xac>;
def CEIL_W_S_MM : MMRel, ABSS_FT<"ceil.w.s", FGR32Opnd, FGR32Opnd, II_CEIL>,
ROUND_W_FM_MM<0, 0x6c>;
def FSQRT_S_MM : MMRel, ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd, II_SQRT_S,
fsqrt>, ROUND_W_FM_MM<0, 0x28>;
[mips][microMIPS] Implement MTC*, MTHC* and DMTC* instructions Differential Revision: http://reviews.llvm.org/D17328 llvm-svn: 264246
2016-03-24 16:02:09 +08:00
def MTHC1_MM : MMRel, MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>,
MFC1_FM_MM<0xe0>, ISA_MIPS32R2, FGR_32;
[mips][microMIPS] Implement MFC*, MFHC* and DMFC* instructions Differential Revision: http://reviews.llvm.org/D17334 llvm-svn: 265002
2016-03-31 16:51:24 +08:00
def MFHC1_MM : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, AFGR64Opnd, II_MFHC1>,
MFC1_FM_MM<0xc0>, ISA_MIPS32R2, FGR_32;
[mips][microMIPS] Implement CFC1, CFC2, CTC1 and CTC2 instructions Differential Revision: https://reviews.llvm.org/D22347 llvm-svn: 277719
2016-08-04 19:22:52 +08:00
let DecoderNamespace = "MicroMips" in {
def CFC1_MM : MMRel, MFC1_FT<"cfc1", GPR32Opnd, CCROpnd, II_CFC1>,
MFC1_FM_MM<0x40>;
def CTC1_MM : MMRel, MTC1_FT<"ctc1", CCROpnd, GPR32Opnd, II_CTC1>,
MFC1_FM_MM<0x60>;
Recommit: "[mips] Add rsqrt, recip for MIPS" Add rsqrt.[ds], recip.[ds] for MIPS. Correct the microMIPS definitions for architecture support and register usage. Reviewers: vkalintiris, zoran.jovanoic Differential Review: https://reviews.llvm.org/D24499 llvm-svn: 283334
2016-10-06 00:11:01 +08:00
def RECIP_S_MM : MMRel, ABSS_FT<"recip.s", FGR32Opnd, FGR32Opnd,
II_RECIP_S>,
ROUND_W_FM_MM<0b0, 0b01001000>;
def RECIP_D_MM : MMRel, ABSS_FT<"recip.d", AFGR64Opnd, AFGR64Opnd,
II_RECIP_D>, ROUND_W_FM_MM<0b1, 0b01001000>;
def RSQRT_S_MM : MMRel, ABSS_FT<"rsqrt.s", FGR32Opnd, FGR32Opnd,
II_RECIP_S>,
ROUND_W_FM_MM<0b0, 0b00001000>;
def RSQRT_D_MM : MMRel, ABSS_FT<"rsqrt.d", AFGR64Opnd, AFGR64Opnd,
II_RECIP_D>, ROUND_W_FM_MM<0b1, 0b00001000>;
[mips][microMIPS] Implement CFC1, CFC2, CTC1 and CTC2 instructions Differential Revision: https://reviews.llvm.org/D22347 llvm-svn: 277719
2016-08-04 19:22:52 +08:00
}
[mips][microMIPS] Implement LDC1, SDC1, LDC2, SDC2, LWC1, SWC1, LWC2 and SWC2 instructions and add CodeGen support Differential Revision: http://reviews.llvm.org/D18824 llvm-svn: 275050
2016-07-11 15:41:56 +08:00
let DecoderNamespace = "MicroMips", DecoderMethod = "DecodeFMemMMR2" in {
def LDC1_MM : MMRel, LW_FT<"ldc1", AFGR64Opnd, mem_mm_16, II_LDC1, load>,
LW_FM_MM<0x2f>, FGR_32 {
let BaseOpcode = "LDC132";
}
def SDC1_MM : MMRel, SW_FT<"sdc1", AFGR64Opnd, mem_mm_16, II_SDC1, store>,
LW_FM_MM<0x2e>, FGR_32;
def LWC1_MM : MMRel, LW_FT<"lwc1", FGR32Opnd, mem_mm_16, II_LWC1, load>,
LW_FM_MM<0x27>;
def SWC1_MM : MMRel, SW_FT<"swc1", FGR32Opnd, mem_mm_16, II_SWC1, store>,
LW_FM_MM<0x26>;
}
[mips] Correct c.cond.fmt instruction definition. Permit explicit $fcc<X> operand in c.cond.fmt instruction. Add c.cond.fmt to the MIPS to microMIPS instruction mapping table. Check that $fcc1 - $fcc7 are unusable for MIPS-I to MIPS-III for c.cond.fmt, bc1t, bc1f. Reviewers: seanbruno, zoran.jovanovic, vkalintiris Differential Revision: https://reviews.llvm.org/D24510 llvm-svn: 292117
2017-01-16 21:55:58 +08:00
multiclass C_COND_MM<string TypeStr, RegisterOperand RC, bits<2> fmt,
InstrItinClass itin> {
def C_F_#NAME#_MM : MMRel, C_COND_FT<"f", TypeStr, RC, itin>,
C_COND_FM_MM<fmt, 0> {
let BaseOpcode = "c.f."#NAME;
let isCommutable = 1;
}
def C_UN_#NAME#_MM : MMRel, C_COND_FT<"un", TypeStr, RC, itin>,
C_COND_FM_MM<fmt, 1> {
let BaseOpcode = "c.un."#NAME;
let isCommutable = 1;
}
def C_EQ_#NAME#_MM : MMRel, C_COND_FT<"eq", TypeStr, RC, itin>,
C_COND_FM_MM<fmt, 2> {
let BaseOpcode = "c.eq."#NAME;
let isCommutable = 1;
}
def C_UEQ_#NAME#_MM : MMRel, C_COND_FT<"ueq", TypeStr, RC, itin>,
C_COND_FM_MM<fmt, 3> {
let BaseOpcode = "c.ueq."#NAME;
let isCommutable = 1;
}
def C_OLT_#NAME#_MM : MMRel, C_COND_FT<"olt", TypeStr, RC, itin>,
C_COND_FM_MM<fmt, 4> {
let BaseOpcode = "c.olt."#NAME;
}
def C_ULT_#NAME#_MM : MMRel, C_COND_FT<"ult", TypeStr, RC, itin>,
C_COND_FM_MM<fmt, 5> {
let BaseOpcode = "c.ult."#NAME;
}
def C_OLE_#NAME#_MM : MMRel, C_COND_FT<"ole", TypeStr, RC, itin>,
C_COND_FM_MM<fmt, 6> {
let BaseOpcode = "c.ole."#NAME;
}
def C_ULE_#NAME#_MM : MMRel, C_COND_FT<"ule", TypeStr, RC, itin>,
C_COND_FM_MM<fmt, 7> {
let BaseOpcode = "c.ule."#NAME;
}
def C_SF_#NAME#_MM : MMRel, C_COND_FT<"sf", TypeStr, RC, itin>,
C_COND_FM_MM<fmt, 8> {
let BaseOpcode = "c.sf."#NAME;
let isCommutable = 1;
}
def C_NGLE_#NAME#_MM : MMRel, C_COND_FT<"ngle", TypeStr, RC, itin>,
C_COND_FM_MM<fmt, 9> {
let BaseOpcode = "c.ngle."#NAME;
}
def C_SEQ_#NAME#_MM : MMRel, C_COND_FT<"seq", TypeStr, RC, itin>,
C_COND_FM_MM<fmt, 10> {
let BaseOpcode = "c.seq."#NAME;
let isCommutable = 1;
}
def C_NGL_#NAME#_MM : MMRel, C_COND_FT<"ngl", TypeStr, RC, itin>,
C_COND_FM_MM<fmt, 11> {
let BaseOpcode = "c.ngl."#NAME;
}
def C_LT_#NAME#_MM : MMRel, C_COND_FT<"lt", TypeStr, RC, itin>,
C_COND_FM_MM<fmt, 12> {
let BaseOpcode = "c.lt."#NAME;
}
def C_NGE_#NAME#_MM : MMRel, C_COND_FT<"nge", TypeStr, RC, itin>,
C_COND_FM_MM<fmt, 13> {
let BaseOpcode = "c.nge."#NAME;
}
def C_LE_#NAME#_MM : MMRel, C_COND_FT<"le", TypeStr, RC, itin>,
C_COND_FM_MM<fmt, 14> {
let BaseOpcode = "c.le."#NAME;
}
def C_NGT_#NAME#_MM : MMRel, C_COND_FT<"ngt", TypeStr, RC, itin>,
C_COND_FM_MM<fmt, 15> {
let BaseOpcode = "c.ngt."#NAME;
}
}
defm S : C_COND_MM<"s", FGR32Opnd, 0b00, II_C_CC_S>,
ISA_MIPS1_NOT_32R6_64R6;
defm D32 : C_COND_MM<"d", AFGR64Opnd, 0b01, II_C_CC_D>,
ISA_MIPS1_NOT_32R6_64R6, FGR_32;
let DecoderNamespace = "Mips64" in
defm D64 : C_COND_MM<"d", FGR64Opnd, 0b01, II_C_CC_D>,
ISA_MIPS1_NOT_32R6_64R6, FGR_64;
defm S_MM : C_COND_ALIASES<"s", FGR32Opnd>, HARDFLOAT,
ISA_MIPS1_NOT_32R6_64R6;
defm D32_MM : C_COND_ALIASES<"d", AFGR64Opnd>, HARDFLOAT,
ISA_MIPS1_NOT_32R6_64R6, FGR_32;
defm D64_MM : C_COND_ALIASES<"d", FGR64Opnd>, HARDFLOAT,
ISA_MIPS1_NOT_32R6_64R6, FGR_64;
defm : BC1_ALIASES<BC1T_MM, "bc1t", BC1F_MM, "bc1f">,
ISA_MIPS1_NOT_32R6_64R6, HARDFLOAT;
[mips][microMIPS] Implement LDC1, SDC1, LDC2, SDC2, LWC1, SWC1, LWC2 and SWC2 instructions and add CodeGen support Differential Revision: http://reviews.llvm.org/D18824 llvm-svn: 275050
2016-07-11 15:41:56 +08:00
}
//===----------------------------------------------------------------------===//
// Floating Point Patterns
//===----------------------------------------------------------------------===//
let AdditionalPredicates = [InMicroMips] in {
// Patterns for loads/stores with a reg+imm operand.
let AddedComplexity = 40 in {
def : LoadRegImmPat<LDC1_MM, f64, load>, FGR_32;
def : StoreRegImmPat<SDC1_MM, f64>, FGR_32;
def : LoadRegImmPat<LWC1_MM, f32, load>;
def : StoreRegImmPat<SWC1_MM, f32>;
}
[mips][microMIPS] Implement ABS.fmt, CEIL.L.fmt, CEIL.W.fmt, FLOOR.L.fmt, FLOOR.W.fmt, TRUNC.L.fmt, TRUNC.W.fmt, RSQRT.fmt and SQRT.fmt instructions Differential Revision: http://reviews.llvm.org/D11674 llvm-svn: 246968
2015-09-07 21:01:04 +08:00
}